Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206309
S. Tawfik, V. Kursun
Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay, setup time, leakage power consumption, layout area, and static noise margin. The clock power is minimized with the multi-Vth latches that combine the independent-gate bias and gate underlap engineering techniques. Alternatively, the total active mode power and the leakage power are minimized with the multi-Vth latches that combine the independent-gate bias and work-function engineering techniques. With the multi-Vth latches, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 50.3%, 22%, and 47%, respectively, while maintaining similar speed and data stability as compared to the standard single-Vth circuits. Furthermore, the area is reduced by up to 21% with the multi-Vth latches as compared to the circuits with single-Vth tied-gate transistors in a 32nm FinFET technology. The FinFET latches with gate-drain/source overlap engineering are easier to implement with fewer processing steps as compared to the previously published latches based on independent-gate bias and work-function engineering.
{"title":"Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches","authors":"S. Tawfik, V. Kursun","doi":"10.1109/ASQED.2009.5206309","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206309","url":null,"abstract":"Various circuit topologies and FinFET technology options for implementing brute-force latches are explored in this paper. New low-power multi-threshold voltage (multi-Vth) FinFET brute force latches based on gate-drain/source overlap engineering and independent-gate bias are proposed. Different brute-force latches are characterized and compared for active mode power consumption, propagation delay, setup time, leakage power consumption, layout area, and static noise margin. The clock power is minimized with the multi-Vth latches that combine the independent-gate bias and gate underlap engineering techniques. Alternatively, the total active mode power and the leakage power are minimized with the multi-Vth latches that combine the independent-gate bias and work-function engineering techniques. With the multi-Vth latches, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 50.3%, 22%, and 47%, respectively, while maintaining similar speed and data stability as compared to the standard single-Vth circuits. Furthermore, the area is reduced by up to 21% with the multi-Vth latches as compared to the circuits with single-Vth tied-gate transistors in a 32nm FinFET technology. The FinFET latches with gate-drain/source overlap engineering are easier to implement with fewer processing steps as compared to the previously published latches based on independent-gate bias and work-function engineering.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206296
F. Tan
Worst case graphics core power delivery noise is a major indicator of graphics chip performance. The design of good graphics core power delivery network (PDN) is technically difficult because it is not easy to predict a worst case current stimulus during pre-silicon design stage. Many times, the worst case power delivery noise is observed when graphics benchmark software is run during post-silicon validation. At times like this, it is too late to rectify the power delivery noise issue unless many extra capacitor placeholders are placed during early design stage. To intelligently optimize the graphics core power delivery network design and determining the right amount of decoupling capacitors, this paper suggests an approach that setup a working platform to capture the worst case power delivery noise; and later re-construct the worst case power delivery current using Thevenin's Theorem. The measurement is based on actual gaming application instead of engineering a special stimulus that is generated thru millions of logic test-vectors. This approach is practical, direct and quick, and does not need huge computing resources; or technically skilled logic designers to design algorithms to build the stimulus.
{"title":"Measurement of worst-case power delivery noise and construction of worst case current for graphics core simulation","authors":"F. Tan","doi":"10.1109/ASQED.2009.5206296","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206296","url":null,"abstract":"Worst case graphics core power delivery noise is a major indicator of graphics chip performance. The design of good graphics core power delivery network (PDN) is technically difficult because it is not easy to predict a worst case current stimulus during pre-silicon design stage. Many times, the worst case power delivery noise is observed when graphics benchmark software is run during post-silicon validation. At times like this, it is too late to rectify the power delivery noise issue unless many extra capacitor placeholders are placed during early design stage. To intelligently optimize the graphics core power delivery network design and determining the right amount of decoupling capacitors, this paper suggests an approach that setup a working platform to capture the worst case power delivery noise; and later re-construct the worst case power delivery current using Thevenin's Theorem. The measurement is based on actual gaming application instead of engineering a special stimulus that is generated thru millions of logic test-vectors. This approach is practical, direct and quick, and does not need huge computing resources; or technically skilled logic designers to design algorithms to build the stimulus.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117092229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206262
I. Bhattacharya, S. Foo
Multijunction solar cells direct sunlight towards matched spectral sensitivity by splitting the spectrum into smaller slices. The main challenge in the photovoltaic industry is to make the modules more cost effective. The high efficiency multijunction photovoltaics have played a very significant role in reducing the cost through concentrator photovoltaic systems being implemented around the world. For example National Renewable Energy Laboratory (NREL) and US Department of Energy (DOE) have funded several III–IV multijunction solar cell projects. In this paper we have introduced a new multijunction photovoltaic cell based upon InP/InGaAs/InGaSb, and performed a comparison of solar energy absorption, reflection and transmission with existing single-junction and multijunction cells being deployed around the world. The inclusion of InGaSb layer in the design has made a significant difference in absorption in the spectral range of 598nm-800nm, contributing to a higher efficiency of the solar cell.
{"title":"Indium phosphide, indium-gallium-arsenide and indium-gallium-antimonide based high efficiency multijunction photovoltaics for solar energy harvesting","authors":"I. Bhattacharya, S. Foo","doi":"10.1109/ASQED.2009.5206262","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206262","url":null,"abstract":"Multijunction solar cells direct sunlight towards matched spectral sensitivity by splitting the spectrum into smaller slices. The main challenge in the photovoltaic industry is to make the modules more cost effective. The high efficiency multijunction photovoltaics have played a very significant role in reducing the cost through concentrator photovoltaic systems being implemented around the world. For example National Renewable Energy Laboratory (NREL) and US Department of Energy (DOE) have funded several III–IV multijunction solar cell projects. In this paper we have introduced a new multijunction photovoltaic cell based upon InP/InGaAs/InGaSb, and performed a comparison of solar energy absorption, reflection and transmission with existing single-junction and multijunction cells being deployed around the world. The inclusion of InGaSb layer in the design has made a significant difference in absorption in the spectral range of 598nm-800nm, contributing to a higher efficiency of the solar cell.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206281
U. Hashim, M. N. Haron
This paper describes the digital display system using Peripheral Interface Controller (PIC) microcontroller. The research is conducted in-house at the university microelectronic and nanotechnology research cluster well equipped with electrical instruments and electronic equipments. This paper focuses on the design of schematic circuit for digital display system using PIC microcontroller and development of programming for PIC microcontroller. Digital display system is the most popular technology and most compatible with the embedded system devices. The system is a variable device that is easily adapted to a wide range of agriculture, chemical, biochemical and biomedical measurements. The operation of this system is based on the analogue value in term of electrical conducted by Ionic Sensitive Field Effect Transistor (ISFET) pH sensor and display the captured data using PIC microcontroller. As a result of this process, the threshold voltage of the ISFET is modulated and it will be converted as the value of pH on digital display system. This paper also highlights the research on ISFET and deals with the fundamental issue: fabrication of ISFET using CMOS technology. The ISFET compatible layout will be presented and the ISFET process flow will be discussed.
{"title":"Design of digital display system for ISFET pH sensor by using PIC microcontroller Unit (MCU)","authors":"U. Hashim, M. N. Haron","doi":"10.1109/ASQED.2009.5206281","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206281","url":null,"abstract":"This paper describes the digital display system using Peripheral Interface Controller (PIC) microcontroller. The research is conducted in-house at the university microelectronic and nanotechnology research cluster well equipped with electrical instruments and electronic equipments. This paper focuses on the design of schematic circuit for digital display system using PIC microcontroller and development of programming for PIC microcontroller. Digital display system is the most popular technology and most compatible with the embedded system devices. The system is a variable device that is easily adapted to a wide range of agriculture, chemical, biochemical and biomedical measurements. The operation of this system is based on the analogue value in term of electrical conducted by Ionic Sensitive Field Effect Transistor (ISFET) pH sensor and display the captured data using PIC microcontroller. As a result of this process, the threshold voltage of the ISFET is modulated and it will be converted as the value of pH on digital display system. This paper also highlights the research on ISFET and deals with the fundamental issue: fabrication of ISFET using CMOS technology. The ISFET compatible layout will be presented and the ISFET process flow will be discussed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128458299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206264
M. Ooi, Y. C. Kang, W. J. Tee, A. A. Mohanan, Chris Chan
It is widely observed in the industry that defective dies tend to occur in groups of systematic pattern. These are so-called defect clusters. There are many proposed methods to achieve cluster classification and recognition with different degree of accuracy and limitations. Many of these methods, although powerful, generally do not actually detect the presence/absence of a cluster but simply segments them and then attempts to calculate the validity of the segment. Thus, they fail to be flexible and accurate because they implicitly assume that the problem is singular: identify the defect clusters, when in actuality, the problem of defect cluster identification can be divided into three distinct stages: detection, segmentation and recognition. This paper proposes the use of joint-count statistics to perform the sole task of defect cluster detection. It is recommended that segmentation and recognition be performed after the detetion algoritm completed to a satisfactory level.
{"title":"Accurate defect cluster detection and localisation on fabricated semiconductor wafters using joint count statistics","authors":"M. Ooi, Y. C. Kang, W. J. Tee, A. A. Mohanan, Chris Chan","doi":"10.1109/ASQED.2009.5206264","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206264","url":null,"abstract":"It is widely observed in the industry that defective dies tend to occur in groups of systematic pattern. These are so-called defect clusters. There are many proposed methods to achieve cluster classification and recognition with different degree of accuracy and limitations. Many of these methods, although powerful, generally do not actually detect the presence/absence of a cluster but simply segments them and then attempts to calculate the validity of the segment. Thus, they fail to be flexible and accurate because they implicitly assume that the problem is singular: identify the defect clusters, when in actuality, the problem of defect cluster identification can be divided into three distinct stages: detection, segmentation and recognition. This paper proposes the use of joint-count statistics to perform the sole task of defect cluster detection. It is recommended that segmentation and recognition be performed after the detetion algoritm completed to a satisfactory level.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132970015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206280
Brahmantyo Heruseto, E. Prasetyo, Hamzah Afandi, M. Paindavoine
Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network.
{"title":"Embedded Analog CMOS Neural Network inside high speed camera","authors":"Brahmantyo Heruseto, E. Prasetyo, Hamzah Afandi, M. Paindavoine","doi":"10.1109/ASQED.2009.5206280","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206280","url":null,"abstract":"Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123882190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206239
Zhiping Yu, Litian Liu, Zhaohua Zhang, James Y. Yang, R. Liu, Yafei Bi
A new temperature insensitive digital pressure-sensing device with filtered frequency output using ring oscillator and mixer is presented. It employs the Micro-ElectroMechanical Systems (MEMS) technologies to form pressure sensing using PMOS ring oscillators to generate frequency which depends on the pressure-induced stress. The digital pressure sensor has several advantages. One of them is the very low temperature coefficient and simple fabrication process. Another one is to convert the analog measurement of pressures into the frequency measurement. Compared to a direct pressure measurement, it is much more convenient and easier to conduct the frequency measurement with digital circuits. Since the ring resonators are exposed to the change of the pressure, the structure is significantly simplified as no shielding protections of the sensor from the pressure are required.
{"title":"Digital pressure sensor with filtered frequency output using ring oscillator and mixer","authors":"Zhiping Yu, Litian Liu, Zhaohua Zhang, James Y. Yang, R. Liu, Yafei Bi","doi":"10.1109/ASQED.2009.5206239","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206239","url":null,"abstract":"A new temperature insensitive digital pressure-sensing device with filtered frequency output using ring oscillator and mixer is presented. It employs the Micro-ElectroMechanical Systems (MEMS) technologies to form pressure sensing using PMOS ring oscillators to generate frequency which depends on the pressure-induced stress. The digital pressure sensor has several advantages. One of them is the very low temperature coefficient and simple fabrication process. Another one is to convert the analog measurement of pressures into the frequency measurement. Compared to a direct pressure measurement, it is much more convenient and easier to conduct the frequency measurement with digital circuits. Since the ring resonators are exposed to the change of the pressure, the structure is significantly simplified as no shielding protections of the sensor from the pressure are required.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206297
Hailong Jiao, V. Kursun
Ground bouncing noise produced during the sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware MTCMOS circuit techniques to deal with the ground bouncing noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by up to 69.17% with the noise-aware MTCMOS circuits without sacrificing the savings in leakage power consumption as compared to the standard MTCMOS circuits in a 90nm CMOS technology.
{"title":"Ground bouncing noise suppression techniques for MTCMOS circuits","authors":"Hailong Jiao, V. Kursun","doi":"10.1109/ASQED.2009.5206297","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206297","url":null,"abstract":"Ground bouncing noise produced during the sleep to active mode transitions is an important challenge in Multi-Threshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware MTCMOS circuit techniques to deal with the ground bouncing noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual ground line to the real ground distribution network during the sleep to active mode transitions. The peak amplitude of the ground bouncing noise is reduced by up to 69.17% with the noise-aware MTCMOS circuits without sacrificing the savings in leakage power consumption as compared to the standard MTCMOS circuits in a 90nm CMOS technology.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125087235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206260
S. Tawfik, V. Kursun
The influence of different device parameters on the electrical characteristics of n-channel and p-channel symmetric double-gate FinFETs is studied in this paper. Guidelines for enhancing the performance and suppressing the leakage currents are provided. A sub-threshold slope lower than 100mV is achieved at the room temperature with fins thinner than half the gate length in a 32nm FinFET technology. The maximum on-current to leakage current ratio of n-channel FinFETs at room temperature is achieved when the fin thickness and the gate-oxide thickness are 8nm and 1.6nm, respectively. Alternatively, the on-current to leakage currents ratio of p-channel FinFETs is maximized when the fin thickness and the gate-oxide thickness are 8nm and 1.2nm, respectively.
{"title":"Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs","authors":"S. Tawfik, V. Kursun","doi":"10.1109/ASQED.2009.5206260","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206260","url":null,"abstract":"The influence of different device parameters on the electrical characteristics of n-channel and p-channel symmetric double-gate FinFETs is studied in this paper. Guidelines for enhancing the performance and suppressing the leakage currents are provided. A sub-threshold slope lower than 100mV is achieved at the room temperature with fins thinner than half the gate length in a 32nm FinFET technology. The maximum on-current to leakage current ratio of n-channel FinFETs at room temperature is achieved when the fin thickness and the gate-oxide thickness are 8nm and 1.6nm, respectively. Alternatively, the on-current to leakage currents ratio of p-channel FinFETs is maximized when the fin thickness and the gate-oxide thickness are 8nm and 1.2nm, respectively.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133299169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-15DOI: 10.1109/ASQED.2009.5206269
B. Y. Low, Ravishankar Freescale
This paper focuses on how the PBGA (plastic ball grid array) organic substrate structure and traces design improve the assembly packaging robustness. Via plugging process at the substrate fabrication has been studied. Comparison of substrate without via plug, laminate substrate with via plugging process increases the overall hardness of the substrate. This is due to the via plug materials use (IR6) is a harder materials than the solder resist. Another area of study is the addition of dummy traces design on the air venting area improves the solder resist evenness by elimination mold resin bleed.
{"title":"How organic substrate structure & design improve assembly robustness","authors":"B. Y. Low, Ravishankar Freescale","doi":"10.1109/ASQED.2009.5206269","DOIUrl":"https://doi.org/10.1109/ASQED.2009.5206269","url":null,"abstract":"This paper focuses on how the PBGA (plastic ball grid array) organic substrate structure and traces design improve the assembly packaging robustness. Via plugging process at the substrate fabrication has been studied. Comparison of substrate without via plug, laminate substrate with via plugging process increases the overall hardness of the substrate. This is due to the via plug materials use (IR6) is a harder materials than the solder resist. Another area of study is the addition of dummy traces design on the air venting area improves the solder resist evenness by elimination mold resin bleed.","PeriodicalId":437303,"journal":{"name":"2009 1st Asia Symposium on Quality Electronic Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133690345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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