The field of embedded systems is in full expansion. However, the design of these systems stemming from a high abstraction level remains challenging, causing the industry to continuously search for more powerful tools and environments for the design of such systems. This work presents a platform for the refinement of OS services. This platform enables early exploration without requiring the synthesis of an OS' port for a particular architecture and does not require knowing the different APIs from this operating system. By gradual refinements through different abstractions, this platform enables the designers to choose the operating system ideally suited for the targeted embedded application. These various refinement layers can interact with HDLs (VHDL, Verilog) and SLDLs (SystemC, eSYS.net), thus enabling an environment for hardware/software system design. For the platform development we exploited the strength of .NET.
{"title":"A platform for refinement of OS services for embedded systems","authors":"B. Girodias, E. Aboulhamid, G. Nicolescu","doi":"10.1109/DELTA.2006.97","DOIUrl":"https://doi.org/10.1109/DELTA.2006.97","url":null,"abstract":"The field of embedded systems is in full expansion. However, the design of these systems stemming from a high abstraction level remains challenging, causing the industry to continuously search for more powerful tools and environments for the design of such systems. This work presents a platform for the refinement of OS services. This platform enables early exploration without requiring the synthesis of an OS' port for a particular architecture and does not require knowing the different APIs from this operating system. By gradual refinements through different abstractions, this platform enables the designers to choose the operating system ideally suited for the targeted embedded application. These various refinement layers can interact with HDLs (VHDL, Verilog) and SLDLs (SystemC, eSYS.net), thus enabling an environment for hardware/software system design. For the platform development we exploited the strength of .NET.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto
Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.
{"title":"Automatic March tests generation for multi-port SRAMs","authors":"A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/DELTA.2006.17","DOIUrl":"https://doi.org/10.1109/DELTA.2006.17","url":null,"abstract":"Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The condition monitoring of on-load tap changers is very important because they have proved to be the elements with noticeable failures in a power transformer. This article describes the development of a portable virtual instrument for monitoring this kind of elements. The monitoring task is based in the measurement and analysis of the vibrations that a tap change produces. In contrast with other methods that can be used, this one has the advantage of being able to do continuous monitoring because the transformer can be operated on line.
{"title":"Virtual instrument for condition monitoring of on-load tap changers","authors":"F. Poza, P. M. Espiñeira, S. Otero, F. Machado","doi":"10.1109/DELTA.2006.96","DOIUrl":"https://doi.org/10.1109/DELTA.2006.96","url":null,"abstract":"The condition monitoring of on-load tap changers is very important because they have proved to be the elements with noticeable failures in a power transformer. This article describes the development of a portable virtual instrument for monitoring this kind of elements. The monitoring task is based in the measurement and analysis of the vibrations that a tap change produces. In contrast with other methods that can be used, this one has the advantage of being able to do continuous monitoring because the transformer can be operated on line.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121191974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz.
{"title":"Full field image ranger hardware","authors":"A. Payne, D. Carnegie, A. Dorrington, M. Cree","doi":"10.1109/DELTA.2006.50","DOIUrl":"https://doi.org/10.1109/DELTA.2006.50","url":null,"abstract":"We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134138190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a sensor fault tolerance control scheme that is applied to a double inverted pendulum. Sensor faults will affect the system when it is used in closed-loop feedback. The scheme uses a linear observer reconstruct the sensor fault and to subtract the reconstruction from the faulty sensor. The net result is then used for the closed-loop feedback. It was found that the scheme restored the performance to the fault-free scenario
{"title":"Tolerance towards sensor failures: an application to a double inverted pendulum","authors":"K. Y. Ng, Chee Pin Tan, Rini Akmeliawati","doi":"10.1109/DELTA.2006.92","DOIUrl":"https://doi.org/10.1109/DELTA.2006.92","url":null,"abstract":"In this paper we present a sensor fault tolerance control scheme that is applied to a double inverted pendulum. Sensor faults will affect the system when it is used in closed-loop feedback. The scheme uses a linear observer reconstruct the sensor fault and to subtract the reconstruction from the faulty sensor. The net result is then used for the closed-loop feedback. It was found that the scheme restored the performance to the fault-free scenario","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The electromagnetic response of three different types of planar interdigital sensors to pork meat has been studied and their comparative responses are reported. The sensors can be used effectively for the quality testing of pork meat. The amount of fat content can be predicted. The details of the fabricated sensors and experimental results are reported.
{"title":"Comparison of electromagnetic response of planar interdigital sensors: quality testing of pork meat","authors":"S. C. Mukhopadhyay, C. Gooneratne","doi":"10.1109/DELTA.2006.24","DOIUrl":"https://doi.org/10.1109/DELTA.2006.24","url":null,"abstract":"The electromagnetic response of three different types of planar interdigital sensors to pork meat has been studied and their comparative responses are reported. The sensors can be used effectively for the quality testing of pork meat. The amount of fat content can be predicted. The details of the fabricated sensors and experimental results are reported.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).
{"title":"Evaluation of a software-based error detection technique by RT-level fault injection","authors":"A. Ammari, R. Leveugle, B. Nicolescu, Y. Savaria","doi":"10.1109/DELTA.2006.46","DOIUrl":"https://doi.org/10.1109/DELTA.2006.46","url":null,"abstract":"This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128337905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the algorithm. To aid in the process this paper details the application of design patterns to image processing algorithm development. Design patterns embody experience and through reuse provide tools for solving particular mapping problems. The effectiveness of design patterns for overcoming constraints in the mapping process is illustrated in the context of a real world example that focuses on the development of a real-time object tracking algorithm implemented on an FPGA.
{"title":"Using design patterns to overcome image processing constraints on FPGAs","authors":"K. T. Gribbon, D. Bailey, C. T. Johnston","doi":"10.1109/DELTA.2006.93","DOIUrl":"https://doi.org/10.1109/DELTA.2006.93","url":null,"abstract":"The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the algorithm. To aid in the process this paper details the application of design patterns to image processing algorithm development. Design patterns embody experience and through reuse provide tools for solving particular mapping problems. The effectiveness of design patterns for overcoming constraints in the mapping process is illustrated in the context of a real world example that focuses on the development of a real-time object tracking algorithm implemented on an FPGA.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128537706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example
{"title":"Synthesis of fault-tolerant embedded systems with checkpointing and replication","authors":"V. Izosimov, P. Pop, P. Eles, Zebo Peng","doi":"10.1109/delta.2006.83","DOIUrl":"https://doi.org/10.1109/delta.2006.83","url":null,"abstract":"We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129485216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper deals with the problem of on-line diagnosis of computer systems. It is based on three monitoring techniques related to system event logging, performance and resource usage measurements. This approach is illustrated with practical results.
{"title":"On-line monitoring of computer systems","authors":"J. Sosnowski, Marek Poleszak","doi":"10.1109/DELTA.2006.71","DOIUrl":"https://doi.org/10.1109/DELTA.2006.71","url":null,"abstract":"The paper deals with the problem of on-line diagnosis of computer systems. It is based on three monitoring techniques related to system event logging, performance and resource usage measurements. This approach is illustrated with practical results.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129237579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：