The field of embedded systems is in full expansion. However, the design of these systems stemming from a high abstraction level remains challenging, causing the industry to continuously search for more powerful tools and environments for the design of such systems. This work presents a platform for the refinement of OS services. This platform enables early exploration without requiring the synthesis of an OS' port for a particular architecture and does not require knowing the different APIs from this operating system. By gradual refinements through different abstractions, this platform enables the designers to choose the operating system ideally suited for the targeted embedded application. These various refinement layers can interact with HDLs (VHDL, Verilog) and SLDLs (SystemC, eSYS.net), thus enabling an environment for hardware/software system design. For the platform development we exploited the strength of .NET.
{"title":"A platform for refinement of OS services for embedded systems","authors":"B. Girodias, E. Aboulhamid, G. Nicolescu","doi":"10.1109/DELTA.2006.97","DOIUrl":"https://doi.org/10.1109/DELTA.2006.97","url":null,"abstract":"The field of embedded systems is in full expansion. However, the design of these systems stemming from a high abstraction level remains challenging, causing the industry to continuously search for more powerful tools and environments for the design of such systems. This work presents a platform for the refinement of OS services. This platform enables early exploration without requiring the synthesis of an OS' port for a particular architecture and does not require knowing the different APIs from this operating system. By gradual refinements through different abstractions, this platform enables the designers to choose the operating system ideally suited for the targeted embedded application. These various refinement layers can interact with HDLs (VHDL, Verilog) and SLDLs (SystemC, eSYS.net), thus enabling an environment for hardware/software system design. For the platform development we exploited the strength of .NET.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto
Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.
{"title":"Automatic March tests generation for multi-port SRAMs","authors":"A. Benso, A. Bosio, S. Carlo, G. D. Natale, P. Prinetto","doi":"10.1109/DELTA.2006.17","DOIUrl":"https://doi.org/10.1109/DELTA.2006.17","url":null,"abstract":"Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The condition monitoring of on-load tap changers is very important because they have proved to be the elements with noticeable failures in a power transformer. This article describes the development of a portable virtual instrument for monitoring this kind of elements. The monitoring task is based in the measurement and analysis of the vibrations that a tap change produces. In contrast with other methods that can be used, this one has the advantage of being able to do continuous monitoring because the transformer can be operated on line.
{"title":"Virtual instrument for condition monitoring of on-load tap changers","authors":"F. Poza, P. M. Espiñeira, S. Otero, F. Machado","doi":"10.1109/DELTA.2006.96","DOIUrl":"https://doi.org/10.1109/DELTA.2006.96","url":null,"abstract":"The condition monitoring of on-load tap changers is very important because they have proved to be the elements with noticeable failures in a power transformer. This article describes the development of a portable virtual instrument for monitoring this kind of elements. The monitoring task is based in the measurement and analysis of the vibrations that a tap change produces. In contrast with other methods that can be used, this one has the advantage of being able to do continuous monitoring because the transformer can be operated on line.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121191974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a sensor fault tolerance control scheme that is applied to a double inverted pendulum. Sensor faults will affect the system when it is used in closed-loop feedback. The scheme uses a linear observer reconstruct the sensor fault and to subtract the reconstruction from the faulty sensor. The net result is then used for the closed-loop feedback. It was found that the scheme restored the performance to the fault-free scenario
{"title":"Tolerance towards sensor failures: an application to a double inverted pendulum","authors":"K. Y. Ng, Chee Pin Tan, Rini Akmeliawati","doi":"10.1109/DELTA.2006.92","DOIUrl":"https://doi.org/10.1109/DELTA.2006.92","url":null,"abstract":"In this paper we present a sensor fault tolerance control scheme that is applied to a double inverted pendulum. Sensor faults will affect the system when it is used in closed-loop feedback. The scheme uses a linear observer reconstruct the sensor fault and to subtract the reconstruction from the faulty sensor. The net result is then used for the closed-loop feedback. It was found that the scheme restored the performance to the fault-free scenario","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VertiCal is a calibration system for eSys, a family of 32-bit automotive microcontrollers based on the PowerPC architecture. To utilize the calibration system, a common scale package among the derivatives is required and a table of universal pin locations including the calibration pins is properly defined. However, the inclusion of the calibration pins has induced an uncommon structure where two balls in the package are sharing a pad on the die. This structure has created some test challenges. This paper discusses in detail the problem, followed by approaches in analysis and experimental results
{"title":"VertiCal, a universal calibration system for eSys high performance 32-bit PowerPC microcontrollers; test challenges & solution","authors":"Joon Huang Chuah, J. Knight","doi":"10.1109/DELTA.2006.95","DOIUrl":"https://doi.org/10.1109/DELTA.2006.95","url":null,"abstract":"VertiCal is a calibration system for eSys, a family of 32-bit automotive microcontrollers based on the PowerPC architecture. To utilize the calibration system, a common scale package among the derivatives is required and a table of universal pin locations including the calibration pins is properly defined. However, the inclusion of the calibration pins has induced an uncommon structure where two balls in the package are sharing a pad on the die. This structure has created some test challenges. This paper discusses in detail the problem, followed by approaches in analysis and experimental results","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":" 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113948389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The electromagnetic response of three different types of planar interdigital sensors to pork meat has been studied and their comparative responses are reported. The sensors can be used effectively for the quality testing of pork meat. The amount of fat content can be predicted. The details of the fabricated sensors and experimental results are reported.
{"title":"Comparison of electromagnetic response of planar interdigital sensors: quality testing of pork meat","authors":"S. C. Mukhopadhyay, C. Gooneratne","doi":"10.1109/DELTA.2006.24","DOIUrl":"https://doi.org/10.1109/DELTA.2006.24","url":null,"abstract":"The electromagnetic response of three different types of planar interdigital sensors to pork meat has been studied and their comparative responses are reported. The sensors can be used effectively for the quality testing of pork meat. The amount of fat content can be predicted. The details of the fabricated sensors and experimental results are reported.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper deals with the problem of on-line diagnosis of computer systems. It is based on three monitoring techniques related to system event logging, performance and resource usage measurements. This approach is illustrated with practical results.
{"title":"On-line monitoring of computer systems","authors":"J. Sosnowski, Marek Poleszak","doi":"10.1109/DELTA.2006.71","DOIUrl":"https://doi.org/10.1109/DELTA.2006.71","url":null,"abstract":"The paper deals with the problem of on-line diagnosis of computer systems. It is based on three monitoring techniques related to system event logging, performance and resource usage measurements. This approach is illustrated with practical results.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129237579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example
{"title":"Synthesis of fault-tolerant embedded systems with checkpointing and replication","authors":"V. Izosimov, P. Pop, P. Eles, Zebo Peng","doi":"10.1109/delta.2006.83","DOIUrl":"https://doi.org/10.1109/delta.2006.83","url":null,"abstract":"We present an approach to the synthesis of fault-tolerant hard real-time systems for safety-critical applications. We use checkpointing with rollback recovery and active replication for tolerating transient faults. Processes are statically scheduled and communications are performed using the time-triggered protocol. Our synthesis approach decides the assignment of fault-tolerance policies to processes, the optimal placement of checkpoints and the mapping of processes to processors such that transient faults are tolerated and the timing constraints of the application are satisfied. We present several synthesis algorithms which are able to find fault-tolerant implementations given a limited amount of resources. The developed algorithms are evaluated using extensive experiments, including a real-life example","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129485216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the algorithm. To aid in the process this paper details the application of design patterns to image processing algorithm development. Design patterns embody experience and through reuse provide tools for solving particular mapping problems. The effectiveness of design patterns for overcoming constraints in the mapping process is illustrated in the context of a real world example that focuses on the development of a real-time object tracking algorithm implemented on an FPGA.
{"title":"Using design patterns to overcome image processing constraints on FPGAs","authors":"K. T. Gribbon, D. Bailey, C. T. Johnston","doi":"10.1109/DELTA.2006.93","DOIUrl":"https://doi.org/10.1109/DELTA.2006.93","url":null,"abstract":"The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resources of the system. These constraints often force the designer to reformulate the algorithm. To aid in the process this paper details the application of design patterns to image processing algorithm development. Design patterns embody experience and through reuse provide tools for solving particular mapping problems. The effectiveness of design patterns for overcoming constraints in the mapping process is illustrated in the context of a real world example that focuses on the development of a real-time object tracking algorithm implemented on an FPGA.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128537706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent introduction of the open semiconductor test architecture (OPENSTAR) by the semiconductor test consortium and on-going proliferation of the modular instrumentation and measurement systems in the area of industrial automation, including testing (in particular, mixed-signal device testing) make it necessary to look at and perhaps to revise the contents of the electronic test education programs of tertiary institutions. Even though the instrumentation and measurement systems and automatic test equipment (ATE) are close to each other in terms of their target functions, there are still quite different in their implementation, characteristics and application. And both the commonalities and differences have to be addressed when designing and delivering undergraduate and graduate courses on electronic test technology and practical test engineering.
{"title":"Electronic test technology curriculum revisiting","authors":"S. Demidenko, W. Moorhead","doi":"10.1109/DELTA.2006.43","DOIUrl":"https://doi.org/10.1109/DELTA.2006.43","url":null,"abstract":"Recent introduction of the open semiconductor test architecture (OPENSTAR) by the semiconductor test consortium and on-going proliferation of the modular instrumentation and measurement systems in the area of industrial automation, including testing (in particular, mixed-signal device testing) make it necessary to look at and perhaps to revise the contents of the electronic test education programs of tertiary institutions. Even though the instrumentation and measurement systems and automatic test equipment (ATE) are close to each other in terms of their target functions, there are still quite different in their implementation, characteristics and application. And both the commonalities and differences have to be addressed when designing and delivering undergraduate and graduate courses on electronic test technology and practical test engineering.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128862278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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