Conventional sigma-delta (SigmaDelta) analog-to-digital (AD) converters are based on an active analog SigmaDelta modulator followed by a digital filter. In earlier papers we proposed a new architecture for a first-order SigmaDelta modulator that needs no active analog components. Its advantage is that AD converters can be implemented within FPGAs or directly in the software of microprocessors. Its disadvantage is, however, that it realizes a lossy SigmaDelta modulator with an accompanying limited resolution. Here we propose to use dither-injection to relax that resolution limitation and we present simulation results showing that our ideas work
{"title":"Using dither to improve the performance of lossy sigma-delta modulators","authors":"J. Goette, M. Jacomet, M. Hager","doi":"10.1109/DELTA.2006.94","DOIUrl":"https://doi.org/10.1109/DELTA.2006.94","url":null,"abstract":"Conventional sigma-delta (SigmaDelta) analog-to-digital (AD) converters are based on an active analog SigmaDelta modulator followed by a digital filter. In earlier papers we proposed a new architecture for a first-order SigmaDelta modulator that needs no active analog components. Its advantage is that AD converters can be implemented within FPGAs or directly in the software of microprocessors. Its disadvantage is, however, that it realizes a lossy SigmaDelta modulator with an accompanying limited resolution. Here we propose to use dither-injection to relax that resolution limitation and we present simulation results showing that our ideas work","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133665172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In general, it is well known that the induction type magnetic levitation (Maglev) has advantages of a contactless support and a passive control for the levitation and propulsion of a conductive sheet metal. However, heat loss caused by the eddy current inside the sheet metal decreases the efficiency remarkably. In order to use that eddy current more effectively, we have developed a new method for generating quasi-static Lorentz force between the eddy current and additional magnetic flux. In this paper, the basic principles of a new maglev method and evaluation of the total levitation forces by finite element analysis are reported
{"title":"Analytical study on a new induction type magnetic levitation system creating quasi-static Lorentz forces for a nonmagnetic sheet metal","authors":"T. Ohji, M. Sato, K. Amei, M. Sakui","doi":"10.1109/DELTA.2006.14","DOIUrl":"https://doi.org/10.1109/DELTA.2006.14","url":null,"abstract":"In general, it is well known that the induction type magnetic levitation (Maglev) has advantages of a contactless support and a passive control for the levitation and propulsion of a conductive sheet metal. However, heat loss caused by the eddy current inside the sheet metal decreases the efficiency remarkably. In order to use that eddy current more effectively, we have developed a new method for generating quasi-static Lorentz force between the eddy current and additional magnetic flux. In this paper, the basic principles of a new maglev method and evaluation of the total levitation forces by finite element analysis are reported","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using gas sensor array is widely accepted to overcome the non-selectivity of a single sensor. For tin oxide gas sensors, the size of array can’t be very large due to the limited number of doping materials. In this paper, our experimental results shows that duplication of the sensors doped by the same metal is an efficient way to improve the selectivity of the array due to the fabrication mismatch of the sensor chip. We also compare two methods of reducing the dimension of gas patterns: removing the sensors providing redundant information in the array and using principle component analysis (PCA). The experimental results shows that when the number of components is too large PCA can be a useful tool to reduce the data dimension.
{"title":"Redundancy Analysis for Tin Oxide Gas Sensor Array","authors":"M. Shi, B. Guo, A. Bermak","doi":"10.1109/DELTA.2006.75","DOIUrl":"https://doi.org/10.1109/DELTA.2006.75","url":null,"abstract":"Using gas sensor array is widely accepted to overcome the non-selectivity of a single sensor. For tin oxide gas sensors, the size of array can’t be very large due to the limited number of doping materials. In this paper, our experimental results shows that duplication of the sensors doped by the same metal is an efficient way to improve the selectivity of the array due to the fabrication mismatch of the sensor chip. We also compare two methods of reducing the dimension of gas patterns: removing the sensors providing redundant information in the array and using principle component analysis (PCA). The experimental results shows that when the number of components is too large PCA can be a useful tool to reduce the data dimension.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.
{"title":"Design and simulation of a high performance rail-to-rail CMOS op-amp at /spl plusmn/3V supply","authors":"M. Bhaskaran, S. Sriram, A. Stojcevski, A. Zayegh","doi":"10.1109/DELTA.2006.30","DOIUrl":"https://doi.org/10.1109/DELTA.2006.30","url":null,"abstract":"The paper discusses a CMOS operational amplifier at /spl plusmn/ 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with slew rate of 49.24 V//spl mu/s, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128970773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Bao, S. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin
This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.
{"title":"A low cost, high quality embedded array DFT technique for high performance processors","authors":"Z. Bao, S. Kumar, David M. Wu, Vimal K. Natarajan, Mike Lin","doi":"10.1109/DELTA.2006.5","DOIUrl":"https://doi.org/10.1109/DELTA.2006.5","url":null,"abstract":"This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128655871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Face detection is the process of locating the position where faces are present in an image. Not all proposed face detection methods are suitable for direct hardware implementation. This paper explains a method that utilises the reversible component transformation (RCT) colour space and outlines its transition from a software- to hardware-based implementation. The hardware performance and efficiency of the RCT algorithm is examined using the Xilinx Virtex-II field programmable gate arrays (FPGA). Results show that there is almost negligible difference in performance after transition to hardware and its implementation on FPGA requires 255,416 NAND gates, which is only slightly more than twice the number of NAND gates of a basic video-in application
{"title":"Hardware implementation for face detection on Xilinx Virtex-II FPGA using the reversible component transformation colour space","authors":"M. Ooi","doi":"10.1109/DELTA.2006.52","DOIUrl":"https://doi.org/10.1109/DELTA.2006.52","url":null,"abstract":"Face detection is the process of locating the position where faces are present in an image. Not all proposed face detection methods are suitable for direct hardware implementation. This paper explains a method that utilises the reversible component transformation (RCT) colour space and outlines its transition from a software- to hardware-based implementation. The hardware performance and efficiency of the RCT algorithm is examined using the Xilinx Virtex-II field programmable gate arrays (FPGA). Results show that there is almost negligible difference in performance after transition to hardware and its implementation on FPGA requires 255,416 NAND gates, which is only slightly more than twice the number of NAND gates of a basic video-in application","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"136 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121342356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Since systems-on-chip (SoCs) keep on being more and more complex, test data compression has become essential to reduce test costs. In particular, a common technique for reducing test time is to use multiple scan chains. Nevertheless, this possibility is limited by the number of available ATE (automatic test equipment) channels. In this context, horizontal compression allows to fit the number of available ATE channels with the number of scan chains. But to achieve compression, these methods rely on the presence of don't care bits (X's) in the test sequences. Therefore, the length of these sequences is significantly greater than ones with fully specified bits. Conversely, serialization based methods allow to use fully specified test sequences, that are significantly smaller. This paper first presents a new method for horizontal test data compression and secondly proposes an answer to the question: is there really a benefit in terms of test application time (TAT) and test data volume of using compression instead of a simple serialization of test data?.
{"title":"Fitting ATE channels with scan chains: a comparison between a test data compression technique and serial loading of scan chains","authors":"Julien Dalmasso, M. Flottes, B. Rouzeyre","doi":"10.1109/DELTA.2006.49","DOIUrl":"https://doi.org/10.1109/DELTA.2006.49","url":null,"abstract":"Since systems-on-chip (SoCs) keep on being more and more complex, test data compression has become essential to reduce test costs. In particular, a common technique for reducing test time is to use multiple scan chains. Nevertheless, this possibility is limited by the number of available ATE (automatic test equipment) channels. In this context, horizontal compression allows to fit the number of available ATE channels with the number of scan chains. But to achieve compression, these methods rely on the presence of don't care bits (X's) in the test sequences. Therefore, the length of these sequences is significantly greater than ones with fully specified bits. Conversely, serialization based methods allow to use fully specified test sequences, that are significantly smaller. This paper first presents a new method for horizontal test data compression and secondly proposes an answer to the question: is there really a benefit in terms of test application time (TAT) and test data volume of using compression instead of a simple serialization of test data?.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125926632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tracked mobile robot is popular used in hazardous environments, such as explosives disposal, or removal of dangers. Usually, they work in complex environments and need to cross over different obstacles to reach destination. In this status, the stability and security is very important. In this paper, the dynamic stability of a tracked robot crossing obstacle and up/down stairs is analyzed. The factor of influencing the robot stability is obtained by establishing kinematics and dynamics equations. Two parameters, the maximum angular velocity and the additional front rake, are suggested to be used to describing the status of the robot on stairs. According the results of analysis, the angular velocity is larger, the additional front rake is larger too, resulting in a rather larger impulse between the robot and the stairs, and even falling down the stairs
{"title":"Study on dynamic stability of a tracked robot climbing over an obstacle or descending stairs","authors":"Haijun Mo, P. Huang, Shaowei Wu","doi":"10.1109/DELTA.2006.81","DOIUrl":"https://doi.org/10.1109/DELTA.2006.81","url":null,"abstract":"Tracked mobile robot is popular used in hazardous environments, such as explosives disposal, or removal of dangers. Usually, they work in complex environments and need to cross over different obstacles to reach destination. In this status, the stability and security is very important. In this paper, the dynamic stability of a tracked robot crossing obstacle and up/down stairs is analyzed. The factor of influencing the robot stability is obtained by establishing kinematics and dynamics equations. Two parameters, the maximum angular velocity and the additional front rake, are suggested to be used to describing the status of the robot on stairs. According the results of analysis, the angular velocity is larger, the additional front rake is larger too, resulting in a rather larger impulse between the robot and the stairs, and even falling down the stairs","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128494963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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