We need to communicate with other applications using various methods and when communicating, we need to guarantee delivery. In the .NET environment, we generally use and develop MSMQ which creates outgoing queues for messages waiting to be sent and incoming queues for messages waiting to be received. MSMQ is message-oriented middleware whose queues, according to the developer, are very reliable, simple and more efficient than other skills. However, when developing a huge system, we found out that some problems occur when operating various queues (private/public). This paper shows the results of various tests using MSMQ, such as the status of mqsvc, CPU or memory usage, and whether or not the messages are sent and received. Also, we learned how to use MSMQ in order to develop Message Queuing-based applications.
{"title":"Performance and stability testing of MSMQ in the .NET environment","authors":"Jae-Kyu Chun, Seok-Hyung Cho","doi":"10.1109/DELTA.2006.72","DOIUrl":"https://doi.org/10.1109/DELTA.2006.72","url":null,"abstract":"We need to communicate with other applications using various methods and when communicating, we need to guarantee delivery. In the .NET environment, we generally use and develop MSMQ which creates outgoing queues for messages waiting to be sent and incoming queues for messages waiting to be received. MSMQ is message-oriented middleware whose queues, according to the developer, are very reliable, simple and more efficient than other skills. However, when developing a huge system, we found out that some problems occur when operating various queues (private/public). This paper shows the results of various tests using MSMQ, such as the status of mqsvc, CPU or memory usage, and whether or not the messages are sent and received. Also, we learned how to use MSMQ in order to develop Message Queuing-based applications.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126504888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Thapliyal, Anvesh Ramasahayam, V. Kotha, Kunul Gottimukkula, M. Srinivas
The efficiency of the public key encryption systems like RSA and ECC can be improved with the adoption of a faster multiplication scheme. In this paper, Modified Montgomery multiplications and circuit architectures are presented. The first modified Montgomery multiplier uses 4:2 compressor and carry save adders (CSA) to perform large word length additions. The total delay for a single modular multiplication using the proposed approach is 7XOR+1 AND gate compared to 8XOR+1AND gate of the recently proposed fastest algorithm. The second modified Montgomery multiplier uses a novel proposed hardware unit that outputs carry save representation of the 4-input operands in 3XOR delays. The total delay for a single modular multiplication using the novel hardware unit is 5XOR+1 AND gate compared to 6XOR+1AND gate of the recently proposed algorithm. The optimal transistor implementations of the proposed approaches have also been presented. The proposed transistor implementations are highly optimized in terms of area, speed and low power. The proposed Montgomery multiplication circuit will be of eminent importance when implemented for higher word length such as 1024 and 2048 as there will be saving in the propagation delays by 1024 and 2048 XOR gates respectively compared to the recently proposed fastest algorithm.
{"title":"Modified Montgomery modular multiplication using 4:2 compressor and CSA adder","authors":"H. Thapliyal, Anvesh Ramasahayam, V. Kotha, Kunul Gottimukkula, M. Srinivas","doi":"10.1109/DELTA.2006.70","DOIUrl":"https://doi.org/10.1109/DELTA.2006.70","url":null,"abstract":"The efficiency of the public key encryption systems like RSA and ECC can be improved with the adoption of a faster multiplication scheme. In this paper, Modified Montgomery multiplications and circuit architectures are presented. The first modified Montgomery multiplier uses 4:2 compressor and carry save adders (CSA) to perform large word length additions. The total delay for a single modular multiplication using the proposed approach is 7XOR+1 AND gate compared to 8XOR+1AND gate of the recently proposed fastest algorithm. The second modified Montgomery multiplier uses a novel proposed hardware unit that outputs carry save representation of the 4-input operands in 3XOR delays. The total delay for a single modular multiplication using the novel hardware unit is 5XOR+1 AND gate compared to 6XOR+1AND gate of the recently proposed algorithm. The optimal transistor implementations of the proposed approaches have also been presented. The proposed transistor implementations are highly optimized in terms of area, speed and low power. The proposed Montgomery multiplication circuit will be of eminent importance when implemented for higher word length such as 1024 and 2048 as there will be saving in the propagation delays by 1024 and 2048 XOR gates respectively compared to the recently proposed fastest algorithm.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121930723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate a novel Opto-VLSI tunable fiber ring laser structure in which an Opto-VLSI processor driven by steering phase holograms dynamically selects the lasing wavelengths. A proof-of-concept tunable fiber ring laser which has a wavelength tuning range of more than 4 nm around 1530 nm and a side-mode suppression ratio more than 25 dB is demonstrated at room temperature. The output power of the lasing wavelengths can be controlled within 0.5 dB uniformity by reconfiguring the phase hologram of the Opto-VLSI processor. Dual-wavelength laser tuning is also experimentally demonstrated.
{"title":"An opto-VLSI based tunable fiber ring laser","authors":"R. Zheng, Zhenglin Wang, K. Alameh","doi":"10.1109/DELTA.2006.13","DOIUrl":"https://doi.org/10.1109/DELTA.2006.13","url":null,"abstract":"We demonstrate a novel Opto-VLSI tunable fiber ring laser structure in which an Opto-VLSI processor driven by steering phase holograms dynamically selects the lasing wavelengths. A proof-of-concept tunable fiber ring laser which has a wavelength tuning range of more than 4 nm around 1530 nm and a side-mode suppression ratio more than 25 dB is demonstrated at room temperature. The output power of the lasing wavelengths can be controlled within 0.5 dB uniformity by reconfiguring the phase hologram of the Opto-VLSI processor. Dual-wavelength laser tuning is also experimentally demonstrated.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117132821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Haag, A. Vadlamani, Jacob L. Campbell, J. Dickman
This paper discusses the various aspects of using airborne laser scanners (ALS) in terrain referenced navigation (TRN) systems. The paper addresses the system performance of these new ALS-based systems and compares their performance to traditional terrain referenced navigation systems based on radar altimeter and baro-altimeter sensors. The TRN system comparison also includes an inertial measurement unit (IMU) error sensitivity analysis and a discussion on the requirements imposed on the information content in the terrain elevation database by the remote sensor. The paper will use flight test data collected with Ohio University's DC-3Flying Laboratory in Braxton, WV to evaluate the various methodologies and analyses
{"title":"Application of laser range scanner based terrain referenced navigation systems for aircraft guidance","authors":"M. Haag, A. Vadlamani, Jacob L. Campbell, J. Dickman","doi":"10.1109/DELTA.2006.15","DOIUrl":"https://doi.org/10.1109/DELTA.2006.15","url":null,"abstract":"This paper discusses the various aspects of using airborne laser scanners (ALS) in terrain referenced navigation (TRN) systems. The paper addresses the system performance of these new ALS-based systems and compares their performance to traditional terrain referenced navigation systems based on radar altimeter and baro-altimeter sensors. The TRN system comparison also includes an inertial measurement unit (IMU) error sensitivity analysis and a discussion on the requirements imposed on the information content in the terrain elevation database by the remote sensor. The paper will use flight test data collected with Ohio University's DC-3Flying Laboratory in Braxton, WV to evaluate the various methodologies and analyses","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123645343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Proposed paper presents a methodology for RAM testing based on counter address sequences. Presented solution allows us to generate and obtain different address sequences for march tests and use them to detect Pattern Sensitive Faults with a very high probability. According to previous investigations, we can use march tests to test modern memory chips, because their transparent versions are very efficient for the faults testing and diagnoses. In this paper, the most important results were done to calculate the best distance between two consecutive address sequences and to find the most efficient method for Pattern Sensitive Faults detection with simple address sequences generation techniques.
{"title":"Address sequences for march tests to detect pattern sensitive faults","authors":"B. Sokol, S. Yarmolik","doi":"10.1109/DELTA.2006.11","DOIUrl":"https://doi.org/10.1109/DELTA.2006.11","url":null,"abstract":"Proposed paper presents a methodology for RAM testing based on counter address sequences. Presented solution allows us to generate and obtain different address sequences for march tests and use them to detect Pattern Sensitive Faults with a very high probability. According to previous investigations, we can use march tests to test modern memory chips, because their transparent versions are very efficient for the faults testing and diagnoses. In this paper, the most important results were done to calculate the best distance between two consecutive address sequences and to find the most efficient method for Pattern Sensitive Faults detection with simple address sequences generation techniques.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129131755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The co-design of hardware and software systems with object oriented design languages like SystemC has become very popular Static analysis of those descriptions allows to conduct the design process with metrics regarding quality of the code as well as with estimations of the properties of the final design. This paper shows the utilization of software metrics and the computation of high level metrics for SystemC, whose generation is embedded into a complete design methodology. The performance of this analysis process is demonstrated on a UMTS cell searching unit
{"title":"Static code analysis of functional descriptions in SystemC","authors":"M. Holzer, M. Rupp","doi":"10.1109/DELTA.2006.80","DOIUrl":"https://doi.org/10.1109/DELTA.2006.80","url":null,"abstract":"The co-design of hardware and software systems with object oriented design languages like SystemC has become very popular Static analysis of those descriptions allows to conduct the design process with metrics regarding quality of the code as well as with estimations of the properties of the final design. This paper shows the utilization of software metrics and the computation of high level metrics for SystemC, whose generation is embedded into a complete design methodology. The performance of this analysis process is demonstrated on a UMTS cell searching unit","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129150168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The area of microelectronic fluidic arrays is rapidly developing into many different commercial products, one being biological arrays. As a consequence, efficient and reliable design and testing of these systems becomes of crucial importance. This paper shows some of the latest results obtained with regard to the flowFET fluidic transfer device, its fault-free and fault modelling, and the co-simulation of a microelectronic fluidic array for life sciences.
{"title":"Fault modelling and co-simulation in flowFET-based biological array systems","authors":"H. Kerkhoff, Xiao Zhang, R. Barber, D. Emerson","doi":"10.1109/DELTA.2006.48","DOIUrl":"https://doi.org/10.1109/DELTA.2006.48","url":null,"abstract":"The area of microelectronic fluidic arrays is rapidly developing into many different commercial products, one being biological arrays. As a consequence, efficient and reliable design and testing of these systems becomes of crucial importance. This paper shows some of the latest results obtained with regard to the flowFET fluidic transfer device, its fault-free and fault modelling, and the co-simulation of a microelectronic fluidic array for life sciences.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125502513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25/spl mu/m 1P5M salicide process and occupies a silicon area of approximately 115mm/sup 2/ (11.5mm /spl times/ 10mm).
{"title":"A low-power high-speed 1-Mb CMOS SRAM","authors":"Tan Soon-Hwei, Loh Poh-Yee, M. Sulaiman","doi":"10.1109/DELTA.2006.6","DOIUrl":"https://doi.org/10.1109/DELTA.2006.6","url":null,"abstract":"An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of process, voltage & temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25/spl mu/m 1P5M salicide process and occupies a silicon area of approximately 115mm/sup 2/ (11.5mm /spl times/ 10mm).","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed.
{"title":"Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array","authors":"P. J. Green, Desmond P. Taylor","doi":"10.1109/DELTA.2006.56","DOIUrl":"https://doi.org/10.1109/DELTA.2006.56","url":null,"abstract":"This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125628716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Karuri, C. Huben, R. Leupers, G. Ascheid, H. Meyr
The memory subsystem is the major performance bottleneck in terms of speed and power consumption in today's digital systems. This is especially true for application specific embedded systems where power consumption due to memory traffic, memory latency and size of the on-chip caches have a significant role in overall system performance, energy efficiency and cost. There is an urgent need of tools that help designers take informed decisions about memory subsystems for embedded applications. This paper presents a novel, fine-grained memory profiling technique that provides the designer with valuable information such as the total amount of dynamic memory requirement of an application, the most heavily accessed source level data objects, the most memory intensive portions of an application etc. Such information can aid designers to take decisions about the overall memory subsystem comprising of a number of different cache levels, scratch-pad memories and main memory. It can also be used by a compiler to perform advanced compiler controlled memory assignment techniques, and by the application programmer to optimize an application. Case studies at the end of this paper demonstrate the accuracy of our profiling technique and provide some example usage scenarios of it.
{"title":"Memory access micro-profiling for ASIP design","authors":"K. Karuri, C. Huben, R. Leupers, G. Ascheid, H. Meyr","doi":"10.1109/DELTA.2006.63","DOIUrl":"https://doi.org/10.1109/DELTA.2006.63","url":null,"abstract":"The memory subsystem is the major performance bottleneck in terms of speed and power consumption in today's digital systems. This is especially true for application specific embedded systems where power consumption due to memory traffic, memory latency and size of the on-chip caches have a significant role in overall system performance, energy efficiency and cost. There is an urgent need of tools that help designers take informed decisions about memory subsystems for embedded applications. This paper presents a novel, fine-grained memory profiling technique that provides the designer with valuable information such as the total amount of dynamic memory requirement of an application, the most heavily accessed source level data objects, the most memory intensive portions of an application etc. Such information can aid designers to take decisions about the overall memory subsystem comprising of a number of different cache levels, scratch-pad memories and main memory. It can also be used by a compiler to perform advanced compiler controlled memory assignment techniques, and by the application programmer to optimize an application. Case studies at the end of this paper demonstrate the accuracy of our profiling technique and provide some example usage scenarios of it.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131266979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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