There is a permanent shortage of qualified test engineers in the electronic industry and R&D organizations, thus leading to a high demand for such staff. Addressing the issue, leading electronic companies have started to cooperate closely with universities in the area of training future test and failure analysis engineering specialists. Malaysia is a home of large semiconductor fabrication facilities representing a number of major multinational corporations. Freescale Semiconductor Malaysia is among the largest IC fabrication companies in the country. Responding to the needs of the semiconductor sector, Monash University Malaysia and Freescale Semiconductor have jointly developed and implemented an undergraduate unit (subject) on Electronic Test Technology. The unit is available to the 4th year students of BE degrees in Electrical and Computer Systems Engineering and Mechatronics. The successful collaboration between the university and company covers also a number of other areas such as industrial attachments and final year (graduate) project development at Freescale Semiconductor with joint company-university supervision, joint postgraduate supervision, participation in industry-academia advisory committees, joint research publications and presentations, organising seminars and conferences, etc.
{"title":"Industry-academia collaboration in undergraduate test engineering unit development","authors":"S. Demidenko, Victor Lai","doi":"10.1109/DELTA.2006.58","DOIUrl":"https://doi.org/10.1109/DELTA.2006.58","url":null,"abstract":"There is a permanent shortage of qualified test engineers in the electronic industry and R&D organizations, thus leading to a high demand for such staff. Addressing the issue, leading electronic companies have started to cooperate closely with universities in the area of training future test and failure analysis engineering specialists. Malaysia is a home of large semiconductor fabrication facilities representing a number of major multinational corporations. Freescale Semiconductor Malaysia is among the largest IC fabrication companies in the country. Responding to the needs of the semiconductor sector, Monash University Malaysia and Freescale Semiconductor have jointly developed and implemented an undergraduate unit (subject) on Electronic Test Technology. The unit is available to the 4th year students of BE degrees in Electrical and Computer Systems Engineering and Mechatronics. The successful collaboration between the university and company covers also a number of other areas such as industrial attachments and final year (graduate) project development at Freescale Semiconductor with joint company-university supervision, joint postgraduate supervision, participation in industry-academia advisory committees, joint research publications and presentations, organising seminars and conferences, etc.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133606077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a test pattern optimization approach using a proper number of seed selection in mixed-mode patterns. In mixed-mode patterns, the test set is assembled from LFSR based pseudorandom and deterministic patterns. The efficiency of this approach is largely determined by the ratio of those test patterns in the final test. The experiment results show that the total number of patterns in this optimized mixed-mode is minimized compared to conventional mixed-mode technique.
{"title":"Test pattern optimization using proper in mixed-mode technique","authors":"S. Z. Islam, M. Ali","doi":"10.1109/DELTA.2006.86","DOIUrl":"https://doi.org/10.1109/DELTA.2006.86","url":null,"abstract":"This paper presents a test pattern optimization approach using a proper number of seed selection in mixed-mode patterns. In mixed-mode patterns, the test set is assembled from LFSR based pseudorandom and deterministic patterns. The efficiency of this approach is largely determined by the ratio of those test patterns in the final test. The experiment results show that the total number of patterns in this optimized mixed-mode is minimized compared to conventional mixed-mode technique.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The focus of this research is the cryptographic keys generation with low power consumption. The idea of power consumption minimization by using modified structure of LFSR has been proposed. Some pseudorandom non linear pattern generators with low power consumption used in stream cipher cryptography are presented in this paper: the Geffe generator, the Jennings generator, the Beth-Piper stop-and-go generator, the Gollmann cascade stop-and-go generator.
{"title":"Designing cryptographic key generators with low power consumption","authors":"M. Puczko, V. Yarmolik","doi":"10.1109/DELTA.2006.34","DOIUrl":"https://doi.org/10.1109/DELTA.2006.34","url":null,"abstract":"The focus of this research is the cryptographic keys generation with low power consumption. The idea of power consumption minimization by using modified structure of LFSR has been proposed. Some pseudorandom non linear pattern generators with low power consumption used in stream cipher cryptography are presented in this paper: the Geffe generator, the Jennings generator, the Beth-Piper stop-and-go generator, the Gollmann cascade stop-and-go generator.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114320439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Hashizume, T. Nishida, H. Yotsuyanagi, T. Tamesada, Y. Miura
In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing.
{"title":"Current testable design of resistor string DACs","authors":"M. Hashizume, T. Nishida, H. Yotsuyanagi, T. Tamesada, Y. Miura","doi":"10.1109/DELTA.2006.28","DOIUrl":"https://doi.org/10.1109/DELTA.2006.28","url":null,"abstract":"In this paper, supply current testability is examined experimentally for opens and shorts in a general 3 bit resistor string digital/analog converter (DAC). The results show that all of the shorts and the opens are detected by supply current testing, while opens of the MOS switches are not detected. A DFT method for resistor string DACs is proposed in this paper to detect the opens by supply current testing. Also, testability of a resistor string DAC designed with the DFT method is examined. It is shown that all of the targeted shorts and opens in the testable designed DAC are detected by supply current testing.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116380828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we investigate the impact of the most common catastrophic and parametric faults in photonic systems. We demonstrate, using the example of a photonic correlator, the effectiveness of testing techniques for fault detection in photonic systems. To the best of our knowledge, this constitutes the first attempt to define a fault model and to develop a test methodology for photonic systems.
{"title":"Catastrophic and parametric fault modelling for photonic systems","authors":"M. Aljada, A. Osseiran, K. Alameh","doi":"10.1109/DELTA.2006.21","DOIUrl":"https://doi.org/10.1109/DELTA.2006.21","url":null,"abstract":"In this paper, we investigate the impact of the most common catastrophic and parametric faults in photonic systems. We demonstrate, using the example of a photonic correlator, the effectiveness of testing techniques for fault detection in photonic systems. To the best of our knowledge, this constitutes the first attempt to define a fault model and to develop a test methodology for photonic systems.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flash memories are a type of nonvolatile memory, which are becoming more and more popular for system-on-chip. But, flash memories are suffered by different types of disturb faults. In the present paper, some new disturb faults that may appear in flash memory are proposed. A modifies March algorithm is developed to detect these faults. Finally, an embedded processor-based built-in self-test (BIST) design is implemented for embedded memories. The proposed method utilizes the concept of reusing the processor in SoC environment. By reusing the embedded processor, the area overhead due to BIST can be reduced to a great extent. The area overhead is only due to the circuits required to design memory wrapper cell. The experimental results show that the area overhead due to BIST is less than 1% for a typical 256K flash memory
{"title":"Built-in self-test for flash memory embedded in SoC","authors":"Shibaji Banerjee, D. R. Chowdhury","doi":"10.1109/DELTA.2006.19","DOIUrl":"https://doi.org/10.1109/DELTA.2006.19","url":null,"abstract":"Flash memories are a type of nonvolatile memory, which are becoming more and more popular for system-on-chip. But, flash memories are suffered by different types of disturb faults. In the present paper, some new disturb faults that may appear in flash memory are proposed. A modifies March algorithm is developed to detect these faults. Finally, an embedded processor-based built-in self-test (BIST) design is implemented for embedded memories. The proposed method utilizes the concept of reusing the processor in SoC environment. By reusing the embedded processor, the area overhead due to BIST can be reduced to a great extent. The area overhead is only due to the circuits required to design memory wrapper cell. The experimental results show that the area overhead due to BIST is less than 1% for a typical 256K flash memory","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper is concerned with design and an integrated circuit implementation of a multicarrier quadrature phase generator for application in analog spectral synthesis and orthogonal frequency division multiplexing transceiver using amplitude phase shift keying using 0.18/spl mu/ technology. A noble analog or sampled data based rotational quadrature oscillator has been designed for generating quadrature signals. Scheme of multicarrier generation studied includes multiple frequency generation, using regenerative frequency dividers and mixers. Simulation results and performance of multicarrier generation have been presented. This scheme shows very low power consumption than typical method of multi-frequency signal synthesis using IFFT.
{"title":"Design and implementation of analog multitone signal generator using regenerative frequency divider for OFDM transceiver","authors":"Amlan Ghosh, A. Ranjan, N. B. Chakrabarti","doi":"10.1109/DELTA.2006.31","DOIUrl":"https://doi.org/10.1109/DELTA.2006.31","url":null,"abstract":"This paper is concerned with design and an integrated circuit implementation of a multicarrier quadrature phase generator for application in analog spectral synthesis and orthogonal frequency division multiplexing transceiver using amplitude phase shift keying using 0.18/spl mu/ technology. A noble analog or sampled data based rotational quadrature oscillator has been designed for generating quadrature signals. Scheme of multicarrier generation studied includes multiple frequency generation, using regenerative frequency dividers and mixers. Simulation results and performance of multicarrier generation have been presented. This scheme shows very low power consumption than typical method of multi-frequency signal synthesis using IFFT.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128388880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Somsak, K. Chomsuwan, S. Yamada, M. Iwahara, S. C. Mukhopadhyay
We present an eddy-current test (ECT) method for detecting conductive microbeads on a nonconductive substrate. A Helmholtz coil is used to generate an exciting magnetic field. The magnetic fields, generated by eddy-currents in a Pb-Sn microbead, are detected by a spin-valve giant magnetoresistive (SV-GMR) sensor. The experimental results are compared to an analytical solution for the magnetic field over the microbead. Early results for the detection of a grid of microbeads are also presented.
{"title":"Conductive microbead detection by Helmholtz coil technique with SV-GMR sensor","authors":"T. Somsak, K. Chomsuwan, S. Yamada, M. Iwahara, S. C. Mukhopadhyay","doi":"10.1109/DELTA.2006.25","DOIUrl":"https://doi.org/10.1109/DELTA.2006.25","url":null,"abstract":"We present an eddy-current test (ECT) method for detecting conductive microbeads on a nonconductive substrate. A Helmholtz coil is used to generate an exciting magnetic field. The magnetic fields, generated by eddy-currents in a Pb-Sn microbead, are detected by a spin-valve giant magnetoresistive (SV-GMR) sensor. The experimental results are compared to an analytical solution for the magnetic field over the microbead. Early results for the detection of a grid of microbeads are also presented.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130068548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the technology scales down, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus result in increased cross-coupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. We propose an efficient encoding scheme that eliminates correlated switching (coupling transitions) in 4-bit buses and also minimizes self-transitions among the wires in these data busses. Wider data busses are implemented using these 4-bit bus blocks.
{"title":"Bus encoding scheme to eliminate unwanted signal transitions","authors":"A. Elkammar, N. Scheinberg, S. Vemuru","doi":"10.1109/DELTA.2006.20","DOIUrl":"https://doi.org/10.1109/DELTA.2006.20","url":null,"abstract":"As the technology scales down, the increased wire aspect ratio and the reduced spacing between the individual wires within a bus result in increased cross-coupling capacitances. This increases crosstalk noise and power dissipation particularly in wide data buses. We propose an efficient encoding scheme that eliminates correlated switching (coupling transitions) in 4-bit buses and also minimizes self-transitions among the wires in these data busses. Wider data busses are implemented using these 4-bit bus blocks.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130925307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transconductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.
{"title":"The new low power 10-bit pipelined ADC using novel background calibration technique","authors":"J. Haze, R. Vrba","doi":"10.1109/DELTA.2006.87","DOIUrl":"https://doi.org/10.1109/DELTA.2006.87","url":null,"abstract":"The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transconductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：