A table-based implementation of an application specific data prefetching approach is presented in this paper. This approach is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, the cache controller prefetches all data fields of an object required by a class method, when the class method is invoked. In the proposed table-based implementation, the cache controller monitors the class method calls and records the index of object data members that each method accessed. This information is used to prefetch the data items needed by a class method on next invocations of that method. This approach adapts the prefetching mechanism to the running application. The experimental results show that on average, this prefetching approach improves the miss ratio by 65%.
{"title":"A data prefetching mechanism for object-oriented embedded systems using run-time profiling","authors":"M. Modarressi, S. Hessabi, M. Goudarzi","doi":"10.1109/DELTA.2006.1","DOIUrl":"https://doi.org/10.1109/DELTA.2006.1","url":null,"abstract":"A table-based implementation of an application specific data prefetching approach is presented in this paper. This approach is proposed to improve the performance of the application specific instruction-set processors (ASIP) we develop customized to an object-oriented application. In this approach, the cache controller prefetches all data fields of an object required by a class method, when the class method is invoked. In the proposed table-based implementation, the cache controller monitors the class method calls and records the index of object data members that each method accessed. This information is used to prefetch the data items needed by a class method on next invocations of that method. This approach adapts the prefetching mechanism to the running application. The experimental results show that on average, this prefetching approach improves the miss ratio by 65%.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new approach to optimise the performance of a multi-head marking system in terms of its marking speed. This processing method named as MMA (molecular marking optimisation algorithm) adopts the use of genetic algorithm. The advantage of the 'self evolving' nature of the genetic algorithm has been considered to discover the most relevant combination of features for each diagnosis considered. The knowledge acquired by the process is interpreted and mapped into vectors, which are kept in the database and used by the system to guide its reasoning process. The representation approach has been implemented via computer program in order to achieve optimised marking performance. Also, the performance of the new operators for evolutionary approaches to the time-based problem has been discussed in the paper
{"title":"Dual-head marking performance optimisation via evolutionary solutions","authors":"J. Koh, S. Tiong, I. Aris, S. Mahmoud","doi":"10.1109/DELTA.2006.39","DOIUrl":"https://doi.org/10.1109/DELTA.2006.39","url":null,"abstract":"This paper presents a new approach to optimise the performance of a multi-head marking system in terms of its marking speed. This processing method named as MMA (molecular marking optimisation algorithm) adopts the use of genetic algorithm. The advantage of the 'self evolving' nature of the genetic algorithm has been considered to discover the most relevant combination of features for each diagnosis considered. The knowledge acquired by the process is interpreted and mapped into vectors, which are kept in the database and used by the system to guide its reasoning process. The representation approach has been implemented via computer program in order to achieve optimised marking performance. Also, the performance of the new operators for evolutionary approaches to the time-based problem has been discussed in the paper","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132132783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gate-oxide shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in domino cells are proposed.
{"title":"Electrical behavior of GOS fault affected domino logic cell","authors":"M. Comte, S. Ohtake, H. Fujiwara, M. Renovell","doi":"10.1109/DELTA.2006.42","DOIUrl":"https://doi.org/10.1109/DELTA.2006.42","url":null,"abstract":"Gate-oxide shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in domino cells are proposed.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128364892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Smart antenna is a well known method to increase the spectral efficiency of the wireless channel and subsequently increase the mobile communication system capacity without jeopardizing the system QoS (De Sousa et al, 2003; Marikar, 2002). There are two major types of smart antenna systems; switch beam antenna and adaptive beam antenna. Adaptive antenna which has dynamic beam to cater for users needs is better in improving the system capacity but requires more advance beam forming algorithm and requires intensive processing power for beam forming. Thus, adaptive beamforming technique is critically important. In this paper, a novel adaptive downlink beam forming technique for WCDMA system namely Minimum Downlink Power Consumption (MDPC) is introduced. A dynamic radio network simulator was developed in Visual C++/spl reg/ to study the power consumption at WCDMA base station (Node B) and to estimate the downlink capacity improvement by implementing this novel algorithm. Simulation was done based on a single micro cell environment with consideration of interference from the first tier. User mobility is taken into account to provide a combined evaluation of Radio Resource Management (RRM). Capacity system expressed in downlink outage under various simulation scenarios was represented in this paper.
智能天线是一种众所周知的方法，可以提高无线信道的频谱效率，从而在不损害系统QoS的情况下增加移动通信系统的容量(De Sousa et al .， 2003;Marikar, 2002)。智能天线系统主要有两种类型;开关波束天线和自适应波束天线。采用适应用户需求的动态波束的自适应天线能更好地提高系统容量，但对波束形成算法要求更高，波束形成需要大量的处理能力。因此，自适应波束形成技术至关重要。本文介绍了一种新的WCDMA系统自适应下行波束形成技术——最小下行功耗(MDPC)。在Visual c++ /spl / reg/环境下开发了动态无线网络模拟器，研究了WCDMA基站(节点B)的功耗，并对采用该算法后的下行容量改进进行了估计。在考虑第一层干扰的单微单元环境下进行仿真。考虑用户移动性，对无线电资源管理(RRM)进行综合评估。本文描述了各种仿真场景下下行中断的容量系统。
{"title":"Downlink capacity improvement of WCDMA system by using adaptive antenna with novel MDPC beamforming technique","authors":"S. Tiong, J. Koh, M. Ismail, Azmi Hassan","doi":"10.1109/DELTA.2006.38","DOIUrl":"https://doi.org/10.1109/DELTA.2006.38","url":null,"abstract":"Smart antenna is a well known method to increase the spectral efficiency of the wireless channel and subsequently increase the mobile communication system capacity without jeopardizing the system QoS (De Sousa et al, 2003; Marikar, 2002). There are two major types of smart antenna systems; switch beam antenna and adaptive beam antenna. Adaptive antenna which has dynamic beam to cater for users needs is better in improving the system capacity but requires more advance beam forming algorithm and requires intensive processing power for beam forming. Thus, adaptive beamforming technique is critically important. In this paper, a novel adaptive downlink beam forming technique for WCDMA system namely Minimum Downlink Power Consumption (MDPC) is introduced. A dynamic radio network simulator was developed in Visual C++/spl reg/ to study the power consumption at WCDMA base station (Node B) and to estimate the downlink capacity improvement by implementing this novel algorithm. Simulation was done based on a single micro cell environment with consideration of interference from the first tier. User mobility is taken into account to provide a combined evaluation of Radio Resource Management (RRM). Capacity system expressed in downlink outage under various simulation scenarios was represented in this paper.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133034606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular structure. The cells are adjacent to each other and are able to process signals based on simple transition rules. In delay-insensitive circuits the delay on a signal path does not affect circuit behavior. The combination of delay-insensitive circuit style and cellular arrays makes it possible to implement nanoscale circuits. This paper proposes a technique to synthesize and implement logic functions in Reed-Muller form onto cellular arrays. The resulting circuits have delay-insensitivity and high modularity
{"title":"Synthesis of nanoelectronic circuits on delay-insensitive cellular arrays","authors":"J. Di, D. Vasudevan","doi":"10.1109/DELTA.2006.84","DOIUrl":"https://doi.org/10.1109/DELTA.2006.84","url":null,"abstract":"The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular structure. The cells are adjacent to each other and are able to process signals based on simple transition rules. In delay-insensitive circuits the delay on a signal path does not affect circuit behavior. The combination of delay-insensitive circuit style and cellular arrays makes it possible to implement nanoscale circuits. This paper proposes a technique to synthesize and implement logic functions in Reed-Muller form onto cellular arrays. The resulting circuits have delay-insensitivity and high modularity","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129117495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, key recent innovations with respect to all major segments of the test industry are discussed. These innovations do not provide incremental improvement; they change the paradigm impacting the productivity and cost by orders of magnitude. The objective is to provide guidance for academic and industrial researchers for these new grounds.
{"title":"Innovation in test: where are we","authors":"R. Rajsuman","doi":"10.1109/DELTA.2006.59","DOIUrl":"https://doi.org/10.1109/DELTA.2006.59","url":null,"abstract":"In this paper, key recent innovations with respect to all major segments of the test industry are discussed. These innovations do not provide incremental improvement; they change the paradigm impacting the productivity and cost by orders of magnitude. The objective is to provide guidance for academic and industrial researchers for these new grounds.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129475160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test compression/decompression methods for reducing the test application time and memory requirement of an LSI tester have been proposed. In these methods, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can compress highly the test data. However, these methods have some drawbacks, e.g., the coding algorithm may not be effective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to the used coding algorithms and a given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-re configurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding.
{"title":"A reconfigurable embedded decompressor for test compression","authors":"Tomoyuki Saiki, H. Ichihara, Tomoo Inoue","doi":"10.1109/DELTA.2006.10","DOIUrl":"https://doi.org/10.1109/DELTA.2006.10","url":null,"abstract":"Test compression/decompression methods for reducing the test application time and memory requirement of an LSI tester have been proposed. In these methods, the employed coding algorithms are tailored to a given test data, so that the tailored coding algorithm can compress highly the test data. However, these methods have some drawbacks, e.g., the coding algorithm may not be effective in extra test data except for the given test data. In this paper, we introduce an embedded decompressor that is reconfigurable according to the used coding algorithms and a given test data. Its reconfigurability can overcome the drawbacks of conventional decompressors with keeping high compression ratio. Moreover, we propose an architecture of reconfigurable decompressors for four variable-length codings. In the proposed architecture, the common functions for four codings are implemented as fixed (or non-re configurable) components so as to reduce the configuration data, which is stored on an ATE and sent to a CUT. Experimental results show that (1) the configuration data size becomes reasonably small by reducing the configuration part of the decompressor, (2) the reconfigurable decompressor is effective for SoC testing in respect of the test data size, and (3) it can achieve an optimal compression of test data by Huffman coding.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the pressing issues faced by the semiconductor industry today is the cost of testing, especially on the low cost and high volume microcontroller (MCU) supply to automotive market. This paper describes the general consideration and justification made on the investment of tester, handler and device interface board (DIB) to enable the /spl times/6 and /spl times/8 multi-site testing on the 80 and 112pin counts 16-bit HCS12 MCU in quad flat pack (QFP) package and the associate test cost reduction and tester saving estimation. Test issue encounter on the first spin of /spl times/6 and /spl times/8 DIB and how it was resolved through re-design of the DIB also is presented. This finding also provide the PCS designer the valuable information on the constraint of trace length and component layout one need to take into consideration when design a multi-site DIB use for high speed MCU testing to avoid AC or DC test failure induced by excessive capacitive loading and resistance drop over signal trace on the DIB.
{"title":"Test cost saving and challenges in the implementation of /spl times/6 and /spl times/8 parallel testing on freescale 16-bit HCS12 microcontroller product family","authors":"Lew Boon Kian","doi":"10.1109/DELTA.2006.85","DOIUrl":"https://doi.org/10.1109/DELTA.2006.85","url":null,"abstract":"One of the pressing issues faced by the semiconductor industry today is the cost of testing, especially on the low cost and high volume microcontroller (MCU) supply to automotive market. This paper describes the general consideration and justification made on the investment of tester, handler and device interface board (DIB) to enable the /spl times/6 and /spl times/8 multi-site testing on the 80 and 112pin counts 16-bit HCS12 MCU in quad flat pack (QFP) package and the associate test cost reduction and tester saving estimation. Test issue encounter on the first spin of /spl times/6 and /spl times/8 DIB and how it was resolved through re-design of the DIB also is presented. This finding also provide the PCS designer the valuable information on the constraint of trace length and component layout one need to take into consideration when design a multi-site DIB use for high speed MCU testing to avoid AC or DC test failure induced by excessive capacitive loading and resistance drop over signal trace on the DIB.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Bailey, K. T. Gribbon, C. T. Johnston, M. Siripruchyanun
FPGAs are increasingly being used to implement low-level vision operations in stand-alone configurations. For real-time image processing applications there is a need for several interactive operating system functions such as tuning, calibration, user interaction, and debugging which are difficult to perform when not under the control of a host operating system. This paper proposes the gate array terminal operating system (GATOS) which provides a set of high-level IP blocks that implement the graphical user interface of an interactive windowing operating system. The requirements and desired levels of functionality for GATOS are discussed and the preliminary design is presented.
{"title":"GATOS: a windowing operating system for FPGAs","authors":"D. Bailey, K. T. Gribbon, C. T. Johnston, M. Siripruchyanun","doi":"10.1109/DELTA.2006.51","DOIUrl":"https://doi.org/10.1109/DELTA.2006.51","url":null,"abstract":"FPGAs are increasingly being used to implement low-level vision operations in stand-alone configurations. For real-time image processing applications there is a need for several interactive operating system functions such as tuning, calibration, user interaction, and debugging which are difficult to perform when not under the control of a host operating system. This paper proposes the gate array terminal operating system (GATOS) which provides a set of high-level IP blocks that implement the graphical user interface of an interactive windowing operating system. The requirements and desired levels of functionality for GATOS are discussed and the preliminary design is presented.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132022373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method for leveraging a communication protocol called Universal Plug and Play (UPnP) for workcell automation and integration is presented. By leveraging UPnP for automation equipment, a workcell can potentially be built in a modular manner whereby the modules can be easily replaced, reused, or upgraded over time with minimal re-engineering of a workcell. UPnP devices can be automatically discovered and their services can be activated remotely via a communication network. However, the UPnP protocol is relatively new and it was designed primarily for connecting home entertainment devices for serving and playing movies and songs. This paper will present preliminary investigative work required to integrate typical automation equipment such as a robot and its vision system in a simple pick and place workcell.
{"title":"Automation integration with UPnP modules","authors":"S. Mok, Chi-haur Wu","doi":"10.1109/DELTA.2006.18","DOIUrl":"https://doi.org/10.1109/DELTA.2006.18","url":null,"abstract":"A method for leveraging a communication protocol called Universal Plug and Play (UPnP) for workcell automation and integration is presented. By leveraging UPnP for automation equipment, a workcell can potentially be built in a modular manner whereby the modules can be easily replaced, reused, or upgraded over time with minimal re-engineering of a workcell. UPnP devices can be automatically discovered and their services can be activated remotely via a communication network. However, the UPnP protocol is relatively new and it was designed primarily for connecting home entertainment devices for serving and playing movies and songs. This paper will present preliminary investigative work required to integrate typical automation equipment such as a robot and its vision system in a simple pick and place workcell.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131216614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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