This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).
{"title":"Evaluation of a software-based error detection technique by RT-level fault injection","authors":"A. Ammari, R. Leveugle, B. Nicolescu, Y. Savaria","doi":"10.1109/DELTA.2006.46","DOIUrl":"https://doi.org/10.1109/DELTA.2006.46","url":null,"abstract":"This paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers).","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128337905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz.
{"title":"Full field image ranger hardware","authors":"A. Payne, D. Carnegie, A. Dorrington, M. Cree","doi":"10.1109/DELTA.2006.50","DOIUrl":"https://doi.org/10.1109/DELTA.2006.50","url":null,"abstract":"We describe the hardware designed to implement a full field heterodyning imaging system. Comprising three key components - a light source, high speed shutter and a signal generator - the system is expected to be capable of simultaneous range measurements to millimetre precision over the entire field of view. Current modulated laser diodes provide the required illumination, with a bandwidth of 100 MHz and peak output power exceeding 600 mW. The high speed shutter action is performed by gating the cathode of an image intensifier, driven by a 50 Vpp waveform with 3.5 ns rise and fall times. A direct digital synthesiser, with multiple synchronised channels, provides high stability between its outputs, 160 MHz bandwidth and tuning of 0.1 Hz.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134138190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe a bandgap circuit capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18/spl mu/m CMOS technology and operates with 0.9 V supply voltage, consuming 5/spl mu/A current. The circuit achieves 7ppm/spl rho/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60/spl deg/ centigrade.
{"title":"Curvature compensated CMOS bandgap with sub 1V supply","authors":"K. Tom, A. Alvandpour","doi":"10.1109/DELTA.2006.29","DOIUrl":"https://doi.org/10.1109/DELTA.2006.29","url":null,"abstract":"We describe a bandgap circuit capable of generating a reference voltage of 0.730V. The circuit is implemented in 0.18/spl mu/m CMOS technology and operates with 0.9 V supply voltage, consuming 5/spl mu/A current. The circuit achieves 7ppm/spl rho/K of temperature coefficient with supply voltage range from 0.9 to 1.5V and temperature range from 0 to 60/spl deg/ centigrade.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ensuring the functional correctness of a SoC is essential for successful design projects. A proven and effective method from Freescale Semiconductor Australia is to employ software application testing at the pre-silicon simulation stage. This method was formalized and implemented into a Software Application Level Verification Methodology (SALVEM). However, despite its successes, SALVEM lacks an effective coverage technique. Existing coverage methods are unsuitable because they do not provide any useful information about the functional applications verified. The contribution of this paper is a coverage method that determines what functional SoC behaviours were tested, and quantifies this information into a coverage metric to estimate the comprehensiveness of SALVEM testing. The paper will outline the coverage method, and explain the abstraction and coverage modelling graph techniques adapted from the formal verification domain of Symbolic Trajectory Evaluation. The coverage method was applied to the Nios SoC and experimental coverage results will be discussed.
{"title":"Coverage measurement for software application testing using partially ordered domains and symbolic trajectory evaluation techniques","authors":"A. Cheng, A. Parashkevov, C. Lim","doi":"10.1109/DELTA.2006.26","DOIUrl":"https://doi.org/10.1109/DELTA.2006.26","url":null,"abstract":"Ensuring the functional correctness of a SoC is essential for successful design projects. A proven and effective method from Freescale Semiconductor Australia is to employ software application testing at the pre-silicon simulation stage. This method was formalized and implemented into a Software Application Level Verification Methodology (SALVEM). However, despite its successes, SALVEM lacks an effective coverage technique. Existing coverage methods are unsuitable because they do not provide any useful information about the functional applications verified. The contribution of this paper is a coverage method that determines what functional SoC behaviours were tested, and quantifies this information into a coverage metric to estimate the comprehensiveness of SALVEM testing. The paper will outline the coverage method, and explain the abstraction and coverage modelling graph techniques adapted from the formal verification domain of Symbolic Trajectory Evaluation. The coverage method was applied to the Nios SoC and experimental coverage results will be discussed.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"312 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121174528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. See, Weixiang Shen, O. Seng, S. Ramanathan, I-Wern Low
To quantify the potential for performance improvement of a standalone photovoltaic (PV) system, a test facility has been installed. This paper describes this development of a prototype standalone PV system. Essentially this entire system involves the integration of a personal computer (PC), data acquisition (DAQ), a battery array and a solar array simulator (SAS) to create a standalone PV system and to test and simulate the system. This new system boasts of high accuracy measurements coupled with the commercial viability of low cost. The basic idea of this facility is that the SAS simulates solar power which is utilized to charge batteries. The information obtained by monitoring parameters, such as average battery's temperature, voltage and current is fed to the PC via the DAQ for analysis. This customized control interface has been developed by utilizing LabVIEW software, which forms the programming backbone of inter-instrument communication via IEEE-GPIB bus. The software created for this system is highly generic and can be used for other instances where different hardware is used. This paper also discussed further research plan, in utilizing this standalone PV system to perform load analysis and batteries charging or discharging with the inputs to the SAS with actual meteorological data obtained from the Malaysian meteorological department.
{"title":"Development of a LabVIEW-based test facility for standalone PV systems","authors":"A. See, Weixiang Shen, O. Seng, S. Ramanathan, I-Wern Low","doi":"10.1109/DELTA.2006.36","DOIUrl":"https://doi.org/10.1109/DELTA.2006.36","url":null,"abstract":"To quantify the potential for performance improvement of a standalone photovoltaic (PV) system, a test facility has been installed. This paper describes this development of a prototype standalone PV system. Essentially this entire system involves the integration of a personal computer (PC), data acquisition (DAQ), a battery array and a solar array simulator (SAS) to create a standalone PV system and to test and simulate the system. This new system boasts of high accuracy measurements coupled with the commercial viability of low cost. The basic idea of this facility is that the SAS simulates solar power which is utilized to charge batteries. The information obtained by monitoring parameters, such as average battery's temperature, voltage and current is fed to the PC via the DAQ for analysis. This customized control interface has been developed by utilizing LabVIEW software, which forms the programming backbone of inter-instrument communication via IEEE-GPIB bus. The software created for this system is highly generic and can be used for other instances where different hardware is used. This paper also discussed further research plan, in utilizing this standalone PV system to perform load analysis and batteries charging or discharging with the inputs to the SAS with actual meteorological data obtained from the Malaysian meteorological department.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116682236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A maximum likelihood for Bayesian estimator based on alpha-stable was discussed in our previous papers. It is in terms of closer to a realistic situation, and unlike previous methods used for Bayesian estimator, for the case discussed here it is not necessary to know the variance of the noise. The Bayesian estimator here is based on in a Nakagami fading channel. Our previous research results has been extended to that Bayesian estimator that we investigated is still working well for the image noise removal in Nakagami fading channels. As an example, an improved Bayesian estimator (soft and hard threshold methods), is illustrated in our discussion
{"title":"Image noise removal in Nakagami fading channels via Bayesian estimator","authors":"Xu Huang, A. C. Madoc, D. Sharma","doi":"10.1109/DELTA.2006.54","DOIUrl":"https://doi.org/10.1109/DELTA.2006.54","url":null,"abstract":"A maximum likelihood for Bayesian estimator based on alpha-stable was discussed in our previous papers. It is in terms of closer to a realistic situation, and unlike previous methods used for Bayesian estimator, for the case discussed here it is not necessary to know the variance of the noise. The Bayesian estimator here is based on in a Nakagami fading channel. Our previous research results has been extended to that Bayesian estimator that we investigated is still working well for the image noise removal in Nakagami fading channels. As an example, an improved Bayesian estimator (soft and hard threshold methods), is illustrated in our discussion","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117167394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design, verification and test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping
{"title":"Some common aspects of design validation, debug and diagnosis","authors":"Talal Arnaout, Gunter Bartsch, H. Wunderlich","doi":"10.1109/DELTA.2006.79","DOIUrl":"https://doi.org/10.1109/DELTA.2006.79","url":null,"abstract":"Design, verification and test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test speed and diagnostic resolution. In this paper, an overview is given on the common aspects of these tasks and how they interact. Diagnosis techniques may be used after manufacturing, for chip characterization and field return analysis, and even for rapid prototyping","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Prasad, B. Mills, A. Assi, S. M. N. Arosha Senanayake, V. Prasad
This paper describes a mathematical model for the prediction of binary decision diagram (BDD) depth measures, such as the longest path length (LPL) and the average path length (APL). The formal core of the model is a formula for the average LPL and APL over the set of BDD derived from Boolean logic expressions with a given number of variables and product terms. The formula was determined by extensive empirical studies of these measures. The proposed model can provide valuable information about Pass Transistor Logic (PTL) evaluation time for any variable ordering method without building the BDD. Our experimental results show good correlation between the theoretical results and those predicted by the mathematical model, which will greatly reduce the time complexity of applications that use BDDs
{"title":"Evaluation time estimation for pass transistor logic circuits","authors":"P. Prasad, B. Mills, A. Assi, S. M. N. Arosha Senanayake, V. Prasad","doi":"10.1109/DELTA.2006.47","DOIUrl":"https://doi.org/10.1109/DELTA.2006.47","url":null,"abstract":"This paper describes a mathematical model for the prediction of binary decision diagram (BDD) depth measures, such as the longest path length (LPL) and the average path length (APL). The formal core of the model is a formula for the average LPL and APL over the set of BDD derived from Boolean logic expressions with a given number of variables and product terms. The formula was determined by extensive empirical studies of these measures. The proposed model can provide valuable information about Pass Transistor Logic (PTL) evaluation time for any variable ordering method without building the BDD. Our experimental results show good correlation between the theoretical results and those predicted by the mathematical model, which will greatly reduce the time complexity of applications that use BDDs","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114906267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the concept, architecture, development and demonstration of a high performance, 4 transmitter, real-time space time encoder designed for research into transmitter diversity and multiple input and multiple output (MIMO) wireless systems. It is implemented on a Xilinx Virtex 2 Pro field programmable gate array (FPGA) and parallel processing on multiple Freescale DSP56321 digital signal processors (DSP). The system is software defined to allow for flexibility in the choice of transmit modulation formats, data rates and space-time coding schemes. Hardware, firmware and software aspects of the space time encoder system to meet design requirements are discussed. The testing and demonstration of the system running the Alamouti space time coding scheme is covered
{"title":"Implementation of a high speed four transmitter space-time encoder using field programmable gate array and parallel digital signal processors","authors":"P. J. Green, Desmond P. Taylor","doi":"10.1109/DELTA.2006.55","DOIUrl":"https://doi.org/10.1109/DELTA.2006.55","url":null,"abstract":"This paper describes the concept, architecture, development and demonstration of a high performance, 4 transmitter, real-time space time encoder designed for research into transmitter diversity and multiple input and multiple output (MIMO) wireless systems. It is implemented on a Xilinx Virtex 2 Pro field programmable gate array (FPGA) and parallel processing on multiple Freescale DSP56321 digital signal processors (DSP). The system is software defined to allow for flexibility in the choice of transmit modulation formats, data rates and space-time coding schemes. Hardware, firmware and software aspects of the space time encoder system to meet design requirements are discussed. The testing and demonstration of the system running the Alamouti space time coding scheme is covered","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127530968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35/spl mu/ CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schottky diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits and a low-voltage reference circuit.
{"title":"CMOS Schottky diode microwave power detector fabrication, SPICE modeling, and applications","authors":"W. Jeon, J. Melngailis, R. Newcomb","doi":"10.1109/DELTA.2006.22","DOIUrl":"https://doi.org/10.1109/DELTA.2006.22","url":null,"abstract":"CMOS Schottky diodes with various contact areas and geometries were fabricated through 0.35/spl mu/ CMOS process. Fabricated diodes were tested under DC and RF direct injection. Based on the measured result, a CMOS Schottky diode SPICE model is suggested and simulated. The suggested SPICE model is used for designing charge pump circuits and a low-voltage reference circuit.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125381200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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