This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and improve bandwidth utilization. Furthermore it increases the performance of internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based which decreases performance. MPLS performance can be enhanced by executing core tasks in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware design of MPLS on an FPGA for increased performance and efficiency.
{"title":"A hardware implementation of layer 2 MPLS","authors":"Raymond Peterkin, D. Ionescu","doi":"10.1109/DELTA.2006.3","DOIUrl":"https://doi.org/10.1109/DELTA.2006.3","url":null,"abstract":"This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and improve bandwidth utilization. Furthermore it increases the performance of internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based which decreases performance. MPLS performance can be enhanced by executing core tasks in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware design of MPLS on an FPGA for increased performance and efficiency.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134275708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an experimental method and theoretical analysis to study the dielectric effect in Mn-Zn ferrite cores. Experimental results show that dielectric effect becomes very pronounced at high frequency. This is caused by the high permittivity of the ferrite core. Theoretical analysis is then introduced to study the influence of high permittivity on the permeability measurement. Numerical results show that significant aberrations of measured permeability from its intrinsic value could occur due to the high permittivity in the Mn-Zn ferrite cores.
{"title":"Effect of high permittivity and core dimensions on the permeability measurement for Mn-Zn ferrite cores used in high-frequency transformer","authors":"Daming Zhang, K. Tseng","doi":"10.1109/DELTA.2006.40","DOIUrl":"https://doi.org/10.1109/DELTA.2006.40","url":null,"abstract":"This paper presents an experimental method and theoretical analysis to study the dielectric effect in Mn-Zn ferrite cores. Experimental results show that dielectric effect becomes very pronounced at high frequency. This is caused by the high permittivity of the ferrite core. Theoretical analysis is then introduced to study the influence of high permittivity on the permeability measurement. Numerical results show that significant aberrations of measured permeability from its intrinsic value could occur due to the high permittivity in the Mn-Zn ferrite cores.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114112466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Harmonic distortion may be characterised by the proportion of energy of a sinusoidal signal transferred to the harmonics. Differential time scaling resulting from the spectral warping transform allows the fundamental and harmonics to be separated, and thus measured separately. Two spectral warping transforms for distortion measurement are compared: the standard all-pass mapping, and a piecewise linear mapping. Both are shown to be effective at measuring distortion, although the piecewise linear mapping is computationally less expensive.
{"title":"Harmonic distortion measurement using spectral warping","authors":"D. Bailey","doi":"10.1109/DELTA.2006.53","DOIUrl":"https://doi.org/10.1109/DELTA.2006.53","url":null,"abstract":"Harmonic distortion may be characterised by the proportion of energy of a sinusoidal signal transferred to the harmonics. Differential time scaling resulting from the spectral warping transform allows the fundamental and harmonics to be separated, and thus measured separately. Two spectral warping transforms for distortion measurement are compared: the standard all-pass mapping, and a piecewise linear mapping. Both are shown to be effective at measuring distortion, although the piecewise linear mapping is computationally less expensive.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pseudorandom bit stream (PRBS) testing is critical in network and communication devices to ensure compliant to industry standards. Thus, many new high speed devices have been designed with internal PRBS generator and comparator capability for built-in-self-test. On the other hand, devices that are without this design-for-test feature will have to be tested through conventional methods such as bit error rate (BER) tester due to capability limitation on automated test equipment (ATE). However, this setup is typically expensive and unfriendly in a high volume manufacturing due to long test time, rack and stack setup and dedicated systems. A novel idea was conceived where a pair of programmable PRBS drivers and comparators is embedded into the test loadboard to provide the BER test capability. Coupled with an intelligent BER algorithm, the solution provides a low cost BER test solution that can be implemented in a high volume manufacturing using only a mixed signal ATE.
{"title":"Enabling test-time optimized pseudorandom bit stream (PRBS) 2/sup 31/ BER testing on automated test equipment for 10Gbps device","authors":"Shao Chee Ong","doi":"10.1109/DELTA.2006.44","DOIUrl":"https://doi.org/10.1109/DELTA.2006.44","url":null,"abstract":"Pseudorandom bit stream (PRBS) testing is critical in network and communication devices to ensure compliant to industry standards. Thus, many new high speed devices have been designed with internal PRBS generator and comparator capability for built-in-self-test. On the other hand, devices that are without this design-for-test feature will have to be tested through conventional methods such as bit error rate (BER) tester due to capability limitation on automated test equipment (ATE). However, this setup is typically expensive and unfriendly in a high volume manufacturing due to long test time, rack and stack setup and dedicated systems. A novel idea was conceived where a pair of programmable PRBS drivers and comparators is embedded into the test loadboard to provide the BER test capability. Coupled with an intelligent BER algorithm, the solution provides a low cost BER test solution that can be implemented in a high volume manufacturing using only a mixed signal ATE.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126730175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose three search methods for obtaining exact minimum AND-EXOR expressions: the depth-first, the breadth-first, and the depth-first-when-optimum searches. They minimize up to 7-variable functions in a practical computation time. Experimental results to compare the efficiency of these methods are presented. The depth-first search, which saves the memory consumption, minimizes the 16-variable benchmark function t481 without memory exhaustion. This search method is the fastest among these three methods on the average computation time for randomly-generated single-output functions. The depth-first-when-optimum search is the fastest on the computation time for the most of benchmark functions. For some benchmark functions, however, the breadth-first search is the fastest
{"title":"Efficient search methods for obtaining exact minimum AND-EXOR expressions","authors":"T. Hirayama, Y. Nishitani","doi":"10.1109/DELTA.2006.41","DOIUrl":"https://doi.org/10.1109/DELTA.2006.41","url":null,"abstract":"We propose three search methods for obtaining exact minimum AND-EXOR expressions: the depth-first, the breadth-first, and the depth-first-when-optimum searches. They minimize up to 7-variable functions in a practical computation time. Experimental results to compare the efficiency of these methods are presented. The depth-first search, which saves the memory consumption, minimizes the 16-variable benchmark function t481 without memory exhaustion. This search method is the fastest among these three methods on the average computation time for randomly-generated single-output functions. The depth-first-when-optimum search is the fastest on the computation time for the most of benchmark functions. For some benchmark functions, however, the breadth-first search is the fastest","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129502254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a current-mode automatic gain control (AGC) is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipment such as hearing aid instrument and wireless radio device. The proposed AGC consists of current controlled exponential amplifier, current-mode precision rectifier, current-mode low pass filter and current-mode integrator. The performances of the proposed circuit are explored through HSPICE simulation program using BSIM3V3 model from MOSIS, they demonstrate good agreement to the theoretical anticipation. The proposed circuit works at /spl plusmn/1.5 V supply voltage, power consumption is merely 7.12mW.
{"title":"A low-voltage, low-power current-mode automatic gain control (AGC) for battery-powered equipment","authors":"M. Siripruchyanun","doi":"10.1109/DELTA.2006.7","DOIUrl":"https://doi.org/10.1109/DELTA.2006.7","url":null,"abstract":"In this paper, a current-mode automatic gain control (AGC) is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipment such as hearing aid instrument and wireless radio device. The proposed AGC consists of current controlled exponential amplifier, current-mode precision rectifier, current-mode low pass filter and current-mode integrator. The performances of the proposed circuit are explored through HSPICE simulation program using BSIM3V3 model from MOSIS, they demonstrate good agreement to the theoretical anticipation. The proposed circuit works at /spl plusmn/1.5 V supply voltage, power consumption is merely 7.12mW.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Instruction set customization is becoming a preferred approach for accelerating high-speed demanding applications. In this paper, we present performance and delay-area product estimation models to accelerate the design of custom instructions on the Nios II configurable processor platform. The proposed models outline the performance bandwidth and delay-area product to enable profitable selection on the type and number of custom instructions, without the need to undertake time-consuming hardware synthesis in the design exploration stage. The models exhibit a high degree of accuracy as they incorporate the architectural dependencies of the arbitrator logic between the Nios II processor and custom hardware. Experimental results reveal that the area-time implications of the arbitrator logic with respect to the number of custom instructions can significantly affect the system's performance and area utilization.
{"title":"Modeling arbitrator delay-area dependencies in customizable instruction set processors","authors":"S. Lam, M. Shoaib, T. Srikanthan","doi":"10.1109/DELTA.2006.69","DOIUrl":"https://doi.org/10.1109/DELTA.2006.69","url":null,"abstract":"Instruction set customization is becoming a preferred approach for accelerating high-speed demanding applications. In this paper, we present performance and delay-area product estimation models to accelerate the design of custom instructions on the Nios II configurable processor platform. The proposed models outline the performance bandwidth and delay-area product to enable profitable selection on the type and number of custom instructions, without the need to undertake time-consuming hardware synthesis in the design exploration stage. The models exhibit a high degree of accuracy as they incorporate the architectural dependencies of the arbitrator logic between the Nios II processor and custom hardware. Experimental results reveal that the area-time implications of the arbitrator logic with respect to the number of custom instructions can significantly affect the system's performance and area utilization.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116477269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconductor manufacturers are constantly challenged by increased demand in quality and product customization at lower cost and faster turn around time. Manufacturing engineers need a systematic, fast and reliable methodology to make decisions to ensure that the Measurement System (MS) is in excellent condition. The Measurement System Analysis (MSA) consists of established statistical tools deployed to ensure that the measurement setups are within an acceptable condition to meet manufacturing capabilities and customer requirements. These tools (Linearity, Stability, Gauge Repeatability and Reproducibility (GRR) and Delta Correlation (deltaCor)) were successfully implemented into the MS in Texas Instruments Malaysia (TIM). It also increases TIM's confidence with the MS and customers satisfaction with the quality of parts received. These tools are in compliance with ISO9001 and TS16949 Automotive Standards. Implementation of these tools have dramatically improved first pass yields, detect and fix ATE abnormalities, and speed up setup time [Tilden, 2003].
{"title":"Measurement system analysis","authors":"A. Shaji","doi":"10.1109/DELTA.2006.62","DOIUrl":"https://doi.org/10.1109/DELTA.2006.62","url":null,"abstract":"Semiconductor manufacturers are constantly challenged by increased demand in quality and product customization at lower cost and faster turn around time. Manufacturing engineers need a systematic, fast and reliable methodology to make decisions to ensure that the Measurement System (MS) is in excellent condition. The Measurement System Analysis (MSA) consists of established statistical tools deployed to ensure that the measurement setups are within an acceptable condition to meet manufacturing capabilities and customer requirements. These tools (Linearity, Stability, Gauge Repeatability and Reproducibility (GRR) and Delta Correlation (deltaCor)) were successfully implemented into the MS in Texas Instruments Malaysia (TIM). It also increases TIM's confidence with the MS and customers satisfaction with the quality of parts received. These tools are in compliance with ISO9001 and TS16949 Automotive Standards. Implementation of these tools have dramatically improved first pass yields, detect and fix ATE abnormalities, and speed up setup time [Tilden, 2003].","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A crosstalk effect in counter-pumped distributed Raman amplifiers (DRAs) with discrete time-division multiplexed (DTDM) pumping is investigated using numerical modeling. We show that the pump repetition frequency has an impact on the pump mediated cross modulation between two channels. Crosstalk effects between channels are shown to be worse in the case of DTDM pumping in comparison with continuous wave (CW) pumping at lower pump repetition frequencies
{"title":"Crosstalk in counter-pumped distributed Raman amplifiers with DTDM pumping","authors":"V. Kalavally, T. Win, M. Premaratne","doi":"10.1109/DELTA.2006.27","DOIUrl":"https://doi.org/10.1109/DELTA.2006.27","url":null,"abstract":"A crosstalk effect in counter-pumped distributed Raman amplifiers (DRAs) with discrete time-division multiplexed (DTDM) pumping is investigated using numerical modeling. We show that the pump repetition frequency has an impact on the pump mediated cross modulation between two channels. Crosstalk effects between channels are shown to be worse in the case of DTDM pumping in comparison with continuous wave (CW) pumping at lower pump repetition frequencies","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133516606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an observer based robust sensor fault reconstruction scheme designed by assigning right eigenvectors. It was found that if the observer had a certain eigenstructure, it could robustly reconstruct the sensor faults. The work in this paper investigates the existence conditions that guarantee a successful design. Then, it proposes an design method for the observer using Linear Matrix Inequalities, such that it is stable and has the desired eigenstructure. Design examples and simulation results validate the work in this paper; where the scheme reconstructs the sensor faults accurately independent of the disturbances.
{"title":"Robust sensor fault reconstruction using right eigenstructure assignment","authors":"Chee Pin Tan, Y. Kuang, C. Edwards","doi":"10.1109/DELTA.2006.77","DOIUrl":"https://doi.org/10.1109/DELTA.2006.77","url":null,"abstract":"This paper presents an observer based robust sensor fault reconstruction scheme designed by assigning right eigenvectors. It was found that if the observer had a certain eigenstructure, it could robustly reconstruct the sensor faults. The work in this paper investigates the existence conditions that guarantee a successful design. Then, it proposes an design method for the observer using Linear Matrix Inequalities, such that it is stable and has the desired eigenstructure. Design examples and simulation results validate the work in this paper; where the scheme reconstructs the sensor faults accurately independent of the disturbances.","PeriodicalId":439448,"journal":{"name":"Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127239664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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