Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79859
H. Park, P. Mandeville, R. Saito, P. Tasker, W. Schaff, L. Eastman
The authors have fabricated Al/sub 0.5/Ga/sub 0.5/As/GaAs MODFETs with gate length as small as 0.25 mu m and characterized them at both DC and RF in an effort to realize high-speed complementary MODFET circuits. Good gate characteristics, high current-drive capability, and high transconductance have been demonstrated. A current-gain cutoff frequency as high as 10 GHz has been obtained, and an effective hole velocity of 1.7*10/sup 6/ cm/s has been estimated from RF data. The device performance shows the potential of the p-channel MODFETs in high-speed complementary heterostructure circuits.<>
{"title":"RF and DC characterization of P-channel Al/sub 0.5/Ga/sub 0.5/As/GaAs MODFETs with gate lengths as small as 0.25 mu m","authors":"H. Park, P. Mandeville, R. Saito, P. Tasker, W. Schaff, L. Eastman","doi":"10.1109/CORNEL.1989.79859","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79859","url":null,"abstract":"The authors have fabricated Al/sub 0.5/Ga/sub 0.5/As/GaAs MODFETs with gate length as small as 0.25 mu m and characterized them at both DC and RF in an effort to realize high-speed complementary MODFET circuits. Good gate characteristics, high current-drive capability, and high transconductance have been demonstrated. A current-gain cutoff frequency as high as 10 GHz has been obtained, and an effective hole velocity of 1.7*10/sup 6/ cm/s has been estimated from RF data. The device performance shows the potential of the p-channel MODFETs in high-speed complementary heterostructure circuits.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"425 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133166004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79840
S. Weinzierl, J. Krusius
Extensive Monte Carlo simulations of both steady-state and transient operation of a heterojunction vertical field-effect transistor (VFET) show that the discrepancy between measured and predicted cutoff frequencies for the device has two causes. First, experiments with lateral gate placement show that fabricated devices have not been optimized for high-speed performance. In addition, it is shown that because the operation of the devices in this study was governed by hot carrier transport and multidimensional space charge effects, previous predictions which did not take these phenomena into account are unrealistic. The structure and characteristics of the device used to verify the accuracy of the simulation method are described. A simple conceptual model which considers both local current continuity and space charges is presented for understanding the Monte Carlo results.<>
{"title":"Optimization of the design of the heterojunction vertical field effect transistor using a two-dimensional self-consistent Monte Carlo method","authors":"S. Weinzierl, J. Krusius","doi":"10.1109/CORNEL.1989.79840","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79840","url":null,"abstract":"Extensive Monte Carlo simulations of both steady-state and transient operation of a heterojunction vertical field-effect transistor (VFET) show that the discrepancy between measured and predicted cutoff frequencies for the device has two causes. First, experiments with lateral gate placement show that fabricated devices have not been optimized for high-speed performance. In addition, it is shown that because the operation of the devices in this study was governed by hot carrier transport and multidimensional space charge effects, previous predictions which did not take these phenomena into account are unrealistic. The structure and characteristics of the device used to verify the accuracy of the simulation method are described. A simple conceptual model which considers both local current continuity and space charges is presented for understanding the Monte Carlo results.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134183055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79838
S. Sriram, R. C. Clarke, R. Messham, T.J. Smith, M. Driver
Surface trapping effects are shown to affect adversely the RF power performance of high-voltage GaAs MESFETs and a model is presented to explain them. It is shown that the adverse effects of surface trapping can be minimized by: (1) including an undoped layer near the surface, (2) reducing the distance between the gate and n/sup +/ ledge, and (3) making the gate recess narrower than the gate. Devices fabricated with such a structure showed excellent RF power performance at 10 GHz: P/sub 0/=678 mW/mm, G /sub A/=6.8 dB, and eta /sub PA/=51.1% at a drain-bias voltage of 12 V. The design of devices to minimize surface-trapping effects is also expected to lead to self-passivating devices that will be inherently more reliable and show less 1/f noise. The high-voltage, high-efficiency devices described here will be applicable in airborne phased array radar systems where power supply requirements and heat dissipation problems limit system performance.<>
表面捕获效应对高压GaAs mesfet的射频功率性能有不利影响，并提出了一个模型来解释它们。结果表明，通过以下方法可以最大限度地减少表面捕获的不利影响:(1)在表面附近加入未掺杂层;(2)减小栅极与n/sup +/壁架之间的距离;(3)使栅极凹槽比栅极窄。在漏偏置电压为12 V时，采用该结构制备的器件在10 GHz频段表现出优异的射频功率性能:P/sub 0/=678 mW/mm, G /sub a /=6.8 dB, eta /sub PA/=51.1%。最小化表面捕获效应的器件设计也有望导致自钝化器件，其本质上更可靠，显示更少的1/f噪声。这里描述的高压、高效率器件将适用于机载相控阵雷达系统，其中电源要求和散热问题限制了系统性能。
{"title":"High voltage operation in class B GaAs X-band power MESFETs","authors":"S. Sriram, R. C. Clarke, R. Messham, T.J. Smith, M. Driver","doi":"10.1109/CORNEL.1989.79838","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79838","url":null,"abstract":"Surface trapping effects are shown to affect adversely the RF power performance of high-voltage GaAs MESFETs and a model is presented to explain them. It is shown that the adverse effects of surface trapping can be minimized by: (1) including an undoped layer near the surface, (2) reducing the distance between the gate and n/sup +/ ledge, and (3) making the gate recess narrower than the gate. Devices fabricated with such a structure showed excellent RF power performance at 10 GHz: P/sub 0/=678 mW/mm, G /sub A/=6.8 dB, and eta /sub PA/=51.1% at a drain-bias voltage of 12 V. The design of devices to minimize surface-trapping effects is also expected to lead to self-passivating devices that will be inherently more reliable and show less 1/f noise. The high-voltage, high-efficiency devices described here will be applicable in airborne phased array radar systems where power supply requirements and heat dissipation problems limit system performance.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124362126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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