Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79856
P.M. Mock, R. Trew
The results of a large-signal simulation of diamond IMPATT (impact avalanche and transit time) diodes are presented. The purpose of this investigation is to determine the potential of diamond IMPATTs as millimeter-wave power generators. This computer simulation is used to compare the performance of diamond IMPATTs with that of similar Si, GaAs, and InP devices. In addition, diamond IMPATT output power and power conversion efficiency are compared with experimental results on Si, GaAs and InP IMPATT and Gunn diodes. Thermal effects on the RF performance are investigated by means of an area-current-density plane analysis. The results indicate that diamond IMPATTs could produce power conversion efficiencies comparable to those of Si and GaAs. Due to their higher operating voltages and thermal conductivity, diamond IMPATTs could produce output power much greater than that of the other materials at frequencies below 100 GHz. At higher frequencies, diamond IMPATT performance is limited by its electrical properties and produces powers comparable to those of Si devices.<>
{"title":"Power generation of millimeter-wave diamond IMPATT diodes","authors":"P.M. Mock, R. Trew","doi":"10.1109/CORNEL.1989.79856","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79856","url":null,"abstract":"The results of a large-signal simulation of diamond IMPATT (impact avalanche and transit time) diodes are presented. The purpose of this investigation is to determine the potential of diamond IMPATTs as millimeter-wave power generators. This computer simulation is used to compare the performance of diamond IMPATTs with that of similar Si, GaAs, and InP devices. In addition, diamond IMPATT output power and power conversion efficiency are compared with experimental results on Si, GaAs and InP IMPATT and Gunn diodes. Thermal effects on the RF performance are investigated by means of an area-current-density plane analysis. The results indicate that diamond IMPATTs could produce power conversion efficiencies comparable to those of Si and GaAs. Due to their higher operating voltages and thermal conductivity, diamond IMPATTs could produce output power much greater than that of the other materials at frequencies below 100 GHz. At higher frequencies, diamond IMPATT performance is limited by its electrical properties and produces powers comparable to those of Si devices.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"367 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114049755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79834
D. Rathman, M. Hollis, R. A. Murphy, A. L. McWhorter, M. Mcnamara
The effects of variations in the vertical doping profiles of etched-emitter Si PBTs (permeable base transistors) on f/sub t/ and V/sub B/ have been investigated. CANDE, a two-dimensional simulation program, has been used to determine f/sub T/ as a function of V/sub CE/ and V/sub B/ for a number of profiles. A highly nonuniform doping profile (high-doped emitter, low-doped collector) results in a device with a higher V/sub B/ than a uniformly doped device for doping levels at which the maximum f/sub T/'s are identical. The range of V/sub CE/ over which f/sub T/ remains high is extended for the nonuniformly doped PBT, whereas the uniformly doped device shows a slow degradation from its maximum with increasing V/sub CE/. The enhancement in f/sub T/ and V/sub B/ observed for the nonuniformly doped case should make the device very useful in large-signal operation, particularly in class A. Experimental devices with both nonuniform and uniform doping profiles have been fabricated. The dependence of f/sub T/ on V/sub CE/ and VB are consistent with the model presented. Despite processing limitations which currently limit f/sub T/'s to 60% of their theoretical value and V/sub B/'s to 80% of their theoretical value, nonuniformly doped Si PBTs with f/sub T/=22 GHz at V/sub CE/=15 V and f/sub T/=12 GHz at C/sub CE/=26 V have been fabricated.<>
{"title":"Doping profile optimization in silicon permeable base transistors for high-frequency, high-voltage operation","authors":"D. Rathman, M. Hollis, R. A. Murphy, A. L. McWhorter, M. Mcnamara","doi":"10.1109/CORNEL.1989.79834","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79834","url":null,"abstract":"The effects of variations in the vertical doping profiles of etched-emitter Si PBTs (permeable base transistors) on f/sub t/ and V/sub B/ have been investigated. CANDE, a two-dimensional simulation program, has been used to determine f/sub T/ as a function of V/sub CE/ and V/sub B/ for a number of profiles. A highly nonuniform doping profile (high-doped emitter, low-doped collector) results in a device with a higher V/sub B/ than a uniformly doped device for doping levels at which the maximum f/sub T/'s are identical. The range of V/sub CE/ over which f/sub T/ remains high is extended for the nonuniformly doped PBT, whereas the uniformly doped device shows a slow degradation from its maximum with increasing V/sub CE/. The enhancement in f/sub T/ and V/sub B/ observed for the nonuniformly doped case should make the device very useful in large-signal operation, particularly in class A. Experimental devices with both nonuniform and uniform doping profiles have been fabricated. The dependence of f/sub T/ on V/sub CE/ and VB are consistent with the model presented. Despite processing limitations which currently limit f/sub T/'s to 60% of their theoretical value and V/sub B/'s to 80% of their theoretical value, nonuniformly doped Si PBTs with f/sub T/=22 GHz at V/sub CE/=15 V and f/sub T/=12 GHz at C/sub CE/=26 V have been fabricated.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127895350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79818
M. C. Driver, H. Nathanson, R. Freitag, G. W. Eldridge, R. C. Clarke, M. M. Sopira
A description is given of the Westinghouse RF Wafer-Scale Integration (RFWSI) program, a novel approach to controlling the cost of fighter aircraft radar modules. The technologies required for the program include three implants of silicon into 3-inch-diameter semi-insulating GaAs wafers and proton implants providing isolation between the closely spaced elements. Wafers will be cut so that a 'tile' containing several modules may be mounted on a carrier and form part of a tiled array of several hundred modules. Each tile will have electric feeds that pass through the gallium arsenide to the underlying layers. Integral to this structure are the cooling channels, the RF and DC manifolds for the distribution of signals, and the wideband flared notch antenna. Construction of an active array using this configuration will result in reduced assembly costs because the parts count is reduced. The implementation of this approach in the design of advanced fighter aircraft is considered.<>
{"title":"Wafer scale integration","authors":"M. C. Driver, H. Nathanson, R. Freitag, G. W. Eldridge, R. C. Clarke, M. M. Sopira","doi":"10.1109/CORNEL.1989.79818","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79818","url":null,"abstract":"A description is given of the Westinghouse RF Wafer-Scale Integration (RFWSI) program, a novel approach to controlling the cost of fighter aircraft radar modules. The technologies required for the program include three implants of silicon into 3-inch-diameter semi-insulating GaAs wafers and proton implants providing isolation between the closely spaced elements. Wafers will be cut so that a 'tile' containing several modules may be mounted on a carrier and form part of a tiled array of several hundred modules. Each tile will have electric feeds that pass through the gallium arsenide to the underlying layers. Integral to this structure are the cooling channels, the RF and DC manifolds for the distribution of signals, and the wideband flared notch antenna. Construction of an active array using this configuration will result in reduced assembly costs because the parts count is reduced. The implementation of this approach in the design of advanced fighter aircraft is considered.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128910382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79819
H. Grubin, J. P. Kreskovsky, R. Levy
The feasibility of using a physically based research algorithm to generate the coefficients for a nonlinear, equivalent-circuit model of an FET is demonstrated. The coefficients of the ordinary differential equations (ODES) representing the device are determined numerically using a model based on the drift and diffusion equations. The resulting ODE representation is then executed, and the validity of the results are verified, at select bias points, by performing accurate transient drift and diffusion simulations for steady AC operation into a simple resistive load. The comparison gives some degree of confidence in the equivalent-circuit model. However, it is stressed that the equivalent-circuit results must always be regarded as preliminary. It is always necessary to verify them against physical models and against experiments.<>
{"title":"Modeling of large signal device/circuit interactions","authors":"H. Grubin, J. P. Kreskovsky, R. Levy","doi":"10.1109/CORNEL.1989.79819","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79819","url":null,"abstract":"The feasibility of using a physically based research algorithm to generate the coefficients for a nonlinear, equivalent-circuit model of an FET is demonstrated. The coefficients of the ordinary differential equations (ODES) representing the device are determined numerically using a model based on the drift and diffusion equations. The resulting ODE representation is then executed, and the validity of the results are verified, at select bias points, by performing accurate transient drift and diffusion simulations for steady AC operation into a simple resistive load. The comparison gives some degree of confidence in the equivalent-circuit model. However, it is stressed that the equivalent-circuit results must always be regarded as preliminary. It is always necessary to verify them against physical models and against experiments.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115478385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79837
Y. Kwark, P. Solomon, D. La Tulipe
SISFETs where characterized at both room and liquid nitrogen (LN) temperatures to evaluate their dynamic performance. Equivalent circuit parameters obtained from low-frequency parametric measurements were compared to those deduced from S-parameter measurements. The measurements were made on a bifurcated gate structure consisting of two identical gate fingers totalling 70 mu m in width. Microwave characterization of the devices relied on measurement of the S-parameters over a 50-MHz-26-GHz range using an HP8510B network analyzer and cascade probes. The room- and LN-temperature characterization of SISFETs shows no evidence of anomalous behavior. The equivalent circuit parameters deduced from microwave measurements are consistent with those derived from the low-frequency measurements. The low gate leakage, improved g/sub m/, and unchanged gate capacitance result in a high f/sub T/ at LN temperatures, indicating potential for enhanced performance in digital systems.<>
{"title":"S-parameter characterization of GaAs gate SISFETs at liquid nitrogen temperatures","authors":"Y. Kwark, P. Solomon, D. La Tulipe","doi":"10.1109/CORNEL.1989.79837","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79837","url":null,"abstract":"SISFETs where characterized at both room and liquid nitrogen (LN) temperatures to evaluate their dynamic performance. Equivalent circuit parameters obtained from low-frequency parametric measurements were compared to those deduced from S-parameter measurements. The measurements were made on a bifurcated gate structure consisting of two identical gate fingers totalling 70 mu m in width. Microwave characterization of the devices relied on measurement of the S-parameters over a 50-MHz-26-GHz range using an HP8510B network analyzer and cascade probes. The room- and LN-temperature characterization of SISFETs shows no evidence of anomalous behavior. The equivalent circuit parameters deduced from microwave measurements are consistent with those derived from the low-frequency measurements. The low gate leakage, improved g/sub m/, and unchanged gate capacitance result in a high f/sub T/ at LN temperatures, indicating potential for enhanced performance in digital systems.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"503 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123198199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79823
G. Ng, A. Reynoso, J. Oh, D. Pavlidis, J. Graffeuil, P. Bhattacharya, M. Weiss, K. Moore
The low-frequency characteristics of lattice-matched (x=0.53) and strained (0.60>
晶格匹配(x=0.53)和应变(0.60)的低频特性
{"title":"Low-frequency properties of lattice matched and strained InGaAs/InAlAs HEMTs","authors":"G. Ng, A. Reynoso, J. Oh, D. Pavlidis, J. Graffeuil, P. Bhattacharya, M. Weiss, K. Moore","doi":"10.1109/CORNEL.1989.79823","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79823","url":null,"abstract":"The low-frequency characteristics of lattice-matched (x=0.53) and strained (0.60<or=x<or=0.70) In/sub x/Ga/sub 1-x/As/InAlAs HEMTs (high-electron-mobility transistors) are studied. Low-frequency noise measurements reveal shallow traps of 0.078 eV to 0.18 eV which have a slight dependence on In composition. The input noise spectra are almost insensitive to In percentage, but the output spectra suggest that the noise increases with strain. This is related to the increase of device gain with In composition and indicates that a compromise has to be made between high gain (large excess In %) and low noise (low excess In %). Transconductance dispersion is observed only under large gate bias and is absent when the device is biased for maximum g/sub m/. Trap densities seem to be largest for lattice-matched devices and minimum for 60% In channels.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133927096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79835
M. Steer, G. Bilbro, R. Trew, S. G. Skaggs
The authors have developed an alternative formulation of simulated annealing using a tree-based Metropolis procedure called tree annealing. Tree annealing is suited to continuous optimization problems and, in particular, to transistor parameter extraction. The tree annealing optimization algorithm was used to extract the parameters of the HBT (heterojunction bipolar transistor) of U.K. Mishra et al. (IEDM Tech. Dig., p.180-3, Dec. 1988) using a physically based equivalent circuit and deembedded scattering parameter measurements from 45 MHz to 26.5 GHz. Good results were obtained from the parameter extraction technique, and the ability of MFA not to be locked in local minima enabled a physically based equivalent circuit model to be used. Tree annealing is essentially a smart random search technique and so requires many more functional evaluations than do gradient-based minimization algorithms. However, no startling guess is required, and the bounds on parameter values can be widely separated with little effect on optimization time.<>
{"title":"Parameter extraction of microwave transistors using tree annealing","authors":"M. Steer, G. Bilbro, R. Trew, S. G. Skaggs","doi":"10.1109/CORNEL.1989.79835","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79835","url":null,"abstract":"The authors have developed an alternative formulation of simulated annealing using a tree-based Metropolis procedure called tree annealing. Tree annealing is suited to continuous optimization problems and, in particular, to transistor parameter extraction. The tree annealing optimization algorithm was used to extract the parameters of the HBT (heterojunction bipolar transistor) of U.K. Mishra et al. (IEDM Tech. Dig., p.180-3, Dec. 1988) using a physically based equivalent circuit and deembedded scattering parameter measurements from 45 MHz to 26.5 GHz. Good results were obtained from the parameter extraction technique, and the ability of MFA not to be locked in local minima enabled a physically based equivalent circuit model to be used. Tree annealing is essentially a smart random search technique and so requires many more functional evaluations than do gradient-based minimization algorithms. However, no startling guess is required, and the bounds on parameter values can be widely separated with little effect on optimization time.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"214 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134093926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79849
J. Tantillo, P. Cook, K. Evans, M.J. Martinez, R. Bobb, E. Martinez, C. E. Stutz, F. Schuermeyer
The initial results on the FET characteristics of pseudomorphic GaAsSb/AlGaAs p-HFETs (heterostructure FETs) on GaAs substrates are described. Curves showing the drain current versus drain voltage, gate current versus gate voltage, transconductance, and square root of drain current versus gate voltage are shown and discussed. The data confirm the improvement in gate characteristics due to an increased valence band discontinuity. The devices showed a large source resistance due to the recessed gate process utilized and the relatively low pinch-off voltage.<>
{"title":"p-HFETs with GaAsSb channel","authors":"J. Tantillo, P. Cook, K. Evans, M.J. Martinez, R. Bobb, E. Martinez, C. E. Stutz, F. Schuermeyer","doi":"10.1109/CORNEL.1989.79849","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79849","url":null,"abstract":"The initial results on the FET characteristics of pseudomorphic GaAsSb/AlGaAs p-HFETs (heterostructure FETs) on GaAs substrates are described. Curves showing the drain current versus drain voltage, gate current versus gate voltage, transconductance, and square root of drain current versus gate voltage are shown and discussed. The data confirm the improvement in gate characteristics due to an increased valence band discontinuity. The devices showed a large source resistance due to the recessed gate process utilized and the relatively low pinch-off voltage.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132971053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79828
K. Wang, R. Karunasiri
Several successful techniques for growth of pseudomorphic strained Ge/sub x/Si/sub 1-x/ layers on Si are briefly reviewed. The properties of the strained layers that affect the device design and performance are discussed. Devices based on the material are also discussed, with emphasis on heterojunction bipolar transistors (HBTs). High gain and high cutoff frequency has been predicted. Other advances, including the demonstration of tunneling structures, quantum well structures, and devices based on band-aligned superlattices, are presented. The growth of monolayer Ge/sub m/Si/sub n/ superlattices is discussed as well as the concept of Brillouin zone-folding and the formation of quasi-direct bandgaps.<>
{"title":"Properties and devices of SiGe heterostructures and superlattices","authors":"K. Wang, R. Karunasiri","doi":"10.1109/CORNEL.1989.79828","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79828","url":null,"abstract":"Several successful techniques for growth of pseudomorphic strained Ge/sub x/Si/sub 1-x/ layers on Si are briefly reviewed. The properties of the strained layers that affect the device design and performance are discussed. Devices based on the material are also discussed, with emphasis on heterojunction bipolar transistors (HBTs). High gain and high cutoff frequency has been predicted. Other advances, including the demonstration of tunneling structures, quantum well structures, and devices based on band-aligned superlattices, are presented. The growth of monolayer Ge/sub m/Si/sub n/ superlattices is discussed as well as the concept of Brillouin zone-folding and the formation of quasi-direct bandgaps.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122083943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-08-07DOI: 10.1109/CORNEL.1989.79821
A. Tessmer, P. Chao, K. Duh, P. Ho, M. Kao, S. Liu, P.M. Smith, J. Ballingall, A. Jabra, T. Yu
State-of-the-art high-electron-mobility-transistor (HEMT) devices have been fabricated on InAlAs/InGaAs/InP. Devices with 30- mu m and 50- mu m gate widths and 0.15- mu m gate length were fabricated using an all-electron-beam lithography process. After mesa formation, ohmic contacts were formed using a standard NiAuGe metallization. The contacts were annealed using a rapid thermal annealer. Typical ohmic contact resistance was approximately 0.13 Omega -mm. This is the same as the typical contact for the GaAs-based pseudomorphic HEMT result. Gates were defined using a trilayer resist scheme and recessed using a wet chemical etch to reach the desired channel current. A TiPtAu metallization forms the gate. The devices exhibited performance superior to most other low noise HEMT devices. It is found that the gate leakage current increases as recess depth increases. This current increase seems to degrade noise performance.<>
{"title":"Very high performance 0.15 mu m gate-length InAlAs/InGaAs/InP lattice-matched HEMTs","authors":"A. Tessmer, P. Chao, K. Duh, P. Ho, M. Kao, S. Liu, P.M. Smith, J. Ballingall, A. Jabra, T. Yu","doi":"10.1109/CORNEL.1989.79821","DOIUrl":"https://doi.org/10.1109/CORNEL.1989.79821","url":null,"abstract":"State-of-the-art high-electron-mobility-transistor (HEMT) devices have been fabricated on InAlAs/InGaAs/InP. Devices with 30- mu m and 50- mu m gate widths and 0.15- mu m gate length were fabricated using an all-electron-beam lithography process. After mesa formation, ohmic contacts were formed using a standard NiAuGe metallization. The contacts were annealed using a rapid thermal annealer. Typical ohmic contact resistance was approximately 0.13 Omega -mm. This is the same as the typical contact for the GaAs-based pseudomorphic HEMT result. Gates were defined using a trilayer resist scheme and recessed using a wet chemical etch to reach the desired channel current. A TiPtAu metallization forms the gate. The devices exhibited performance superior to most other low noise HEMT devices. It is found that the gate leakage current increases as recess depth increases. This current increase seems to degrade noise performance.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130724778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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