Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529629
Ufuk Yapar, Günhan Dündar
This paper presents the design of current-mode blocks to be used in modulator and decimator parts of continuous-time sigma-delta converters. Main blocks of sigma delta converters such as integrator and quantizer have been designed in current-mode. Through current-mode design, quantizer outputs are currents so that there is no need to use a voltage input/current output digital/analog converter in the feedback loop. Moreover, current-mode full-adder and delay elements have been designed which are main components of digital filters. Also a first-order modulator has been implemented and simulated.
{"title":"Current-mode circuits for sigma-delta converters","authors":"Ufuk Yapar, Günhan Dündar","doi":"10.1109/ECCTD.2007.4529629","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529629","url":null,"abstract":"This paper presents the design of current-mode blocks to be used in modulator and decimator parts of continuous-time sigma-delta converters. Main blocks of sigma delta converters such as integrator and quantizer have been designed in current-mode. Through current-mode design, quantizer outputs are currents so that there is no need to use a voltage input/current output digital/analog converter in the feedback loop. Moreover, current-mode full-adder and delay elements have been designed which are main components of digital filters. Also a first-order modulator has been implemented and simulated.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114177036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529577
G. Cataldo, G. Palumbo, M. Pennisi, S. Pennisi
The Miller theorem and its derivations are important tools to be used when analyzing feedback networks. However, they can be exploited in linear networks only. In this paper, we derive simple relationships which can be viewed as a generalization of the Miller theorem for nonlinear feedback elements. Their formulation results particularly useful when nonlinear circuits are analyzed to find, for example, harmonic distortion. Indeed, they allow to eliminate the nonlinear feedback, yielding more simple analytic relationships to be managed. The common emitter configuration is studied as an example, and comparisons between expected and simulated data confirm the validity and the accuracy of the analysis developed.
{"title":"A generalization of Miller formulae for nonlinear feedback networks","authors":"G. Cataldo, G. Palumbo, M. Pennisi, S. Pennisi","doi":"10.1109/ECCTD.2007.4529577","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529577","url":null,"abstract":"The Miller theorem and its derivations are important tools to be used when analyzing feedback networks. However, they can be exploited in linear networks only. In this paper, we derive simple relationships which can be viewed as a generalization of the Miller theorem for nonlinear feedback elements. Their formulation results particularly useful when nonlinear circuits are analyzed to find, for example, harmonic distortion. Indeed, they allow to eliminate the nonlinear feedback, yielding more simple analytic relationships to be managed. The common emitter configuration is studied as an example, and comparisons between expected and simulated data confirm the validity and the accuracy of the analysis developed.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125316631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529575
P. Crombez, J. Craninckx, P. Wambacq, M. Steyaert
In analog design, a good understanding of nonlinear behavior is crucial and should be taken into account early in the design flow at the architectural level. This paper presents the design towards optimal linearity of a biquadratic section of a gm-C low-pass filter based on Nauta's transconductor. First, Volterra analysis is extended from circuit to architectural level by means of macro models. At circuit level, Volterra is used to optimize and size the transconductor while at architectural level, Volterra series define the main nonlinearity contributors of the biquad and hence allow to set the optimal filter parameters. These results are then translated into a design rule for optimal linearity in the full bandwidth at architectural level. Finally, a bottom-up verification is performed using circuit simulations to confirm the optimum. Both methods are applied on a 10 MHz Butterworth filter, designed in 0.13 mum CMOS. It achieves a SFDR of 67 dB and consumes 3 mW from a 1.2 V supply.
在模拟设计中，很好地理解非线性行为是至关重要的，应该在架构级别的设计流程的早期考虑到这一点。本文提出了一种基于Nauta公司晶体管的gm-C低通滤波器双二次段的最佳线性设计方法。首先，通过宏观模型将Volterra分析从电路层面扩展到架构层面。在电路级，Volterra用于优化和调整晶体管的尺寸，而在架构级，Volterra系列定义了biquad的主要非线性贡献者，从而允许设置最佳滤波器参数。然后将这些结果转化为在架构级别的全带宽中实现最佳线性的设计规则。最后，利用电路仿真进行了自下而上的验证，以确定最优方案。这两种方法都应用于在0.13 μ m CMOS中设计的10 MHz巴特沃斯滤波器。它实现67 dB的SFDR，并从1.2 V电源消耗3 mW。
{"title":"Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis","authors":"P. Crombez, J. Craninckx, P. Wambacq, M. Steyaert","doi":"10.1109/ECCTD.2007.4529575","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529575","url":null,"abstract":"In analog design, a good understanding of nonlinear behavior is crucial and should be taken into account early in the design flow at the architectural level. This paper presents the design towards optimal linearity of a biquadratic section of a gm-C low-pass filter based on Nauta's transconductor. First, Volterra analysis is extended from circuit to architectural level by means of macro models. At circuit level, Volterra is used to optimize and size the transconductor while at architectural level, Volterra series define the main nonlinearity contributors of the biquad and hence allow to set the optimal filter parameters. These results are then translated into a design rule for optimal linearity in the full bandwidth at architectural level. Finally, a bottom-up verification is performed using circuit simulations to confirm the optimum. Both methods are applied on a 10 MHz Butterworth filter, designed in 0.13 mum CMOS. It achieves a SFDR of 67 dB and consumes 3 mW from a 1.2 V supply.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529773
Cenk Dincbakir, M. Bilgiç
A gyrator design based on an inductor coupled double bridge converter is presented. It is shown that this gyrator can operate in four-quadrant mode by using bi-directional MOS switches without the necessity of any feedback control circuit. There are different usage areas of such a gyrator. Some of which can be used for conversions of voltage to current, current to voltage, capacitor to inductor and Resistance to Resistance. In this paper, the dynamic and static gyrator behavior is first simulated and some of above conversions are also tested.
{"title":"Four-quadrant switch-mode gyrator","authors":"Cenk Dincbakir, M. Bilgiç","doi":"10.1109/ECCTD.2007.4529773","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529773","url":null,"abstract":"A gyrator design based on an inductor coupled double bridge converter is presented. It is shown that this gyrator can operate in four-quadrant mode by using bi-directional MOS switches without the necessity of any feedback control circuit. There are different usage areas of such a gyrator. Some of which can be used for conversions of voltage to current, current to voltage, capacitor to inductor and Resistance to Resistance. In this paper, the dynamic and static gyrator behavior is first simulated and some of above conversions are also tested.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529616
R. Costea, C. Marinov
An analog Hopfield type network with O (N2) interconnections and capacitive coupling between cells is considered and designed as an analog sorter. A rigorous mathematical treatment provides new bounds for the processing and resetting time intervals. These are combined with the WTA demands for a complete design procedure.
{"title":"Clocking and WTA design of a continuous time Hopfield net with parasitic capacitances","authors":"R. Costea, C. Marinov","doi":"10.1109/ECCTD.2007.4529616","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529616","url":null,"abstract":"An analog Hopfield type network with O (N2) interconnections and capacitive coupling between cells is considered and designed as an analog sorter. A rigorous mathematical treatment provides new bounds for the processing and resetting time intervals. These are combined with the WTA demands for a complete design procedure.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126544612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529776
Caitriona Boushel, P. Curran
A novel second order neuron is presented which exhibits the principal bifurcations observed in the Hodgkin-Huxley (HH) neuron. The new model is based on the topological normal form for the Bautin bifurcation. The effect of electrical coupling on the local dynamics of the equilibrium of two coupled second order neurons is shown to be similar to the effect of coupling on the local dynamics of the equilibrium of two coupled HH neurons. In particular, the equilibriums of both types of coupled neurons experience a Hopf bifurcation as the coupling parameter is increased from zero.
{"title":"The bifurcation behaviour of a novel second order model of the Hodgkin-Huxley Neuron","authors":"Caitriona Boushel, P. Curran","doi":"10.1109/ECCTD.2007.4529776","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529776","url":null,"abstract":"A novel second order neuron is presented which exhibits the principal bifurcations observed in the Hodgkin-Huxley (HH) neuron. The new model is based on the topological normal form for the Bautin bifurcation. The effect of electrical coupling on the local dynamics of the equilibrium of two coupled second order neurons is shown to be similar to the effect of coupling on the local dynamics of the equilibrium of two coupled HH neurons. In particular, the equilibriums of both types of coupled neurons experience a Hopf bifurcation as the coupling parameter is increased from zero.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"95 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122703148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529657
L. Labrak, T. Tixier, Y. Fellah, N. Abouchi
In this article, we present a new method to improve analog design automation and design reuse. A top-down constraint driven methodology is applied to design complex analog system. This approach formulates the design problem as a multi objective optimization problem (MOOP). As the knowledge needed to build an optimization problem dedicated to an analog circuit is still out of reach of designers, our approach propose a new efficient way to capture design performance metrics allowing an automatic optimization problem formulation. Based only on performance specifications (e.g., gain of 80 dB) and preferences of the designers (i.e, maximize or minimize a given performance metric), a multi objective optimisation problem (MOOP) is built. An example using hybrid algorithm consisting in coupling a pattern search based algorithm and a conjugate gradient based one to solve the MOOP for a CMOS two stage opamp is given.
{"title":"Automated cost function formulation for analog design optimization","authors":"L. Labrak, T. Tixier, Y. Fellah, N. Abouchi","doi":"10.1109/ECCTD.2007.4529657","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529657","url":null,"abstract":"In this article, we present a new method to improve analog design automation and design reuse. A top-down constraint driven methodology is applied to design complex analog system. This approach formulates the design problem as a multi objective optimization problem (MOOP). As the knowledge needed to build an optimization problem dedicated to an analog circuit is still out of reach of designers, our approach propose a new efficient way to capture design performance metrics allowing an automatic optimization problem formulation. Based only on performance specifications (e.g., gain of 80 dB) and preferences of the designers (i.e, maximize or minimize a given performance metric), a multi objective optimisation problem (MOOP) is built. An example using hybrid algorithm consisting in coupling a pattern search based algorithm and a conjugate gradient based one to solve the MOOP for a CMOS two stage opamp is given.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122712795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529754
D. Durini, W. Brockherde, B. Hosticka
Concept and experimental results obtained from a pixel detector based on CMOS time-compression charge- injection-devices (TC-CID) with a huge internal photocurrent amplification (-104), fabricated in CMOS silicon-on-insulator (SOI) technology are presented. Here, the readout circuitry is fabricated on highly-doped, 200 nm thick SOI film, while the photogate (PG) detector is fabricated on higher-resistivity handle wafer. The latter, together with the 30 V biasing possibilities enhances the quantum efficiency, especially for irradiations with wavelengths in the near-infra-red (NIR) part of the spectra.
{"title":"SOI pixel detector based on CMOS time-compression charge-injection","authors":"D. Durini, W. Brockherde, B. Hosticka","doi":"10.1109/ECCTD.2007.4529754","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529754","url":null,"abstract":"Concept and experimental results obtained from a pixel detector based on CMOS time-compression charge- injection-devices (TC-CID) with a huge internal photocurrent amplification (-104), fabricated in CMOS silicon-on-insulator (SOI) technology are presented. Here, the readout circuitry is fabricated on highly-doped, 200 nm thick SOI film, while the photogate (PG) detector is fabricated on higher-resistivity handle wafer. The latter, together with the 30 V biasing possibilities enhances the quantum efficiency, especially for irradiations with wavelengths in the near-infra-red (NIR) part of the spectra.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121737794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529703
P. Monsurrò, G. Scotti, A. Trifiletti, S. Pennisi
A minimum-supply rail-to-rail differential stage architecture is presented. It exhibits easy cascading features and unlike previous similar solutions does not critically affect CMRR. Starting from this block, a fully-differential two-stage amplifier is designed using 0.7-V supply in a 130-nm CMOS technology. Simulations show a 47-dB dc differential gain with a gain-bandwidth product of 700 MHz, and 70-dB CMRR at dc, under a total nominal current consumption lower than 2 mA.
{"title":"Very low voltage CMOS two-stage amplifier","authors":"P. Monsurrò, G. Scotti, A. Trifiletti, S. Pennisi","doi":"10.1109/ECCTD.2007.4529703","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529703","url":null,"abstract":"A minimum-supply rail-to-rail differential stage architecture is presented. It exhibits easy cascading features and unlike previous similar solutions does not critically affect CMRR. Starting from this block, a fully-differential two-stage amplifier is designed using 0.7-V supply in a 130-nm CMOS technology. Simulations show a 47-dB dc differential gain with a gain-bandwidth product of 700 MHz, and 70-dB CMRR at dc, under a total nominal current consumption lower than 2 mA.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125042072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529549
S. A. Jawed, D. Cattin, N. Massari, M. Gottardi, B. Margesin, A. Baschirotto
This paper reports two behavioral models for a MEMS capacitive sensor and presents their simulation results for a bootstrapped continuous-time pre-amplifier. The first model uses a simplistic voltage-source based approach to imitate the variable capacitance in the sensor, while the other accurately models the mechanical and electrostatic forces inside the sensor in VerilogA. It is demonstrated through simulation results that the simple model can be used for a large input range without considerable differences as compared to the accurate model, proving it viable for functional simulations. Whereas, the accurate model traces the performance of the pre-amplifier in the presence of mechanical and electrostatic limitations of the sensor, revealing differences in the results for those cases where the non-linear response of the sensor is not negligible.
{"title":"A simplified modeling approach for a MEMS capacitive sensor","authors":"S. A. Jawed, D. Cattin, N. Massari, M. Gottardi, B. Margesin, A. Baschirotto","doi":"10.1109/ECCTD.2007.4529549","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529549","url":null,"abstract":"This paper reports two behavioral models for a MEMS capacitive sensor and presents their simulation results for a bootstrapped continuous-time pre-amplifier. The first model uses a simplistic voltage-source based approach to imitate the variable capacitance in the sensor, while the other accurately models the mechanical and electrostatic forces inside the sensor in VerilogA. It is demonstrated through simulation results that the simple model can be used for a large input range without considerable differences as compared to the accurate model, proving it viable for functional simulations. Whereas, the accurate model traces the performance of the pre-amplifier in the presence of mechanical and electrostatic limitations of the sensor, revealing differences in the results for those cases where the non-linear response of the sensor is not negligible.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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