Pub Date : 2022-03-30DOI: 10.1109/OJNANO.2022.3163386
Akeeb Hassan;Sepehr Soroushiani;Abdulhameed Abdal;Sk Yeahia Been Sayeed;Wei-Chiang Lin;Markondeya Raj Pulugurtha
Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.
{"title":"Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications","authors":"Akeeb Hassan;Sepehr Soroushiani;Abdulhameed Abdal;Sk Yeahia Been Sayeed;Wei-Chiang Lin;Markondeya Raj Pulugurtha","doi":"10.1109/OJNANO.2022.3163386","DOIUrl":"10.1109/OJNANO.2022.3163386","url":null,"abstract":"Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"52-60"},"PeriodicalIF":1.7,"publicationDate":"2022-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9745373","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-27DOI: 10.1109/OJNANO.2022.3178545
Hilal Ahmad Bhat;Farooq Ahmad Khanday;Brajesh Kumar Kaushik;Faisal Bashir;Khurshed Ahmad Shah
Quantum Computing is a technology, which promises to overcome the drawbacks of conventional CMOS technology for high density and high performance applications. Its potential to revolutionize today's computing world is attracting more and more researchers towards this field. However, due to the involvement of quantum properties, many beginners find it difficult to follow the field. Therefore, in this research note an effort has been made to introduce the various aspects of quantum computing to researchers, quantum engineers and scientists. The historical background and basic concepts necessary to understand quantum computation and information processing have been introduced in a lucid manner. Various physical implementations and potential application areas of quantum computation have also been discussed in this paper. Recent developments in each realization, in the context of the DiVincenzo criteria, including ion traps based quantum computing, superconducting quantum computing, nuclear magnetic resonance (NMR) quantum computing, spintronics and semiconductor based quantum computing have been discussed.
{"title":"Quantum Computing: Fundamentals, Implementations and Applications","authors":"Hilal Ahmad Bhat;Farooq Ahmad Khanday;Brajesh Kumar Kaushik;Faisal Bashir;Khurshed Ahmad Shah","doi":"10.1109/OJNANO.2022.3178545","DOIUrl":"10.1109/OJNANO.2022.3178545","url":null,"abstract":"Quantum Computing is a technology, which promises to overcome the drawbacks of conventional CMOS technology for high density and high performance applications. Its potential to revolutionize today's computing world is attracting more and more researchers towards this field. However, due to the involvement of quantum properties, many beginners find it difficult to follow the field. Therefore, in this research note an effort has been made to introduce the various aspects of quantum computing to researchers, quantum engineers and scientists. The historical background and basic concepts necessary to understand quantum computation and information processing have been introduced in a lucid manner. Various physical implementations and potential application areas of quantum computation have also been discussed in this paper. Recent developments in each realization, in the context of the DiVincenzo criteria, including ion traps based quantum computing, superconducting quantum computing, nuclear magnetic resonance (NMR) quantum computing, spintronics and semiconductor based quantum computing have been discussed.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"61-77"},"PeriodicalIF":1.7,"publicationDate":"2022-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9783210","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-23DOI: 10.1109/OJNANO.2022.3153329
Ke Chen;Weiqiang Liu;Ahmed Louri;Fabrizio Lombardi
A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.
{"title":"Low-Power Approximate RPR Scheme for Unsigned Integer Arithmetic Computation","authors":"Ke Chen;Weiqiang Liu;Ahmed Louri;Fabrizio Lombardi","doi":"10.1109/OJNANO.2022.3153329","DOIUrl":"https://doi.org/10.1109/OJNANO.2022.3153329","url":null,"abstract":"A scheme often used for error tolerance of arithmetic circuits is the so-called Reduced Precision Redundancy (RPR). Rather than replicating multiple times the entire module, RPR uses reduced precision (inexact) copies to significantly reduce the redundancy overhead, while still being able to correct the largest errors. This paper focuses on the low-power operation for RPR; a new scheme is proposed. At circuit level, power gating is initially utilized in the arithmetic modules to power off one of the modules (i.e., the exact module) when the inexact modules’ error is smaller than the threshold. The proposed design is applicable to (unsigned integer) addition, multiplication, and MAC (multiply and add) by proposing RPR implementations that reduce the power consumption with a limited impact on its error correction capability. The proposed schemes have been implemented and tested for various applications (image and DCT processing). The results show that they can significantly reduce power consumption; moreover, the simulation results show that the Mean Square Error (MSE) at the proposed schemes’ output is low.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"36-44"},"PeriodicalIF":1.7,"publicationDate":"2022-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09720147.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3477918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJNANO.2023.3234525
Presents the 2022 author/subject index for this issue of the publication.
给出了本期出版物的2022年作者/主题索引。
{"title":"2022 Index IEEE Open Journal of Nanotechnology Vol. 3","authors":"","doi":"10.1109/OJNANO.2023.3234525","DOIUrl":"10.1109/OJNANO.2023.3234525","url":null,"abstract":"Presents the 2022 author/subject index for this issue of the publication.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"244-250"},"PeriodicalIF":1.7,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10007541","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-24DOI: 10.1109/OJNANO.2021.3138344
Amit Kumar;Brajesh Kumar Kaushik
This paper presents the transient analysis of the equivalent single conductor (ESC) model of hybrid Cu-CNT on-chip interconnects for nanopackaging using matrix rational approximation (MRA) modeling technique. The analysis of propagation delay and peak crosstalk noise is carried out for single and coupled Cu-CNT interconnect lines at 14 nm and 22 nm technology nodes. It has been observed that the proposed MRA model provides a speed-up factor of 131 compared to the HSPICE. An error of less than 1% confirms the accuracy of the proposed model compared to the SPICE simulations. It is observed that Cu-CNT lines are more immune to the crosstalk due to lesser coupling effects compared to Cu and CNT interconnects. The efficacy, accuracy, and comprehensive analysis using the proposed model ensures immense application possibility of the proposed model in the VLSI design automation tools at the nanopackaging level.
{"title":"Transient Analysis of Hybrid Cu-CNT On-Chip Interconnects Using MRA Technique","authors":"Amit Kumar;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2021.3138344","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3138344","url":null,"abstract":"This paper presents the transient analysis of the equivalent single conductor (ESC) model of hybrid Cu-CNT on-chip interconnects for nanopackaging using matrix rational approximation (MRA) modeling technique. The analysis of propagation delay and peak crosstalk noise is carried out for single and coupled Cu-CNT interconnect lines at 14 nm and 22 nm technology nodes. It has been observed that the proposed MRA model provides a speed-up factor of 131 compared to the HSPICE. An error of less than 1% confirms the accuracy of the proposed model compared to the SPICE simulations. It is observed that Cu-CNT lines are more immune to the crosstalk due to lesser coupling effects compared to Cu and CNT interconnects. The efficacy, accuracy, and comprehensive analysis using the proposed model ensures immense application possibility of the proposed model in the VLSI design automation tools at the nanopackaging level.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"24-35"},"PeriodicalIF":1.7,"publicationDate":"2021-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09663009.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3514042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-24DOI: 10.1109/OJNANO.2021.3134382
Attila Bonyar;Brajesh Kumar Kaushik;James E. Morris
This is the first of two Special Sections on Nanopackaging. This first one has appeared in OJ-NANO Vol. 2, 2021 and the second will appear in Vol. 3, 2022. Electronics packaging is a very multidisciplinary activity requiring an understanding of Electrical, Mechanical, Materials, Thermal (and Thermomechanical) Engineering, and of the underlying Physics and Chemistry. The papers in these two Special sections will reflect this diversity, and the application of modern mathematical algorithms and computational techniques to advance the engineering design techniques. Nanopackaging could refer to the packaging of possibly disruptive nanoelectronics technologies, and this would undoubtedly be a challenging and useful field, but so far, the term has been applied more to the application of nanotechnologies to microelectronics packaging. Although this is the case with some of the papers in this collection, two are particularly driven by the packaging needs of the continuation of Moore’s Law into advanced nanoscales.
{"title":"Guest Editorial: Nanopackaging Part I","authors":"Attila Bonyar;Brajesh Kumar Kaushik;James E. Morris","doi":"10.1109/OJNANO.2021.3134382","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3134382","url":null,"abstract":"This is the first of two Special Sections on Nanopackaging. This first one has appeared in OJ-NANO Vol. 2, 2021 and the second will appear in Vol. 3, 2022. Electronics packaging is a very multidisciplinary activity requiring an understanding of Electrical, Mechanical, Materials, Thermal (and Thermomechanical) Engineering, and of the underlying Physics and Chemistry. The papers in these two Special sections will reflect this diversity, and the application of modern mathematical algorithms and computational techniques to advance the engineering design techniques. Nanopackaging could refer to the packaging of possibly disruptive nanoelectronics technologies, and this would undoubtedly be a challenging and useful field, but so far, the term has been applied more to the application of nanotechnologies to microelectronics packaging. Although this is the case with some of the papers in this collection, two are particularly driven by the packaging needs of the continuation of Moore’s Law into advanced nanoscales.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"201-202"},"PeriodicalIF":1.7,"publicationDate":"2021-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09662658.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3515812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-15DOI: 10.1109/OJNANO.2021.3135478
Guanxuan Lu;Jiaqi Wang;Zhemiao Xie;John T. W. Yeow
Increasing demands for high-speed wireless communication have stimulated the development of novel optoelectrical devices. Typically, terahertz (THz) wave, is much advantageous because of its relatively high-resolution transportation and strong penetrability property. One of the electromagnetic devices, the antenna, plays a key role in future THz devices. However, there are few review publishments related to carbon-based THz microstrip antenna designs. In this article, we list the basic figure of merits for evaluating antennas. We also show the developing microstrip antenna structures. Importantly, we summarize the current progress of THz microstrip antennas using different dimensional carbon materials, such as carbon nanotubes, graphene, and carbon foams. This review will lay a solid foundation for carbon-based THz microstrip antenna design, and furthermore provide novel sights for other THz antenna designs.
{"title":"Carbon-Based THz Microstrip Antenna Design: A Review","authors":"Guanxuan Lu;Jiaqi Wang;Zhemiao Xie;John T. W. Yeow","doi":"10.1109/OJNANO.2021.3135478","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3135478","url":null,"abstract":"Increasing demands for high-speed wireless communication have stimulated the development of novel optoelectrical devices. Typically, terahertz (THz) wave, is much advantageous because of its relatively high-resolution transportation and strong penetrability property. One of the electromagnetic devices, the antenna, plays a key role in future THz devices. However, there are few review publishments related to carbon-based THz microstrip antenna designs. In this article, we list the basic figure of merits for evaluating antennas. We also show the developing microstrip antenna structures. Importantly, we summarize the current progress of THz microstrip antennas using different dimensional carbon materials, such as carbon nanotubes, graphene, and carbon foams. This review will lay a solid foundation for carbon-based THz microstrip antenna design, and furthermore provide novel sights for other THz antenna designs.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"15-23"},"PeriodicalIF":1.7,"publicationDate":"2021-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09652034.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3476147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-14DOI: 10.1109/OJNANO.2021.3135364
Amit Degada;Himanshu Thapliyal
Designing energy-efficient and secure cryptographic circuits in low-frequency medical devices are challenging due to low-energy requirements. Also, the conventional CMOS logic-based cryptographic circuits solutions in medical devices can be vulnerable to side-channel attacks (e.g. correlation power analysis (CPA)). In this article, we explored single-rail Clocked CMOS Adiabatic Logic (CCAL) to design an energy-efficient and secure cryptographic circuit for low-frequency medical devices. The performance of the CCAL logic-based circuits was checked with a power clock generator (2N2P-PCG) integrated into the design for the frequency range of 50 kHz to 250 kHz. The CCAL logic gates show an average of approximately 48% energy-saving and more than 95% improvement in security metrics performance compared to its CMOS logic gate counterparts. Further, the CCAL based circuits are also compared for energy-saving performance against dual-rail adiabatic logic, 2-EE-SPFAL, and 2-SPGAL. The adiabatic CCAL gates save on an average of 55% energy saving compared to 2-EE-SPFAL and 2-SPGAL over the frequency range of 50 kHz to 250 kHz. To check the efficacy of CCAL to design a larger cryptographic circuit, we implemented a case-study design of a Substitution-box (S-box) of popular lightweight PRESENT-80 encryption. The case-study implementation (2N2P-PCG integrated into the design) using CCAL shows more than 95% energy saving compared to CMOS for the frequency 50 kHz to 125 kHz and around 60% energy saving at frequency 250 kHz. At 250 kHz, compared to the dual-rail adiabatic designs of S-box based on 2-EE-SPFAL and 2-SPGAL, the CCAL based S-box shows 32.67% and 11.21% of energy savings, respectively. Additionally, the CCAL logic gate structure requires a lesser number of transistors compared to dual-rail adiabatic logic. The case-study implementation using CCAL saves 45.74% and 34.88% transistor counts compared to 2-EE-SPFAL and 2-SPGAL. The article also presents the effect of varying tank capacitance in 2N2P-PCG over energy efficiency and security performance. The CCAL based case-study was also subjected against CPA. The CCAL-based S-box case study successfully protects the revelation of the encryption key against the CPA attack, However, the key was revealed in CMOS-based case-study implementation.
由于低能量要求，在低频医疗设备中设计节能和安全的加密电路具有挑战性。此外，医疗设备中传统的基于CMOS逻辑的加密电路解决方案容易受到侧信道攻击(例如相关功率分析(CPA))。在本文中，我们探索了单轨时钟CMOS绝热逻辑(CCAL)来设计一种节能和安全的低频医疗设备加密电路。在50 kHz至250 kHz的频率范围内，通过将功率时钟发生器(2N2P-PCG)集成到设计中来检查基于CCAL逻辑的电路的性能。与CMOS逻辑门相比，CCAL逻辑门平均节能约48%，安全指标性能提高95%以上。此外，还比较了基于CCAL的电路与双轨绝热逻辑、2- ee - spal和2-SPGAL的节能性能。在50 kHz至250 kHz的频率范围内，与2-EE-SPFAL和2-SPGAL相比，绝热CCAL门平均节省55%的能源。为了验证CCAL在设计更大的加密电路中的有效性，我们实现了一个流行的轻量级PRESENT-80加密的替换盒(S-box)的案例研究设计。使用CCAL的案例研究实现(2N2P-PCG集成到设计中)显示，与CMOS相比，在50 kHz至125 kHz频率下节能95%以上，在250 kHz频率下节能约60%。在250 kHz时，与基于2- ee - spal和2-SPGAL的S-box双轨绝热设计相比，基于CCAL的S-box分别节能32.67%和11.21%。此外，与双轨绝热逻辑相比，CCAL逻辑门结构需要更少的晶体管数量。与2- ee - spal和2-SPGAL相比，使用CCAL的案例研究实现节省了45.74%和34.88%的晶体管数量。本文还介绍了2N2P-PCG中不同油箱电容对能效和安全性能的影响。基于CCAL的案例研究也受到CPA的影响。基于ccal的S-box案例研究成功地保护了加密密钥的泄露免受CPA攻击，但在基于cmos的案例研究实现中，密钥被泄露。
{"title":"Single-Rail Adiabatic Logic for Energy-Efficient and CPA-Resistant Cryptographic Circuit in Low-Frequency Medical Devices","authors":"Amit Degada;Himanshu Thapliyal","doi":"10.1109/OJNANO.2021.3135364","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3135364","url":null,"abstract":"Designing energy-efficient and secure cryptographic circuits in low-frequency medical devices are challenging due to low-energy requirements. Also, the conventional CMOS logic-based cryptographic circuits solutions in medical devices can be vulnerable to side-channel attacks (e.g. correlation power analysis (CPA)). In this article, we explored single-rail Clocked CMOS Adiabatic Logic (CCAL) to design an energy-efficient and secure cryptographic circuit for low-frequency medical devices. The performance of the CCAL logic-based circuits was checked with a power clock generator (2N2P-PCG) integrated into the design for the frequency range of 50 kHz to 250 kHz. The CCAL logic gates show an average of approximately 48% energy-saving and more than 95% improvement in security metrics performance compared to its CMOS logic gate counterparts. Further, the CCAL based circuits are also compared for energy-saving performance against dual-rail adiabatic logic, 2-EE-SPFAL, and 2-SPGAL. The adiabatic CCAL gates save on an average of 55% energy saving compared to 2-EE-SPFAL and 2-SPGAL over the frequency range of 50 kHz to 250 kHz. To check the efficacy of CCAL to design a larger cryptographic circuit, we implemented a case-study design of a Substitution-box (S-box) of popular lightweight PRESENT-80 encryption. The case-study implementation (2N2P-PCG integrated into the design) using CCAL shows more than 95% energy saving compared to CMOS for the frequency 50 kHz to 125 kHz and around 60% energy saving at frequency 250 kHz. At 250 kHz, compared to the dual-rail adiabatic designs of S-box based on 2-EE-SPFAL and 2-SPGAL, the CCAL based S-box shows 32.67% and 11.21% of energy savings, respectively. Additionally, the CCAL logic gate structure requires a lesser number of transistors compared to dual-rail adiabatic logic. The case-study implementation using CCAL saves 45.74% and 34.88% transistor counts compared to 2-EE-SPFAL and 2-SPGAL. The article also presents the effect of varying tank capacitance in 2N2P-PCG over energy efficiency and security performance. The CCAL based case-study was also subjected against CPA. The CCAL-based S-box case study successfully protects the revelation of the encryption key against the CPA attack, However, the key was revealed in CMOS-based case-study implementation.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"1-14"},"PeriodicalIF":1.7,"publicationDate":"2021-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9680797/09650767.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3511373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-07DOI: 10.1109/OJNANO.2021.3133213
Akash Jain;Heman Vaghasiya;Jai Narayan Tripathi
In the era of advanced nanotechnology where billions of transistors are fabricated in a single chip, high-speed operations are challenging due to packaging related issues. In High-Speed Very Large Scale Integration (VLSI) systems, decoupling capacitors are essentially used in power delivery networks to reduce power supply noise and to maintain a low impedance of the power delivery networks. In this paper, the cumulative impedance of a power delivery network is reduced below the target impedance by using state-of-the-art metaheuristic algorithms to choose and place decoupling capacitors optimally. A Matrix-based Evolutionary Computing (MEC) approach is used for efficient usage of metaheuristic algorithms. Two case studies are presented on a practical system to demonstrate the proposed approach. A comparative analysis of the performance of state-of-the-art metaheuristics is presented with the insights of practical implementation. The consistency of results in both the case studies confirms the validity of the proposed appraoch.
{"title":"Efficient Selection and Placement of In-Package Decoupling Capacitors Using Matrix-Based Evolutionary Computation","authors":"Akash Jain;Heman Vaghasiya;Jai Narayan Tripathi","doi":"10.1109/OJNANO.2021.3133213","DOIUrl":"https://doi.org/10.1109/OJNANO.2021.3133213","url":null,"abstract":"In the era of advanced nanotechnology where billions of transistors are fabricated in a single chip, high-speed operations are challenging due to packaging related issues. In High-Speed Very Large Scale Integration (VLSI) systems, decoupling capacitors are essentially used in power delivery networks to reduce power supply noise and to maintain a low impedance of the power delivery networks. In this paper, the cumulative impedance of a power delivery network is reduced below the target impedance by using state-of-the-art metaheuristic algorithms to choose and place decoupling capacitors optimally. A Matrix-based Evolutionary Computing (MEC) approach is used for efficient usage of metaheuristic algorithms. Two case studies are presented on a practical system to demonstrate the proposed approach. A comparative analysis of the performance of state-of-the-art metaheuristics is presented with the insights of practical implementation. The consistency of results in both the case studies confirms the validity of the proposed appraoch.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"2 ","pages":"191-200"},"PeriodicalIF":1.7,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/9316416/09640572.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3500653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-07DOI: 10.1109/OJNANO.2021.3133325
Jai Narayan Tripathi;Heman Vaghasiya;Dinesh Junjariya;Aksh Chordia
Interconnects are essential components of any electronic system. Their design, modeling and optimization are becoming complex and computationally expensive with the evolution of semiconductor technology as the devices of nanometer dimensions are being used. In high-speed applications, system level simulations are needed to ensure the robustness of a system in terms of signal and power quality. The simulations are becoming very expensive because of the large dimensional systems and their full-wave models. Machine learning techniques can be used as computationally efficient alternatives in the design cycle of the interconnects. This paper presents a review of the applications of machine learning techniques for design, optimization and analysis of interconnects in high-speed electronic systems. A holistic discussion is presented, including the basics of interconnects, their impact on the system performance, popular machine learning techniques and their applications related to the interconnects. The performance evaluation, optimization and variability analysis of interconnects are discussed in detail. Future scope and overlook that are presented in the literature are also discussed.
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