Spintronic Physically Unclonable Functions (PUFs) show promise in enhancing electronic system security due to their inherent randomness, low energy consumption, fast response times, and temperature stability. This paper presents a novel PUF based on voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) that compares the resistance of MTJ cells utilizing intrinsic process variations to get an output response. Compared to arbiter PUFs, the proposed PUF provides a significantly larger effective challenge-response pair (CRP) space by supporting multiple independent configurations and is also reconfigurable. The Proposed VGSOT-MTJ based PUF implemented at 45 nm technology achieves a lower energy consumption of 63.67 fJ/bit and a throughput of 0.27 Gb/s at a supply voltage of 1 V. The proposed PUF achieves near-ideal uniqueness of 50.2% and a high reliability of 97.3%. Moreover, the proposed PUF demonstrates strong resistance to both machine learning (ML) and side-channel attacks. An ML attack using a multilayer perceptron (MLP) yielded a prediction accuracy of under 55.27%, indicating the PUF’s resilience. The correlation power analysis (CPA) confirmed the PUF’s robustness against side-channel attacks. The designed VGSOT-MTJ based PUF shows robust performance with higher energy efficiency and is highly suitable for resource constrained Internet of Things applications.
{"title":"Energy-Efficient and Attacks Resilient PUF Design Exploiting VGSOT-MTJ","authors":"Kunal Kranti Das;Aditya Japa;Deepika Gupta;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2025.3625466","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3625466","url":null,"abstract":"Spintronic Physically Unclonable Functions (PUFs) show promise in enhancing electronic system security due to their inherent randomness, low energy consumption, fast response times, and temperature stability. This paper presents a novel PUF based on voltage-gated spin-orbit torque magnetic tunnel junctions (VGSOT-MTJs) that compares the resistance of MTJ cells utilizing intrinsic process variations to get an output response. Compared to arbiter PUFs, the proposed PUF provides a significantly larger effective challenge-response pair (CRP) space by supporting multiple independent configurations and is also reconfigurable. The Proposed VGSOT-MTJ based PUF implemented at 45 nm technology achieves a lower energy consumption of 63.67 fJ/bit and a throughput of 0.27 Gb/s at a supply voltage of 1 V. The proposed PUF achieves near-ideal uniqueness of 50.2% and a high reliability of 97.3%. Moreover, the proposed PUF demonstrates strong resistance to both machine learning (ML) and side-channel attacks. An ML attack using a multilayer perceptron (MLP) yielded a prediction accuracy of under 55.27%, indicating the PUF’s resilience. The correlation power analysis (CPA) confirmed the PUF’s robustness against side-channel attacks. The designed VGSOT-MTJ based PUF shows robust performance with higher energy efficiency and is highly suitable for resource constrained Internet of Things applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"153-161"},"PeriodicalIF":1.9,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11216370","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1109/OJNANO.2025.3620878
Christina Villeneuve-Faure;Laurent Boudou;Gilbert Teyssedre;Kremena Makasheva
The intense work on development of unconventional approaches for computing and signal processing involves efforts on design and engineering of materials with tunable dielectric properties and switchable electrical state as conduction state. This is the case of in-memory computing using emerging non-volatile memories which has successfully opened up new prospects for neuromorphic computing via the option of high volume data traffic between processor and memory units but faces materials-related challenges mostly attributed to the intrinsic and non-ideal device properties and expresses complexity in hardware implementation. In the effort to advance on the concept we describe here a way for controlled modulation at nanoscale of the dielectric response of plasma synthesized silver nanoparticles (AgNPs)-based nanocomposites and a method for mapping their dielectric permittivity via Electrostatic Force Microscopy. By embedding a 2D-network of AgNPs close to the surface of thin SiO2-layers, one can locally modulate the relative dielectric permittivity (ϵr) of the device in a large range. The presence of AgNPs in the dielectric layer leads to a nanostructuration of the relative dielectric permittivity, with lower ϵr-values above the AgNPs and higher ones in-between them, when compared to the ϵr-value of a homogeneous SiO2. A nanostructuration factor is introduced to account for this effect. The nanostructured dielectric response is related to modulation of the electric field inside these AgNPs-based nanocomposites. The results in this work generate important contributions towards the practical applicability of such AgNPs-based nanocomposites for neuromorphic computing, which is considered as an important step towards device engineering.
{"title":"Dielectric Permittivity Modulation at Nanoscale in Plasma Synthesized Silver Nanoparticles Based Nanocomposites for In-Memory Computing","authors":"Christina Villeneuve-Faure;Laurent Boudou;Gilbert Teyssedre;Kremena Makasheva","doi":"10.1109/OJNANO.2025.3620878","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3620878","url":null,"abstract":"The intense work on development of unconventional approaches for computing and signal processing involves efforts on design and engineering of materials with tunable dielectric properties and switchable electrical state as conduction state. This is the case of in-memory computing using emerging non-volatile memories which has successfully opened up new prospects for neuromorphic computing via the option of high volume data traffic between processor and memory units but faces materials-related challenges mostly attributed to the intrinsic and non-ideal device properties and expresses complexity in hardware implementation. In the effort to advance on the concept we describe here a way for controlled modulation at nanoscale of the dielectric response of plasma synthesized silver nanoparticles (AgNPs)-based nanocomposites and a method for mapping their dielectric permittivity via Electrostatic Force Microscopy. By embedding a 2D-network of AgNPs close to the surface of thin SiO<sub>2</sub>-layers, one can locally modulate the relative dielectric permittivity (ϵ<sub>r</sub>) of the device in a large range. The presence of AgNPs in the dielectric layer leads to a nanostructuration of the relative dielectric permittivity, with lower ϵ<sub>r</sub>-values above the AgNPs and higher ones in-between them, when compared to the ϵ<sub>r</sub>-value of a homogeneous SiO<sub>2</sub>. A nanostructuration factor is introduced to account for this effect. The nanostructured dielectric response is related to modulation of the electric field inside these AgNPs-based nanocomposites. The results in this work generate important contributions towards the practical applicability of such AgNPs-based nanocomposites for neuromorphic computing, which is considered as an important step towards device engineering.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"131-145"},"PeriodicalIF":1.9,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202627","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-06DOI: 10.1109/OJNANO.2025.3616955
Praween Kumar Srivastava;Atul Kumar;Ajay Kumar
This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced simulation techniques at the 7 nm technology node and a low supply voltage (V DS = 0.3 V). This work evaluates key analog and high-frequency performance metrics of the GaN-TF-FinFET. The results show a 60% increase in drain current, leading to improved transconductance and switching speed. Additionally, the subthreshold slope is reduced to 34 mV/decade, representing a 93.74% improvement compared to the C-FinFET. Furthermore, the GaN-TF-FinFET demonstrates the lowest DIBL and the highest electron mobility. Parameters such as stray capacitance, f T, f MAX, GFP, TFP, and GTFP are superior in GaN-TF-FinFET, highlighting its high-frequency performance. Our findings demonstrate significant improvements in device efficiency and signal integrity, positioning GaN-TF-FinFET as a promising device for next-generation high-frequency applications.
{"title":"Comprehensive Investigation of Truncated Fin GaN FinFET for Improved Analog/RF Performance","authors":"Praween Kumar Srivastava;Atul Kumar;Ajay Kumar","doi":"10.1109/OJNANO.2025.3616955","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3616955","url":null,"abstract":"This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced simulation techniques at the 7 nm technology node and a low supply voltage (<italic>V</i> <sub>DS</sub> = 0.3 V). This work evaluates key analog and high-frequency performance metrics of the GaN-TF-FinFET. The results show a 60% increase in drain current, leading to improved transconductance and switching speed. Additionally, the subthreshold slope is reduced to 34 mV/decade, representing a 93.74% improvement compared to the C-FinFET. Furthermore, the GaN-TF-FinFET demonstrates the lowest DIBL and the highest electron mobility. Parameters such as stray capacitance, <italic>f</i> <sub>T</sub>, <italic>f</i> <sub>MAX</sub>, GFP, TFP, and GTFP are superior in GaN-TF-FinFET, highlighting its high-frequency performance. Our findings demonstrate significant improvements in device efficiency and signal integrity, positioning GaN-TF-FinFET as a promising device for next-generation high-frequency applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"123-130"},"PeriodicalIF":1.9,"publicationDate":"2025-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11189053","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/OJNANO.2025.3613007
Gouranga Mandal;Mourina Ghosh;Pulak Mondal
In the field of neuromorphic computing, there is a growing need for high-frequency memristor emulators, especially for pattern recognition, image classification, and edge detection. A high-frequency memristor-based neural network can enhance synaptic weight updates and accelerate learning. This article presents an innovative memristor emulator circuit using CMOS-based building blocks: the Voltage Differencing Inverting Buffered Amplifier (VDIBA) and the Current Differencing Buffered Amplifier (CDBA). Our design achieves a maximum operating frequency of 60 MHz with a power consumption of only 2.25 mW. The memristor emulator is resistorless, electronically tunable, and functions in both grounded and floating configurations, as well as in incremental and decremental modes. We provide an analysis of transient behavior and voltage-current (V-I) characteristics, along with assessments of robustness and adaptability under various conditions. This memristor emulator is tailored for Adaptive Neural Networks (ANN) to mimic biological behavior and for Memristive Integrated-and-Fire (MIF) neuron circuits to replicate biological neurons, all developed using 180 nm CMOS technology. The proposed design has also been verified using ICs CA3080, LT1193, and AD844.
{"title":"Analog Building Blocks: VDIBA and CDBA Based Energy-Efficient High-Speed Memristor Emulator for Neuromorphic Applications","authors":"Gouranga Mandal;Mourina Ghosh;Pulak Mondal","doi":"10.1109/OJNANO.2025.3613007","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3613007","url":null,"abstract":"In the field of neuromorphic computing, there is a growing need for high-frequency memristor emulators, especially for pattern recognition, image classification, and edge detection. A high-frequency memristor-based neural network can enhance synaptic weight updates and accelerate learning. This article presents an innovative memristor emulator circuit using CMOS-based building blocks: the Voltage Differencing Inverting Buffered Amplifier (VDIBA) and the Current Differencing Buffered Amplifier (CDBA). Our design achieves a maximum operating frequency of 60 MHz with a power consumption of only 2.25 mW. The memristor emulator is resistorless, electronically tunable, and functions in both grounded and floating configurations, as well as in incremental and decremental modes. We provide an analysis of transient behavior and voltage-current (V-I) characteristics, along with assessments of robustness and adaptability under various conditions. This memristor emulator is tailored for Adaptive Neural Networks (ANN) to mimic biological behavior and for Memristive Integrated-and-Fire (MIF) neuron circuits to replicate biological neurons, all developed using 180 nm CMOS technology. The proposed design has also been verified using ICs CA3080, LT1193, and AD844.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"112-122"},"PeriodicalIF":1.9,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11175600","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-18DOI: 10.1109/OJNANO.2025.3611532
Vakkalakula Bharath Sreenivasulu;N Neelima;D Sudha;Prasad M;Asisa Kumar Panigrahy;Aruru Sai Kumar
In the proposed work, we have investigated the potential of the nanosheet FET design and temperature analysis at advanced nodes. Our investigation shows that the variation of gate length (LG) from 30 nm down to 3 nm, accompanied by using different gate dielectric materials, like silicon dioxide (only SiO2(3 nm)) and hafnium dioxide (HfO2) i.e., (SiO2 (2 nm) + HfO2 (1 nm)). The analysis is done at Linear (Ohmic) region to observe variable resistor for amplifiers or analog applications and saturation region to analyze the voltage controlled current sources (VCCS) applications. To comprehensively evaluate the electrical performance of the devices at the nano regime, quantum models are invoked to get accurate metrics like sub-threshold swing (SS), drain induced barrier lowering (DIBL), ON current (ION), OFF current (IOFF), and ION/IOFF ratio. Interestingly, even at the ultra-scaled dimensions of 5 nm and 3 nm, our devices exhibited remarkable electrical properties, with IOFF reaching 1013 at 5 nm and 1011 at 3 nm, while ION maintained a level of ∼106 at both dimensions when HfO2 gate stack is employed as the gate dielectric material. Our findings indicate that the integration of high-k materials becomes imperative for achieving superior device performance, particularly at reduced LG values. Moreover, we explored the scaling flexibility of the transistors by investigating additional parameters such as transconductance (gm) and transconductance generation factor (TGF). The impact of scaling of nanosheet FET towards temperature is also analyzed. The analysis shows that ultra scaled nanosheet FET is capable of driving amplifiers and VCCS applications with HfO2 gate stack compared to SiO2.
{"title":"Gate Stack Analysis of Junctionless Multi-Bridge-Channel FETs for Sub-3 nm Chips","authors":"Vakkalakula Bharath Sreenivasulu;N Neelima;D Sudha;Prasad M;Asisa Kumar Panigrahy;Aruru Sai Kumar","doi":"10.1109/OJNANO.2025.3611532","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3611532","url":null,"abstract":"In the proposed work, we have investigated the potential of the nanosheet FET design and temperature analysis at advanced nodes. Our investigation shows that the variation of gate length (<italic>L</i><sub>G</sub>) from 30 nm down to 3 nm, accompanied by using different gate dielectric materials, like silicon dioxide (only SiO<sub>2</sub>(3 nm)) and hafnium dioxide (HfO<sub>2</sub>) i.e., (SiO<sub>2</sub> (2 nm) + HfO<sub>2</sub> (1 nm)). The analysis is done at Linear (Ohmic) region to observe variable resistor for amplifiers or analog applications and saturation region to analyze the voltage controlled current sources (VCCS) applications. To comprehensively evaluate the electrical performance of the devices at the nano regime, quantum models are invoked to get accurate metrics like sub-threshold swing (SS), drain induced barrier lowering (DIBL), ON current (<italic>I</i><sub>ON</sub>), OFF current (<italic>I</i><sub>OFF</sub>), and <italic>I</i><sub>ON</sub><italic>/I</i><sub>OFF</sub> ratio. Interestingly, even at the ultra-scaled dimensions of 5 nm and 3 nm, our devices exhibited remarkable electrical properties, with <italic>I</i><sub>OFF</sub> reaching 10<sup>13</sup> at 5 nm and 10<sup>11</sup> at 3 nm, while <italic>I</i><sub>ON</sub> maintained a level of ∼10<sup>6</sup> at both dimensions when HfO<sub>2</sub> gate stack is employed as the gate dielectric material. Our findings indicate that the integration of high-<italic>k</i> materials becomes imperative for achieving superior device performance, particularly at reduced <italic>L</i><sub>G</sub> values. Moreover, we explored the scaling flexibility of the transistors by investigating additional parameters such as transconductance (g<sub>m</sub>) and transconductance generation factor (TGF). The impact of scaling of nanosheet FET towards temperature is also analyzed. The analysis shows that ultra scaled nanosheet FET is capable of driving amplifiers and VCCS applications with HfO<sub>2</sub> gate stack compared to SiO<sub>2</sub>.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"102-111"},"PeriodicalIF":1.9,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11171618","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-12DOI: 10.1109/OJNANO.2025.3598219
Adelcio M. de Souza;Daniel R. Celino;Regiane Ragi;Murilo A. Romero
This paper describes device models for the current-voltage (I–V) and capacitance-voltage (C–V) characteristics of ballistic nanotransistors based on two-dimensional (2D) materials. The proposed methodology introduces a novel, fully analytical, and explicit approach grounded in fundamental physical principles. This approach enables seamless integration into circuit simulators and provides clear insight into device operation. In contrast to the drift-diffusion models commonly found in the literature, this approach accurately describes the ballistic transport regime observed in state-of-the-art 2D nanotransistors. The proposed model was validated against both experimental and ab initio numerical simulations from the literature for devices based on molybdenum disulfide (MoS2) and indium selenide (InSe). The results show excellent agreement with the reference datasets, confirming the model’s accuracy and its suitability for designing advanced nanoelectronic devices and circuits.
{"title":"Analytical Model for Ballistic 2D Nanotransistors","authors":"Adelcio M. de Souza;Daniel R. Celino;Regiane Ragi;Murilo A. Romero","doi":"10.1109/OJNANO.2025.3598219","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3598219","url":null,"abstract":"This paper describes device models for the current-voltage (I–V) and capacitance-voltage (C–V) characteristics of ballistic nanotransistors based on two-dimensional (2D) materials. The proposed methodology introduces a novel, fully analytical, and explicit approach grounded in fundamental physical principles. This approach enables seamless integration into circuit simulators and provides clear insight into device operation. In contrast to the drift-diffusion models commonly found in the literature, this approach accurately describes the ballistic transport regime observed in state-of-the-art 2D nanotransistors. The proposed model was validated against both experimental and <italic>ab initio</i> numerical simulations from the literature for devices based on molybdenum disulfide (MoS<sub>2</sub>) and indium selenide (InSe). The results show excellent agreement with the reference datasets, confirming the model’s accuracy and its suitability for designing advanced nanoelectronic devices and circuits.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"91-101"},"PeriodicalIF":1.9,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11123147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144926864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-20DOI: 10.1109/OJNANO.2025.3553692
Sebastiano De Stefano;Alfredo Spuri;Raffaele Barbella;Ofelia Durante;Adolfo Mazzotti;Andrea Sessa;Angelo Di Bernardo;Antonio Di Bartolomeo
The miniaturization of electronic components remains a critical focus in electronics, particularly in transistor design, with research exploring new solutions such as the use of two-dimensional materials in Schottky Barrier Field Effect Transistors (SB-FETs). Following the trend, this study presents two-dimensional MoS2 SB-FETs, configured with back-gate and van der Pauw contacts, and analyses their electrical behaviour through output and transfer characteristics. The consequences that local inhomogeneities due to fabrication processes have on Schottky barriers height and electrical behaviour of the device are underlined. A hierarchy of the Schottky barrier heights at the contacts is established, and a band model is developed to elucidate the underlying conduction mechanisms. This model combines thermionic emission and tunnelling to explain the operation of the studied MoS2 devices and can be broadly applied to other SB-FETs.
{"title":"Multilayer MoS2 Schottky Barrier Field Effect Transistor","authors":"Sebastiano De Stefano;Alfredo Spuri;Raffaele Barbella;Ofelia Durante;Adolfo Mazzotti;Andrea Sessa;Angelo Di Bernardo;Antonio Di Bartolomeo","doi":"10.1109/OJNANO.2025.3553692","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3553692","url":null,"abstract":"The miniaturization of electronic components remains a critical focus in electronics, particularly in transistor design, with research exploring new solutions such as the use of two-dimensional materials in Schottky Barrier Field Effect Transistors (SB-FETs). Following the trend, this study presents two-dimensional MoS<sub>2</sub> SB-FETs, configured with back-gate and van der Pauw contacts, and analyses their electrical behaviour through output and transfer characteristics. The consequences that local inhomogeneities due to fabrication processes have on Schottky barriers height and electrical behaviour of the device are underlined. A hierarchy of the Schottky barrier heights at the contacts is established, and a band model is developed to elucidate the underlying conduction mechanisms. This model combines thermionic emission and tunnelling to explain the operation of the studied MoS<sub>2</sub> devices and can be broadly applied to other SB-FETs.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"51-57"},"PeriodicalIF":1.8,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10935823","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143817787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Magnetic skyrmion has great potential as information carriers in next-generation logic, neuromorphic computing, and memory devices because of its topological stability, incredibly compact size, and low current consumption required to operate it. In this work, the computational demonstration of a skyrmion controlled by a voltage controlled magnetic anisotropy (VCMA) gradient on a trapezoidal nanotrack is studied for the application of racetrack memory. The trapezoidal nanotrack aids in guiding the skyrmion's motion under the anisotropy gradient by leveraging the edge repulsion force. By utilizing a defect, the proposed device ensures a continuous flow of binary bits ‘0’ and ‘1’ without any accumulation on the racetrack. The higher angle (θhigh) and higher anisotropy gradient (ΔKu-high) of the trapezoidal nanotrack accelerates the skyrmion owing to higher edge repulsion force and energy gradient force. The maximum speed of 1.27 m/s was achieved by the skyrmion, and the minimum time taken for the skyrmion to reach the detector from the nucleation point was 2.16 ns. The energy used to maintain the electric field is 4.58fJ per bit operation. This presents a novel approach to manipulate skyrmions under anisotropy gradient (ΔKu) on the trapezoidal nanotrack, paving the way for the development of improved skyrmion racetrack memory (sk-RM).
{"title":"VCMA Gradient-Driven Skyrmion on a Trapezoidal Nanotrack for Racetrack Memory Application","authors":"Bikash Sharma;Pema Rinzing Bhutia;Ravish Kumar Raj;Bibek Chettri;Brajesh Kumar Kaushik;Sonal Shreya","doi":"10.1109/OJNANO.2025.3550173","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3550173","url":null,"abstract":"Magnetic skyrmion has great potential as information carriers in next-generation logic, neuromorphic computing, and memory devices because of its topological stability, incredibly compact size, and low current consumption required to operate it. In this work, the computational demonstration of a skyrmion controlled by a voltage controlled magnetic anisotropy (VCMA) gradient on a trapezoidal nanotrack is studied for the application of racetrack memory. The trapezoidal nanotrack aids in guiding the skyrmion's motion under the anisotropy gradient by leveraging the edge repulsion force. By utilizing a defect, the proposed device ensures a continuous flow of binary bits ‘0’ and ‘1’ without any accumulation on the racetrack. The higher angle (<italic>θ<sub>high</sub></i>) and higher anisotropy gradient (<italic>ΔK<sub>u</sub><sub>-high</sub></i>) of the trapezoidal nanotrack accelerates the skyrmion owing to higher edge repulsion force and energy gradient force. The maximum speed of 1.27 m/s was achieved by the skyrmion, and the minimum time taken for the skyrmion to reach the detector from the nucleation point was 2.16 ns. The energy used to maintain the electric field is 4.58<italic>fJ</i> per bit operation. This presents a novel approach to manipulate skyrmions under anisotropy gradient (<italic>ΔK<sub>u</sub></i>) on the trapezoidal nanotrack, paving the way for the development of improved skyrmion racetrack memory (sk-RM).","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"44-50"},"PeriodicalIF":1.8,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10934757","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The treatment of diffuse, high-grade gliomas, the most aggressive form of primary brain tumors, poses significant therapeutic challenges. Recurrent high-grade gliomas are associated with a median overall survival of less than one year; therefore, new therapeutic strategies must be sought. In this work we propose the synthesis of novel superparamagnetic iron oxide (SPIO), following thermal decomposition in hexadecanediol, oleic acid and oleylamine, then assembled in micelles for brain tumor treatment. The resulting SPIO-micelles are preliminary characterized by an average diameter of 26 nm and a saturation magnetization of 56 emu/g, thus holding great potential for magnetic hyperthermia treatment (MHT). In this work a multiphysics nonlinear model for ad-hoc MHT planning based on patient-specific geometries has been developed. The model accounts for the convection-enhanced delivery (CED) computing the SPIO-micelles concentration patterns, coupling the mass transport to the RF problem, assuming a frequency- and spatial-dependent magnetic susceptibility. Given that the RF field is produced by a pair of Helmholtz coils, while considering the temperature-dependent variation of electromagnetic and thermal properties of normal and neoplastic brain tissue, the efficiency of the MHT was evaluated for different tumor geometries. The findings highlight that using realistic tumor geometries strongly affect treatment parameters (e.g., ∼32% and 1.2°C differences in the magnetic field and in the max. average tumor temperature). The radio-sensitization and equivalent dose distribution are studied, stressing the adjuvant potential of the novel SPIO-micelles formulation. The results also highlight that the proposed model could ensure precise hyperthermia treatment using RF MHT, confirming its potential for personalized cancer therapy. This research provides an important foundation for exploring the therapeutic possibilities of this novel approach, facilitating the development of tailored treatments for patients.
{"title":"Superparamagnetic Micelles for the Magnetic Hyperthermia Against Glioblastoma: A Multiphysics Approach for Personalized Treatment Planning","authors":"Matteo Bruno Lodi;Eleonora Matilde Angela Corda;Wirat Assawapanumat;Gian Luca Chabert;Francesco Desogus;Luca Saba;Andrea Perra;Norased Nasongkla;Alessandro Fanti;Giuseppe Mazzarella","doi":"10.1109/OJNANO.2025.3568291","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3568291","url":null,"abstract":"The treatment of diffuse, high-grade gliomas, the most aggressive form of primary brain tumors, poses significant therapeutic challenges. Recurrent high-grade gliomas are associated with a median overall survival of less than one year; therefore, new therapeutic strategies must be sought. In this work we propose the synthesis of novel superparamagnetic iron oxide (SPIO), following thermal decomposition in hexadecanediol, oleic acid and oleylamine, then assembled in micelles for brain tumor treatment. The resulting SPIO-micelles are preliminary characterized by an average diameter of 26 nm and a saturation magnetization of 56 emu/g, thus holding great potential for magnetic hyperthermia treatment (MHT). In this work a multiphysics nonlinear model for ad-hoc MHT planning based on patient-specific geometries has been developed. The model accounts for the convection-enhanced delivery (CED) computing the SPIO-micelles concentration patterns, coupling the mass transport to the RF problem, assuming a frequency- and spatial-dependent magnetic susceptibility. Given that the RF field is produced by a pair of Helmholtz coils, while considering the temperature-dependent variation of electromagnetic and thermal properties of normal and neoplastic brain tissue, the efficiency of the MHT was evaluated for different tumor geometries. The findings highlight that using realistic tumor geometries strongly affect treatment parameters (e.g., ∼32% and 1.2°C differences in the magnetic field and in the max. average tumor temperature). The radio-sensitization and equivalent dose distribution are studied, stressing the adjuvant potential of the novel SPIO-micelles formulation. The results also highlight that the proposed model could ensure precise hyperthermia treatment using RF MHT, confirming its potential for personalized cancer therapy. This research provides an important foundation for exploring the therapeutic possibilities of this novel approach, facilitating the development of tailored treatments for patients.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"66-79"},"PeriodicalIF":1.8,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10993440","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144255701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-08DOI: 10.1109/OJNANO.2025.3568172
Srinivasa Rao Karumuri;G Sai Lakshmi;Girija Sravani Kondavitee
Diabetes is a metabolic disorder that inhibits the body’s capacity to produce an adequate amount of blood glucose. Indications of diabetes include heightened appetite, frequent urination, and increased thirst. The objective of this research was to employ an electro-osmotic pressure sensor to monitor changes in glucose concentration levels. The main aim was on developing micro bridges that could be integrated into the electro-osmotic pressure sensor. Utilizing a Finite Element Method (FEM) tool, the study examined the mechanical properties and response of three micro bridges, considering factors such as non-linearity and sensitivity conditions. Better suitable is integrated into osmotic pressure sensor by obtaining the response time is 18mins.
{"title":"Integration of Micro/Nano Pressure Sensor for Diabetes Patients Applications","authors":"Srinivasa Rao Karumuri;G Sai Lakshmi;Girija Sravani Kondavitee","doi":"10.1109/OJNANO.2025.3568172","DOIUrl":"https://doi.org/10.1109/OJNANO.2025.3568172","url":null,"abstract":"Diabetes is a metabolic disorder that inhibits the body’s capacity to produce an adequate amount of blood glucose. Indications of diabetes include heightened appetite, frequent urination, and increased thirst. The objective of this research was to employ an electro-osmotic pressure sensor to monitor changes in glucose concentration levels. The main aim was on developing micro bridges that could be integrated into the electro-osmotic pressure sensor. Utilizing a Finite Element Method (FEM) tool, the study examined the mechanical properties and response of three micro bridges, considering factors such as non-linearity and sensitivity conditions. Better suitable is integrated into osmotic pressure sensor by obtaining the response time is 18mins.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"6 ","pages":"80-90"},"PeriodicalIF":1.8,"publicationDate":"2025-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10993415","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144623934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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