Pub Date : 2022-11-23DOI: 10.1109/OJNANO.2022.3224061
DINESH JUNJARIYA;JAI NARAYAN TRIPATHI
Power delivery networks are responsible for supplying clean power to the integrated circuits. Power supply noise plays a critical role in determining the performance of high-speed very large scale integration circuits and systems. In order to maintain power integrity in high-speed systems, decoupling capacitors are used to maintain low impedance of the PDN to eventually minimize power supply noise. However, the discrete optimization problem of selecting decoupling capacitors becomes computationally challenging in the systems having stringent power integrity (PI) requirements. In this work, a novel approach using the Social-Learning Particle Swarm Optimization (SLPSO) technique along with Adaptive Region Search (ARS) is used to tackle the Large-Scale Optimization Problem (LSOP) of decoupling capacitor placement. Region Search (RS) is used to guide particles, followed by ARS to dynamical search for the local best positions and for particles to move faster across the search space while maintaining the diversity of the population. To demonstrate the proposed approach, three practical case studies are presented. The obtained results are compared with current state-of-the-art approaches. The proposed approach drastically reduces computation time and is consistent with better results than other approaches. This consistency of improvement in CPU time in the results of all the examples validates the proposed approach.
{"title":"Large-Scale Optimization of Decoupling Capacitors Using Adaptive Region Based Encoding Scheme in Particle Swarm Optimization","authors":"DINESH JUNJARIYA;JAI NARAYAN TRIPATHI","doi":"10.1109/OJNANO.2022.3224061","DOIUrl":"10.1109/OJNANO.2022.3224061","url":null,"abstract":"Power delivery networks are responsible for supplying clean power to the integrated circuits. Power supply noise plays a critical role in determining the performance of high-speed very large scale integration circuits and systems. In order to maintain power integrity in high-speed systems, decoupling capacitors are used to maintain low impedance of the PDN to eventually minimize power supply noise. However, the discrete optimization problem of selecting decoupling capacitors becomes computationally challenging in the systems having stringent power integrity (PI) requirements. In this work, a novel approach using the Social-Learning Particle Swarm Optimization (SLPSO) technique along with Adaptive Region Search (ARS) is used to tackle the Large-Scale Optimization Problem (LSOP) of decoupling capacitor placement. Region Search (RS) is used to guide particles, followed by ARS to dynamical search for the local best positions and for particles to move faster across the search space while maintaining the diversity of the population. To demonstrate the proposed approach, three practical case studies are presented. The obtained results are compared with current state-of-the-art approaches. The proposed approach drastically reduces computation time and is consistent with better results than other approaches. This consistency of improvement in CPU time in the results of all the examples validates the proposed approach.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"210-219"},"PeriodicalIF":1.7,"publicationDate":"2022-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9961848","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-23DOI: 10.1109/OJNANO.2022.3223897
Kuniko Urashima
Since the beginning of the 20th century, plasma technology has been used in a variety of fields. In the 1980s, R&D related to arc plasma welding and waste disposal, as well as etching, painting, and gas removal equipment that used plasma technology in the processes associated with semiconductor manufacturing. In the 1990s, research on removing air pollutants using atmospheric pressure plasma technology became active. In the 2000s, research on the application of thermal/non-thermal plasma technology to air pollution, waste and water treatment became active. Electrostatic precipitators (ESP) can remove a wide variety of particles such as soot from thermal power plants, coal, and oil mist, resin powder, glass powder, dust, and iron powder generated from incinerators, boilers, and various manufacturing plants. Waste treatment aims to reduce the volume of garbage, recycle incinerated materials, and utilize waste heat from incineration, and plasma technology is used in each process. Various techniques have been used for making purified water. Water quality requirements vary according to the objective. Plasma technology uses an electrical field to encourage seed germination and growth. Due to the spread of such applied technology, plasma technology has attracted attention again in recent years.
{"title":"Review of Plasma Technologies for Contribution of Environmental Purification","authors":"Kuniko Urashima","doi":"10.1109/OJNANO.2022.3223897","DOIUrl":"10.1109/OJNANO.2022.3223897","url":null,"abstract":"Since the beginning of the 20th century, plasma technology has been used in a variety of fields. In the 1980s, R&D related to arc plasma welding and waste disposal, as well as etching, painting, and gas removal equipment that used plasma technology in the processes associated with semiconductor manufacturing. In the 1990s, research on removing air pollutants using atmospheric pressure plasma technology became active. In the 2000s, research on the application of thermal/non-thermal plasma technology to air pollution, waste and water treatment became active. Electrostatic precipitators (ESP) can remove a wide variety of particles such as soot from thermal power plants, coal, and oil mist, resin powder, glass powder, dust, and iron powder generated from incinerators, boilers, and various manufacturing plants. Waste treatment aims to reduce the volume of garbage, recycle incinerated materials, and utilize waste heat from incineration, and plasma technology is used in each process. Various techniques have been used for making purified water. Water quality requirements vary according to the objective. Plasma technology uses an electrical field to encourage seed germination and growth. Due to the spread of such applied technology, plasma technology has attracted attention again in recent years.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"159-165"},"PeriodicalIF":1.7,"publicationDate":"2022-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9961850","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-21DOI: 10.1109/OJNANO.2022.3223712
Ka Wai Kong;Keer Wang;Alice Yeuk Lan Leung;Hongyu Zhang;Jiao Suo;Meng Chen;Guanglie Zhang;Fei Fei;Jiangang Shen;Wen Jung Li
We report a novel flexible capacitive pressure-pulse sensor array developed by integrating droplet-dispensed graphene oxide (GO) sensing elements and flexible electronics. The utilization of droplet-dispensing technology enables the fabrication multiple capacitive sensing elements rapidly while producing sensitive pressure sensors with excellent repeatability. The dispensed droplet volume (GO aqueous dispersion) ranged from around 33.5 to 65.4 pL with diameter ranging from 40 to 50 μm. The size (i.e., footprint and dielectric material thickness) of a sensing element can be controlled by the total GO dispersed per droplet. The fabrication process and preliminary characterization of these GO capacitive sensors are discussed in this paper. Thus far, we have shown that these sensors have a sensitivity of ∼10 −3 kPa −1 , with the relative permittivity of the dispensed GO being ∼6 (measured at a frequency of 600 kHz). We have also demonstrated that the printed sensing elements can be used for human wrist pulse sensing. Hence the technology described in this paper could potentially be used in wearable electronics for healthcare applications.
{"title":"Droplet-Dispensed Graphene Oxide as Capacitive Sensing Elements for Flexible Pressure-Pulse Sensing Array","authors":"Ka Wai Kong;Keer Wang;Alice Yeuk Lan Leung;Hongyu Zhang;Jiao Suo;Meng Chen;Guanglie Zhang;Fei Fei;Jiangang Shen;Wen Jung Li","doi":"10.1109/OJNANO.2022.3223712","DOIUrl":"https://doi.org/10.1109/OJNANO.2022.3223712","url":null,"abstract":"We report a novel flexible capacitive pressure-pulse sensor array developed by integrating droplet-dispensed graphene oxide (GO) sensing elements and flexible electronics. The utilization of droplet-dispensing technology enables the fabrication multiple capacitive sensing elements rapidly while producing sensitive pressure sensors with excellent repeatability. The dispensed droplet volume (GO aqueous dispersion) ranged from around 33.5 to 65.4 pL with diameter ranging from 40 to 50 μm. The size (i.e., footprint and dielectric material thickness) of a sensing element can be controlled by the total GO dispersed per droplet. The fabrication process and preliminary characterization of these GO capacitive sensors are discussed in this paper. Thus far, we have shown that these sensors have a sensitivity of ∼10\u0000<sup>−3</sup>\u0000 kPa\u0000<sup>−1</sup>\u0000, with the relative permittivity of the dispensed GO being ∼6 (measured at a frequency of 600 kHz). We have also demonstrated that the printed sensing elements can be used for human wrist pulse sensing. Hence the technology described in this paper could potentially be used in wearable electronics for healthcare applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"4 ","pages":"47-54"},"PeriodicalIF":1.7,"publicationDate":"2022-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782713/10007543/09956867.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3491208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-18DOI: 10.1109/OJNANO.2022.3223016
Sriharsha Sudhindra;Lokesh Ramesh;Alexander A. Balandin
We provide a summary of the fundamentals of thermal management, outline the state-of-the-art in the field of thermal interface materials, and describe recent developments in graphene-based non-curing and curing composites used for thermal management. The discovery of unique heat conduction properties of graphene and few-layer graphene motivated research activities worldwide focused on creating efficient graphene-based thermal interface materials. While the initial focus of these studies was on obtaining the maximum possible thermal conductivity of the composites, recently the attention has shifted to practical problems of minimizing the thermal contact resistance at interfaces, optimizing the size distribution of graphene as filler, and addressing the issues of scalability, stability, and production costs at commercial scales. We conclude the review with a general outlook for commercial applications of graphene in the thermal management of electronics.
{"title":"Graphene Thermal Interface Materials – State-of-the-Art and Application Prospects","authors":"Sriharsha Sudhindra;Lokesh Ramesh;Alexander A. Balandin","doi":"10.1109/OJNANO.2022.3223016","DOIUrl":"10.1109/OJNANO.2022.3223016","url":null,"abstract":"We provide a summary of the fundamentals of thermal management, outline the state-of-the-art in the field of thermal interface materials, and describe recent developments in graphene-based non-curing and curing composites used for thermal management. The discovery of unique heat conduction properties of graphene and few-layer graphene motivated research activities worldwide focused on creating efficient graphene-based thermal interface materials. While the initial focus of these studies was on obtaining the maximum possible thermal conductivity of the composites, recently the attention has shifted to practical problems of minimizing the thermal contact resistance at interfaces, optimizing the size distribution of graphene as filler, and addressing the issues of scalability, stability, and production costs at commercial scales. We conclude the review with a general outlook for commercial applications of graphene in the thermal management of electronics.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"169-181"},"PeriodicalIF":1.7,"publicationDate":"2022-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9954624","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-18DOI: 10.1109/OJNANO.2022.3223151
M. Sankush Krishna;Sangeeta Singh;Brajesh Kumar Kaushik
The present work explores the theoretical analysis of copper passivated MgONRs (Cu-MgO-Cu) for possible nanointerconnect applications. The first principles calculations based on density functional theory (DFT) and non-equilibrium Green's function are employed for theoretical investigation. Pristine MgONRs (H-MgO-H) and Cu-MgO-Cu are both thermodynamically stable and are metallic with H-MgO-H being relatively more stable. Further, the I-V characteristics evaluated using the two-probe method reveal the ohmic behavior of Cu-MgO-Cu. The Cu-MgO-Cu device is further investigated for the nanointerconnect applications. The computed nanoscale parasitic components such as quantum resistance ( $R_{Q}$ ), quantum capacitance ( $C_{Q}$ ), and kinetic inductance ( $L_{K}$ ) are computed to be 6.46 k $Omega$ , 5.57 fF/ $mutext{m}$ , and 58.17 nF/ $mu$ m, respectively. Furthermore, the delay and power delay product (PDP) of the nanointerconnect are explored which are important attributes of nanointerconnects. The findings suggest the Cu-MgO-Cu nanoribbons with low parasitic parameters can potentially be employed for nanointerconnect applications.
本工作探讨了铜钝化mgonr (Cu-MgO-Cu)的理论分析，以实现可能的纳米互连应用。基于密度泛函理论和非平衡格林函数的第一性原理计算进行了理论研究。原始mgonr (H-MgO-H)和Cu-MgO-Cu都是热力学稳定的金属，H-MgO-H相对更稳定。此外，使用双探针方法评估的I-V特性揭示了Cu-MgO-Cu的欧姆行为。进一步研究了Cu-MgO-Cu器件在纳米互连中的应用。计算得到的纳米级寄生分量如量子电阻($R_{Q}$)、量子电容($C_{Q}$)和动态电感($L_{K}$)分别为6.46 k $Omega$、5.57 fF/ $mutext{m}$和58.17 nF/ $mu$ m。此外，研究了纳米互连的延迟和功率延迟积(PDP)这两个重要属性。研究结果表明，具有低寄生参数的Cu-MgO-Cu纳米带可用于纳米互连应用。
{"title":"Copper Passivated Zigzag MgO Nanoribbons for Potential Nanointerconnect Applications","authors":"M. Sankush Krishna;Sangeeta Singh;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2022.3223151","DOIUrl":"10.1109/OJNANO.2022.3223151","url":null,"abstract":"The present work explores the theoretical analysis of copper passivated MgONRs (Cu-MgO-Cu) for possible nanointerconnect applications. The first principles calculations based on density functional theory (DFT) and non-equilibrium Green's function are employed for theoretical investigation. Pristine MgONRs (H-MgO-H) and Cu-MgO-Cu are both thermodynamically stable and are metallic with H-MgO-H being relatively more stable. Further, the I-V characteristics evaluated using the two-probe method reveal the ohmic behavior of Cu-MgO-Cu. The Cu-MgO-Cu device is further investigated for the nanointerconnect applications. The computed nanoscale parasitic components such as quantum resistance (\u0000<inline-formula><tex-math>$R_{Q}$</tex-math></inline-formula>\u0000), quantum capacitance (\u0000<inline-formula><tex-math>$C_{Q}$</tex-math></inline-formula>\u0000), and kinetic inductance (\u0000<inline-formula><tex-math>$L_{K}$</tex-math></inline-formula>\u0000) are computed to be 6.46 k\u0000<inline-formula><tex-math>$Omega$</tex-math></inline-formula>\u0000, 5.57 fF/\u0000<inline-formula><tex-math>$mutext{m}$</tex-math></inline-formula>\u0000, and 58.17 nF/\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m, respectively. Furthermore, the delay and power delay product (PDP) of the nanointerconnect are explored which are important attributes of nanointerconnects. The findings suggest the Cu-MgO-Cu nanoribbons with low parasitic parameters can potentially be employed for nanointerconnect applications.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"220-226"},"PeriodicalIF":1.7,"publicationDate":"2022-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9954618","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report on optical and electrical properties of amorphous In-Ga-Mg-O (a-IGMO) films and characteristics of a-IGMO channel thin-film transistors which went through the reductive post-annealing process. Optical band-gap energies of a-IGMO films were larger than that of amorphous In-Ga-Zn-O (a-IGZO) films. Carrier density and Hall mobility of a-IGMO films with the reductive post-annealing were almost the same degree as those of a-IGZO films. Although the reductive annealing with the SiN x underlayer makes an a-IGZO film degenerate semiconductor and its TFT inoperative, a-IGMO TFTs successfully operated after this reductive process. Break-junction tunnelling spectroscopy which was applicable not to a-IGMO but to a-IGZO with the reductive process showed a noticeable density of state character in the vicinity of the Fermi level for a-IGZO, which is consistent with its property.
{"title":"Amorphous In-Ga-Mg-O Thin Films Formed by RF Magnetron Sputtering: Optical, Electrical Properties and Thin-Film-Transistor Characteristics","authors":"Hisato Yabuta;Naho Itagaki;Toshikazu Ekino;Yuzo Shigesato","doi":"10.1109/OJNANO.2022.3222850","DOIUrl":"10.1109/OJNANO.2022.3222850","url":null,"abstract":"We report on optical and electrical properties of amorphous In-Ga-Mg-O (a-IGMO) films and characteristics of a-IGMO channel thin-film transistors which went through the reductive post-annealing process. Optical band-gap energies of a-IGMO films were larger than that of amorphous In-Ga-Zn-O (a-IGZO) films. Carrier density and Hall mobility of a-IGMO films with the reductive post-annealing were almost the same degree as those of a-IGZO films. Although the reductive annealing with the SiN\u0000<sub>x</sub>\u0000 underlayer makes an a-IGZO film degenerate semiconductor and its TFT inoperative, a-IGMO TFTs successfully operated after this reductive process. Break-junction tunnelling spectroscopy which was applicable not to a-IGMO but to a-IGZO with the reductive process showed a noticeable density of state character in the vicinity of the Fermi level for a-IGZO, which is consistent with its property.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"149-152"},"PeriodicalIF":1.7,"publicationDate":"2022-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9954130","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The past decade has witnessed a tremendous reduction in the feature size from the deep-submicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Indefinite Admittance Matrix, a reduced two-port network is developed for a multiple-input circuit, considering the presence of the supply/bulk/ground sources. The closed-form expressions of the PSIJ have been evaluated for a single and N-stages CMOS inverter chain. The expression is also valid for the PSIJ analysis at any intermediate stage of the N-stage chain. For validation purpose, the circuits are designed in a standard 28 nm CMOS technology with V $_text{DD}$ of 1 V. The analytical results are compared with the simulation and the experiments. The maximum mean percentage error for EDA simulation and experimentally measured results are 2.4% and 13%, respectively. The proposed analysis is compared with some of the existing PSIJ modelling techniques and shows a significant improvement in speed-up factor and error percentage.
{"title":"Indefinite Admittance Matrix Based Modelling of PSIJ in Nano-Scale CMOS I/O Drivers","authors":"Vijender Kumar Sharma;Jai Narayan Tripathi;Hitesh Shrimali","doi":"10.1109/OJNANO.2022.3221838","DOIUrl":"10.1109/OJNANO.2022.3221838","url":null,"abstract":"The past decade has witnessed a tremendous reduction in the feature size from the deep-submicron to the advanced nano-scale CMOS devices. In nanoscale devices based high-speed systems, the budgeting of jitter due to supply fluctuations is one of the major performance bottlenecks while designing integrated circuits (ICs). In this paper, an accurate and efficient method to analyse power supply induced jitter (PSIJ) in CMOS N-stage inverters is developed using the estimation-by-inspection method. Based on the Indefinite Admittance Matrix, a reduced two-port network is developed for a multiple-input circuit, considering the presence of the supply/bulk/ground sources. The closed-form expressions of the PSIJ have been evaluated for a single and N-stages CMOS inverter chain. The expression is also valid for the PSIJ analysis at any intermediate stage of the N-stage chain. For validation purpose, the circuits are designed in a standard 28 nm CMOS technology with V\u0000<inline-formula><tex-math>$_text{DD}$</tex-math></inline-formula>\u0000 of 1 V. The analytical results are compared with the simulation and the experiments. The maximum mean percentage error for EDA simulation and experimentally measured results are 2.4% and 13%, respectively. The proposed analysis is compared with some of the existing PSIJ modelling techniques and shows a significant improvement in speed-up factor and error percentage.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"199-209"},"PeriodicalIF":1.7,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9947063","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62889006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study addresses the first feasible, and comprehensive approach to demonstrate a compact resistance-inductance-capacitance-conductance ( RLCG ) model for a multi-walled carbon nanotube bundle (MWB) and multilayered graphene nanoribbon (MLGNR) based tapered through silicon via ( T -TSV) along with the different shaped bumps. The physical structures of bumps accurately considered the effect of the high frequency resistive impact and the inter-metal dielectric (IMD) layer. A mathematical framework has been designed for the parasitics of the cylindrical, barrel, hourglass and the tapered bump structures. The bump and via parasitics have been computed by utilizing the current continuity expression, partial inductance method, splitting infinitesimally thin slices of bump and triangular arrangement of tube assemblage. In order to validate the proposed model, the EM simulation is performed and compared against the analytical results. A remarkable consistency of the analytical and EM simulation-based results supports the proposed model accuracy. Furthermore, when compared to the MWB based structures, the MLGNR -based tapered TSV shows a substantial improvement in power loss and crosstalk. Furthermore, regardless of via height, the TSV with tapered bump structure reduces the overall crosstalk induced delay by 33.22%, 28.90%, and 21.61%, respectively, when compared to the barrel, cylindrical and the hourglass structure.
{"title":"Performance Analysis of Bump in Tapered TSV: Impact on Crosstalk and Power Loss","authors":"Shivangi Chandrakar;Deepika Gupta;Manoj Kumar Majumder;Brajesh Kumar Kaushik","doi":"10.1109/OJNANO.2022.3221815","DOIUrl":"10.1109/OJNANO.2022.3221815","url":null,"abstract":"This study addresses the first feasible, and comprehensive approach to demonstrate a compact resistance-inductance-capacitance-conductance (\u0000<italic>RLCG</i>\u0000) model for a multi-walled carbon nanotube bundle (MWB) and multilayered graphene nanoribbon (MLGNR) based tapered through silicon via (\u0000<italic>T</i>\u0000-TSV) along with the different shaped bumps. The physical structures of bumps accurately considered the effect of the high frequency resistive impact and the inter-metal dielectric (IMD) layer. A mathematical framework has been designed for the parasitics of the cylindrical, barrel, hourglass and the tapered bump structures. The bump and via parasitics have been computed by utilizing the current continuity expression, partial inductance method, splitting infinitesimally thin slices of bump and triangular arrangement of tube assemblage. In order to validate the proposed model, the EM simulation is performed and compared against the analytical results. A remarkable consistency of the analytical and EM simulation-based results supports the proposed model accuracy. Furthermore, when compared to the MWB based structures, the MLGNR -based tapered TSV shows a substantial improvement in power loss and crosstalk. Furthermore, regardless of via height, the TSV with tapered bump structure reduces the overall crosstalk induced delay by 33.22%, 28.90%, and 21.61%, respectively, when compared to the barrel, cylindrical and the hourglass structure.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"227-235"},"PeriodicalIF":1.7,"publicationDate":"2022-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9947291","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We fabricated nanocrystalline Ge films using radio-frequency (RF) magnetron plasma sputtering deposition under a high Ar-gas pressure. The Ge nanograins changed from amorphous to crystalline when the distance between the Ge sputtering target and the substrate was decreased to 5 mm and the RF input power was 11.8 W/cm 2 (60 W), where the deposition rate was as high as 660 nm/min. In addition, the size of the nanocrystalline grains increased from 100 to 307 nm when the RF input power for plasma production was increased from 11.8 W/cm 2 (60 W) to 17.7 W/cm 2 (90 W). In the developed narrow-gap plasma process at sub-Torr pressures, nanocrystalline Ge films were successfully fabricated on Cu substrates at low temperatures, without the substrate being heated. However, when annealing was conducted under an N 2 atmosphere, which is the conventional method to induce solid-phase crystallization, the amorphous Ge layer on a Cu substrate changed to a Cu 3 Ge crystal layer through interdiffusion of Ge and Cu atoms at 400–500 °C.
{"title":"Low-Temperature and High-Speed Fabrication of Nanocrystalline Ge Films on Cu Substrates Using Sub-Torr-Pressure Plasma Sputtering","authors":"Giichiro Uchida;Kenta Nagai;Ayaka Wakana;Yumiko Ikebe","doi":"10.1109/OJNANO.2022.3221462","DOIUrl":"10.1109/OJNANO.2022.3221462","url":null,"abstract":"We fabricated nanocrystalline Ge films using radio-frequency (RF) magnetron plasma sputtering deposition under a high Ar-gas pressure. The Ge nanograins changed from amorphous to crystalline when the distance between the Ge sputtering target and the substrate was decreased to 5 mm and the RF input power was 11.8 W/cm\u0000<sup>2</sup>\u0000 (60 W), where the deposition rate was as high as 660 nm/min. In addition, the size of the nanocrystalline grains increased from 100 to 307 nm when the RF input power for plasma production was increased from 11.8 W/cm\u0000<sup>2</sup>\u0000 (60 W) to 17.7 W/cm\u0000<sup>2</sup>\u0000 (90 W). In the developed narrow-gap plasma process at sub-Torr pressures, nanocrystalline Ge films were successfully fabricated on Cu substrates at low temperatures, without the substrate being heated. However, when annealing was conducted under an N\u0000<sub>2</sub>\u0000 atmosphere, which is the conventional method to induce solid-phase crystallization, the amorphous Ge layer on a Cu substrate changed to a Cu\u0000<sub>3</sub>\u0000Ge crystal layer through interdiffusion of Ge and Cu atoms at 400–500 °C.","PeriodicalId":446,"journal":{"name":"IEEE Open Journal of Nanotechnology","volume":"3 ","pages":"153-158"},"PeriodicalIF":1.7,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9946384","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62888336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-10DOI: 10.1109/OJNANO.2022.3221273
Attila Géczy;Csaba Farkas;Rebeka Kovács;Denis Froš;Petr Veselý;Attila Bonyár
Biodegradables are a promising path for the future of electronics in a greener mindset. The review study focuses on their applications and past and current research results. The paper also investigates the application of nanomaterials as fillers to control or increase the physical (electrical, mechanical, thermal) properties of biodegradable biopolymers. These biodegradables and nanocomposites are already effectively used in prototypes and advanced application areas with demanding requirements, such as flexible and wearable electronics, implantable or biomedical applications, and traditional commercial electronics. The nano-enhanced biopolymer substrates (e.g., with improved gas and water barrier functionalities) sometimes also with integrated, nano-enabled functionalities (such as electromagnetic shielding or plasmonic activity) can be beneficial in many electronics packaging and nanopackaging applications as well.
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