Pub Date : 2024-06-13DOI: 10.1109/TDMR.2024.3414181
Yibo Hu;Hao Ge;Zhipeng Ren;Yizhe Yin;Jing Chen
In this work, we investigated a compact model for characterizing Positive Bias Temperature Instability (PBTI) in 22nm FD-SOI nMOSFETs under dynamic voltage scaling (DVS). This model exhibits high flexibility in predicting PBTI-related threshold voltage degradation in both DC and DVS operations. We measured the impact of time-varying stress and recovery bias conditions, revealing a robust correlation between degradation and relaxation. We integrated the coupling of interface traps and fixed charges into the model, which is deemed a significant contribution. As a result, the model demonstrates high predictive accuracy across various stress conditions, including DC/AC, multiple cycles, and different duty cycles.
{"title":"Modeling of Threshold Voltage Degradation of 22nm FD-SOI nMOSFETs Under Dynamic Voltage Scaling","authors":"Yibo Hu;Hao Ge;Zhipeng Ren;Yizhe Yin;Jing Chen","doi":"10.1109/TDMR.2024.3414181","DOIUrl":"10.1109/TDMR.2024.3414181","url":null,"abstract":"In this work, we investigated a compact model for characterizing Positive Bias Temperature Instability (PBTI) in 22nm FD-SOI nMOSFETs under dynamic voltage scaling (DVS). This model exhibits high flexibility in predicting PBTI-related threshold voltage degradation in both DC and DVS operations. We measured the impact of time-varying stress and recovery bias conditions, revealing a robust correlation between degradation and relaxation. We integrated the coupling of interface traps and fixed charges into the model, which is deemed a significant contribution. As a result, the model demonstrates high predictive accuracy across various stress conditions, including DC/AC, multiple cycles, and different duty cycles.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"463-465"},"PeriodicalIF":2.5,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-03DOI: 10.1109/TDMR.2024.3408293
Yu Zhang;Renqiang Zhu;Haolan Qu;Yitian Gu;Huaxing Jiang;Kei May Lau;Xinbo Zou
Dynamic stability of quasi-vertical GaN trench MOSFETs featuring a thick bottom dielectric (TBD) is thoroughly investigated. Degradation in forward drain current was observed as applying gate or drain stressing voltage, and further studied by time-resolved measurements. The drain current of the device can be maintained at 79%, compared to 61% of a reference device without TBD. Meanwhile, repeated switching tests conducted within a short on-state time demonstrate that the current collapse is confined to 10% after 500 switching cycles. The current collapse is related to electron capture at the dielectric/GaN interface, and the introduction of TBD reduces the electric field within the dielectric layer and suppresses the capture process of traps. Positive gate bias-induced threshold instability of the device with and without TBD is investigated. For the device with TBD, a small positive threshold voltage shift of 1 V is obtained. In addition, the effect of drain stressing voltage on devices is also revealed. High-resolution drain current transient spectroscopy displays the drain current reduction, attributing the degradation to captured electrons in the n--GaN layer. A capture activation energy of 0.26 eV is revealed by deep level transient spectroscopy. These findings reveal the efficacy of TBD inclusion in improving gate stability of GaN MOSFETs and underscore the critical importance of high-quality epitaxial growth for ensuring the stability of vertical devices. The stability characterization serves as a valuable reference for the development of reliable quasi-vertical GaN MOSFET devices.
{"title":"Dynamic Reliability Assessment of Vertical GaN Trench MOSFETs With Thick Bottom Dielectric","authors":"Yu Zhang;Renqiang Zhu;Haolan Qu;Yitian Gu;Huaxing Jiang;Kei May Lau;Xinbo Zou","doi":"10.1109/TDMR.2024.3408293","DOIUrl":"10.1109/TDMR.2024.3408293","url":null,"abstract":"Dynamic stability of quasi-vertical GaN trench MOSFETs featuring a thick bottom dielectric (TBD) is thoroughly investigated. Degradation in forward drain current was observed as applying gate or drain stressing voltage, and further studied by time-resolved measurements. The drain current of the device can be maintained at 79%, compared to 61% of a reference device without TBD. Meanwhile, repeated switching tests conducted within a short on-state time demonstrate that the current collapse is confined to 10% after 500 switching cycles. The current collapse is related to electron capture at the dielectric/GaN interface, and the introduction of TBD reduces the electric field within the dielectric layer and suppresses the capture process of traps. Positive gate bias-induced threshold instability of the device with and without TBD is investigated. For the device with TBD, a small positive threshold voltage shift of 1 V is obtained. In addition, the effect of drain stressing voltage on devices is also revealed. High-resolution drain current transient spectroscopy displays the drain current reduction, attributing the degradation to captured electrons in the n--GaN layer. A capture activation energy of 0.26 eV is revealed by deep level transient spectroscopy. These findings reveal the efficacy of TBD inclusion in improving gate stability of GaN MOSFETs and underscore the critical importance of high-quality epitaxial growth for ensuring the stability of vertical devices. The stability characterization serves as a valuable reference for the development of reliable quasi-vertical GaN MOSFET devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"358-364"},"PeriodicalIF":2.5,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-05-27DOI: 10.1109/tdmr.2024.3405659
Ming-Lang Tseng, Nima E. Gorji
{"title":"Predicting the Degradation and Recovery Trends of the Photovoltaic Efficiency of Sb2Se3 Antimony Solar Cells","authors":"Ming-Lang Tseng, Nima E. Gorji","doi":"10.1109/tdmr.2024.3405659","DOIUrl":"https://doi.org/10.1109/tdmr.2024.3405659","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"13 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141167744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-29DOI: 10.1109/TDMR.2024.3394576
Tommaso Zanotti;Alok Ranjan;Sean J. O’Shea;Nagarajan Raghavan;Ramesh Thamankar;Kin Leong Pey;Francesco Maria Puglisi
The development of a robust and secure hardware for the Internet of Things (IoT) and edge computing requires improvements in the existing low-power and low-cost hardware security primitives. Among the various available technologies, true random number generators (TRNGs) that leverage random telegraph noise (RTN) from nanoelectronics devices have emerged as effective solutions. However, the temporal instabilities in the RTN signal, such as the DC drift and temporary inhibition, are a few of the key reliability challenges for the TRNG circuits. In this study, we have utilized experimental RTN data collected from the commonly used gate dielectrics, including silicon dioxide (SiO2), hafnium dioxide (HfO2), and 2D crystalline hexagonal boron nitride (h-BN) to identify the crucial reliability challenges for RTN-based TRNG circuits. We have analyzed the impact of RTN instabilities and of circuit parameters on the output randomness and propose reliability aware design guidelines. Finally, we design and simulate an RTN-based TRNG circuit using a 130 nm CMOS technology and evaluate its reliability at the circuit level.
{"title":"Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators","authors":"Tommaso Zanotti;Alok Ranjan;Sean J. O’Shea;Nagarajan Raghavan;Ramesh Thamankar;Kin Leong Pey;Francesco Maria Puglisi","doi":"10.1109/TDMR.2024.3394576","DOIUrl":"10.1109/TDMR.2024.3394576","url":null,"abstract":"The development of a robust and secure hardware for the Internet of Things (IoT) and edge computing requires improvements in the existing low-power and low-cost hardware security primitives. Among the various available technologies, true random number generators (TRNGs) that leverage random telegraph noise (RTN) from nanoelectronics devices have emerged as effective solutions. However, the temporal instabilities in the RTN signal, such as the DC drift and temporary inhibition, are a few of the key reliability challenges for the TRNG circuits. In this study, we have utilized experimental RTN data collected from the commonly used gate dielectrics, including silicon dioxide (SiO2), hafnium dioxide (HfO2), and 2D crystalline hexagonal boron nitride (h-BN) to identify the crucial reliability challenges for RTN-based TRNG circuits. We have analyzed the impact of RTN instabilities and of circuit parameters on the output randomness and propose reliability aware design guidelines. Finally, we design and simulate an RTN-based TRNG circuit using a 130 nm CMOS technology and evaluate its reliability at the circuit level.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"184-193"},"PeriodicalIF":2.5,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140832466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-29DOI: 10.1109/TDMR.2024.3394517
Xiyuan Huang;Mingxing Du;Hongze Fu;Sai Gao
This paper introduces a novel online aging monitoring method for bond wires in IGBT modules based on voltage ringing frequency characteristics. The synchronous Buck converter was selected as the IGBT module test system. The influence of the aging degree of upper bridge arm IGBT module on the voltage ringing peak frequency characteristics of the lower bridge arm IGBT module is studied during the switching transient. Considering the influence of junction temperature, power loop wires inductance and driving resistance on the ringing frequency characteristics, this paper measured the standard ringing frequency under the coupling conditions of each factor. Then a standard database under different working conditions is constructed, and the database is used as a criterion to complete the monitoring task. Finally, the converter-level aging monitoring method of bond wires is realized which is non-invasive and real-time. The experimental results show that the proposed method does not need additional equipment, which reduces the complexity of monitoring circuit and has universal applicability.
{"title":"An Aging Monitoring Method of Bond Wires Based on Voltage Ringing Frequency Characteristics in IGBT Modules","authors":"Xiyuan Huang;Mingxing Du;Hongze Fu;Sai Gao","doi":"10.1109/TDMR.2024.3394517","DOIUrl":"10.1109/TDMR.2024.3394517","url":null,"abstract":"This paper introduces a novel online aging monitoring method for bond wires in IGBT modules based on voltage ringing frequency characteristics. The synchronous Buck converter was selected as the IGBT module test system. The influence of the aging degree of upper bridge arm IGBT module on the voltage ringing peak frequency characteristics of the lower bridge arm IGBT module is studied during the switching transient. Considering the influence of junction temperature, power loop wires inductance and driving resistance on the ringing frequency characteristics, this paper measured the standard ringing frequency under the coupling conditions of each factor. Then a standard database under different working conditions is constructed, and the database is used as a criterion to complete the monitoring task. Finally, the converter-level aging monitoring method of bond wires is realized which is non-invasive and real-time. The experimental results show that the proposed method does not need additional equipment, which reduces the complexity of monitoring circuit and has universal applicability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"344-353"},"PeriodicalIF":2.5,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140832749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrates the fabrication, testing, reliability and impact of temperature on the nanostructured vanadium pentoxide (V2O5) based memristor devices. The scalability, repeatability and reliability tests were performed across the devices from 2 inch processed wafers. The reliability test of the memristor devices was conducted by performing real time testing with varying temperature from 293 K to 383 K. The performance metric of the memristor devices were enhanced with the increase in the device testing temperature. The current switching ratio 300 was observed at 383 K, which is $sim$ 250 times higher than the room temperature (RT). In addition, these memristor devices offer highly repeatable and reliable results at optimum temperature of 383 K. These test results have proved that the demonstrated wafer scale synthesized V2O5 based memristors can be used for high temperature applications.
本文展示了基于五氧化二钒（V2O5）的纳米结构忆阻器器件的制造、测试、可靠性以及温度对其的影响。对来自 2 英寸加工晶圆的器件进行了可扩展性、可重复性和可靠性测试。忆阻器器件的可靠性测试是在 293 K 至 383 K 的不同温度下进行的实时测试。在383 K时，电流开关比为300，是室温（RT）的250倍。此外，在 383 K 的最佳温度下，这些忆阻器器件的结果具有很高的可重复性和可靠性。这些测试结果证明，基于 V2O5 的晶圆级合成忆阻器可用于高温应用。
{"title":"Device Reliability and Effect of Temperature on Memristors: Nanostructured V₂O₅","authors":"Sharmila B;Ashutosh Kumar Dikshit;Priyanka Dwivedi","doi":"10.1109/TDMR.2024.3392634","DOIUrl":"10.1109/TDMR.2024.3392634","url":null,"abstract":"This paper demonstrates the fabrication, testing, reliability and impact of temperature on the nanostructured vanadium pentoxide (V2O5) based memristor devices. The scalability, repeatability and reliability tests were performed across the devices from 2 inch processed wafers. The reliability test of the memristor devices was conducted by performing real time testing with varying temperature from 293 K to 383 K. The performance metric of the memristor devices were enhanced with the increase in the device testing temperature. The current switching ratio 300 was observed at 383 K, which is \u0000<inline-formula> <tex-math>$sim$ </tex-math></inline-formula>\u0000250 times higher than the room temperature (RT). In addition, these memristor devices offer highly repeatable and reliable results at optimum temperature of 383 K. These test results have proved that the demonstrated wafer scale synthesized V2O5 based memristors can be used for high temperature applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"329-334"},"PeriodicalIF":2.5,"publicationDate":"2024-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140805822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor $beta $ value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.
{"title":"Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond","authors":"Tidjani Garba-Seybou;Alain Bravaix;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho","doi":"10.1109/TDMR.2024.3387271","DOIUrl":"10.1109/TDMR.2024.3387271","url":null,"abstract":"This study investigates the commonality Of TDDB under Off-state conditions across a range of CMOS nodes, from 130nm to ultra-scaled devices, i.e., 28nm FDSOI CMOS. To achieve this, Off-mode gate-oxide breakdown is analyzed under non-uniform electric field to investigate the effects of stress-induced leakage current, channel current, and lateral electric field in dielectric breakdown mechanism related to RF operations using ultra short channel devices. Oxide breakdown is characterized under DC stress with different gate-length LG as a function of drain voltage VDS and temperature. The study indicates that sub-threshold leakage current is a critical factor in determining the Off-state TDDB degradation, which is caused by a combination of band-to-band tunneling mechanism, junction current and impact ionization phenomena. The proposed Off-state TDDB compact model confirms that the leakage current is a reliable indicator of TDDB dependence precursor to hard-breakdown. Additionally, the paper discusses potential causes of the higher form factor \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000 value for PFET under Off-mode stressing, which may be attributed to high impact ionization, non-conducting hot-carrier effects, defect generation kinetics and a thinner defect cell size.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"174-183"},"PeriodicalIF":2.5,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140635661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Space optical imaging systems are subject during their in-orbit lifetime to many damaging effects caused by aging and harsh conditions (temperature and radiation) in the low Earth orbit environment threatening consequently instruments’ performance and durability. In particular, the time-dependent increase of the detector’s thermally-induced dark current due to temperature rises at the Focal-Plane-Array (FPA) may well lead to an unacceptable degradation in the radiometric performance of the optical imager. The aim of this work is to establish measures for the mitigation of FPA thermal effects on the radiometric performance and calibration of a space-borne optical imaging payload through FPA design optimization and in-orbit operation of the optical imaging payload. The temperature rises at FPA during long strip acquisition are first modeled, and results are used to assess the consequent effect on radiometric performance by predicting time-variable changes in detector offset due to thermal leakage current. Then, based on the outcomes of the thermal model and offset signals calculation, recommendations regarding FPA design and the operation of the optical imaging payload are made to mitigate the effect of FPA temperature rises on the imager’s radiometric performance. Finally, in-flight FPA temperature measurements taken during on-orbit operation are compared with the FPA thermal model results. The modeling results exhibit a strong correspondence with the measurements acquired during the flight. The dark current derived from in-flight data demonstrates that the time-dependent increase in the detector offset signals induced by temperature rises at FPA during image acquisition is negligible, validating the proposed thermal mitigation strategy.
{"title":"Modeling of Temperature Rises at Focal-Plane-Array and Their Impact on the Performance of a CCD-Based Spaceborne Earth-Observing Imaging System","authors":"Chahira Serief;Nassima Khorchef;Youcef Ghelamallah","doi":"10.1109/TDMR.2024.3390798","DOIUrl":"10.1109/TDMR.2024.3390798","url":null,"abstract":"Space optical imaging systems are subject during their in-orbit lifetime to many damaging effects caused by aging and harsh conditions (temperature and radiation) in the low Earth orbit environment threatening consequently instruments’ performance and durability. In particular, the time-dependent increase of the detector’s thermally-induced dark current due to temperature rises at the Focal-Plane-Array (FPA) may well lead to an unacceptable degradation in the radiometric performance of the optical imager. The aim of this work is to establish measures for the mitigation of FPA thermal effects on the radiometric performance and calibration of a space-borne optical imaging payload through FPA design optimization and in-orbit operation of the optical imaging payload. The temperature rises at FPA during long strip acquisition are first modeled, and results are used to assess the consequent effect on radiometric performance by predicting time-variable changes in detector offset due to thermal leakage current. Then, based on the outcomes of the thermal model and offset signals calculation, recommendations regarding FPA design and the operation of the optical imaging payload are made to mitigate the effect of FPA temperature rises on the imager’s radiometric performance. Finally, in-flight FPA temperature measurements taken during on-orbit operation are compared with the FPA thermal model results. The modeling results exhibit a strong correspondence with the measurements acquired during the flight. The dark current derived from in-flight data demonstrates that the time-dependent increase in the detector offset signals induced by temperature rises at FPA during image acquisition is negligible, validating the proposed thermal mitigation strategy.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"335-343"},"PeriodicalIF":2.5,"publicationDate":"2024-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140624935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L ${_{text {JFET}}} = 1.4mu $ m has the best HF-FOM (R ${_{text {on}}} times $ Cgd) and HF-FOM (R ${_{text {on}}} times $ Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.
本研究设计并制造了具有不同 JFET 宽度（LJFET）的平面 SiC VDMOSFET 的六边形单元拓扑结构。通过比较每种设计的动态和静态参数，L ${_{text {JFET}} = 1.4mu $ m 具有最佳的 HF-FOM （R ${_{text {on}} times $ Cgd）和 HF-FOM （R ${_{text {on}} times $ Qgd）。此外，还通过实验和 TCAD 仿真研究了串联设计的 UIS 可靠性和失效机理。结果表明，高温是由雪崩时的能量耗散产生的，它驱动寄生 BJT 导通，导致 Ids 失控，并在极短的时间内瞬时热量集中。极高的温度会导致材料内部开裂和金属熔化，从而造成栅源短路和器件损坏。这将为器件设计和可靠性考虑提供建议。
{"title":"Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width","authors":"Hou-Cai Luo;Huan Wu;Jing-Ping Zhang;Bo-Feng Zheng;Lei Lang;Guo-Qi Zhang;Xian-Ping Chen","doi":"10.1109/TDMR.2024.3388482","DOIUrl":"10.1109/TDMR.2024.3388482","url":null,"abstract":"The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L\u0000<inline-formula> <tex-math>${_{text {JFET}}} = 1.4mu $ </tex-math></inline-formula>\u0000m has the best HF-FOM (R\u0000<inline-formula> <tex-math>${_{text {on}}} times $ </tex-math></inline-formula>\u0000Cgd) and HF-FOM (R\u0000<inline-formula> <tex-math>${_{text {on}}} times $ </tex-math></inline-formula>\u0000Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"323-328"},"PeriodicalIF":2.5,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140608373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article proposes an aging reliability compact model with high accuracy to simulate trap effects after long-term aging in power Gallium Nitride (GaN) based high electron mobility transistors (HEMTs). Dynamic on-state resistance $(R_{mathrm{ on,dy}})$ caused by trap effects is taken as an example to deliver the aging reliability modeling concepts and flows. Based on the mechanism of trap effects and accelerated-stress experiments, the variation model of electron mobility has been established, so that the degradation of $R_{mathrm{ on,dy}}$ after aging can be predicted. The structure of the advanced SPICE model for GaN HEMT (ASM-HEMT) is modified to integrate the mobility variation model into SPICE for convenient usage. In addition, the accuracy of the proposed model has been verified, and the RMSE value between measured data and simulated data under long-term high temperature reverse bias stress conditions is only 1.68%, thus the hazard of the power system caused by traps can be discovered and avoided in advance.
{"title":"Aging Reliability Compact Modeling of Trap Effects in Power GaN HEMTs","authors":"Yanfeng Ma;Sheng Li;Mengli Liu;Weihao Lu;Mingfei Li;Siyang Liu;Long Zhang;Jiaxing Wei;Lanlan Yang;Weifeng Sun;Jiaxin Sun","doi":"10.1109/TDMR.2024.3387573","DOIUrl":"10.1109/TDMR.2024.3387573","url":null,"abstract":"This article proposes an aging reliability compact model with high accuracy to simulate trap effects after long-term aging in power Gallium Nitride (GaN) based high electron mobility transistors (HEMTs). Dynamic on-state resistance \u0000<inline-formula> <tex-math>$(R_{mathrm{ on,dy}})$ </tex-math></inline-formula>\u0000 caused by trap effects is taken as an example to deliver the aging reliability modeling concepts and flows. Based on the mechanism of trap effects and accelerated-stress experiments, the variation model of electron mobility has been established, so that the degradation of \u0000<inline-formula> <tex-math>$R_{mathrm{ on,dy}}$ </tex-math></inline-formula>\u0000 after aging can be predicted. The structure of the advanced SPICE model for GaN HEMT (ASM-HEMT) is modified to integrate the mobility variation model into SPICE for convenient usage. In addition, the accuracy of the proposed model has been verified, and the RMSE value between measured data and simulated data under long-term high temperature reverse bias stress conditions is only 1.68%, thus the hazard of the power system caused by traps can be discovered and avoided in advance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"313-322"},"PeriodicalIF":2.5,"publicationDate":"2024-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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