This work investigates the impact of neutron and heavy ion radiation-induced soft errors on Arm Cortex-M Systems-on-Chip and proposes a fault injection methodology designed for the early assessment of these effects on the embedded processors. Our methodology is then employed to assess the effectiveness of software design exploration and implementing fault tolerance techniques. We connect heavy ion and neutron radiation experiments and emulate fault injections for applications running on these resource-constrained low-cost processors. Our case studies include benchmark scenarios with bare-metal applications and the FreeRTOS operating system, tailored for deployment in small satellite missions. Results show that our proposed methodology presents reliability curves that align with those obtained from the radiation experiments.
{"title":"Early Radiation-Induced Soft-Error Assessment of Arm Cortex-M SoCs Through Fault Injection","authors":"Leonardo Gobatto;Fabio Benevenuti;Rodrigo Possamai Bastos;Nemitala Added;Saulo Alberton;Eduardo Macchione;Vitor Aguiar;Nilberto Medina;Fernanda Kastensmidt;Jose Rodrigo Azambuja","doi":"10.1109/TDMR.2024.3501193","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3501193","url":null,"abstract":"This work investigates the impact of neutron and heavy ion radiation-induced soft errors on Arm Cortex-M Systems-on-Chip and proposes a fault injection methodology designed for the early assessment of these effects on the embedded processors. Our methodology is then employed to assess the effectiveness of software design exploration and implementing fault tolerance techniques. We connect heavy ion and neutron radiation experiments and emulate fault injections for applications running on these resource-constrained low-cost processors. Our case studies include benchmark scenarios with bare-metal applications and the FreeRTOS operating system, tailored for deployment in small satellite missions. Results show that our proposed methodology presents reliability curves that align with those obtained from the radiation experiments.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"45-53"},"PeriodicalIF":2.5,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents enhanced hysteresis width for noise-immune radiation-hardened Schmitt trigger circuits. A dual-mode Domino-based Schmitt trigger (DST) circuit is employed for dual purposes owing to the inclusion of a control module that functions as both a domino logic and a Schmitt trigger circuit. For various ST circuits, key performance metrics including hysteresis width, power consumption, latency, process variation, and critical charge at sensitive nodes are determined. The findings demonstrate that, in comparison to other reference circuits, the DST has improved performance metrics. The proposed DST has $3.89times $ , $1.58times $ , and $1.03times $ lower dynamic power, leakage power, and propagation delay, respectively in comparison to conventional ST. The hysteresis width of DST is $1.32times $ higher than conventional ST which makes it more practical for a noisy environment. All the simulation work has been handled by the Cadence virtuoso tool using UMC 40nm technology.
{"title":"Radiation Hardened Domino Logic-Based Schmitt Trigger Circuit With Improved Noise Immunity","authors":"Aryan Kannaujiya;Shubham Singh;Ambika Prasad Shah;Daniele Rossi","doi":"10.1109/TDMR.2024.3496821","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3496821","url":null,"abstract":"This work presents enhanced hysteresis width for noise-immune radiation-hardened Schmitt trigger circuits. A dual-mode Domino-based Schmitt trigger (DST) circuit is employed for dual purposes owing to the inclusion of a control module that functions as both a domino logic and a Schmitt trigger circuit. For various ST circuits, key performance metrics including hysteresis width, power consumption, latency, process variation, and critical charge at sensitive nodes are determined. The findings demonstrate that, in comparison to other reference circuits, the DST has improved performance metrics. The proposed DST has \u0000<inline-formula> <tex-math>$3.89times $ </tex-math></inline-formula>\u0000, \u0000<inline-formula> <tex-math>$1.58times $ </tex-math></inline-formula>\u0000, and \u0000<inline-formula> <tex-math>$1.03times $ </tex-math></inline-formula>\u0000 lower dynamic power, leakage power, and propagation delay, respectively in comparison to conventional ST. The hysteresis width of DST is \u0000<inline-formula> <tex-math>$1.32times $ </tex-math></inline-formula>\u0000 higher than conventional ST which makes it more practical for a noisy environment. All the simulation work has been handled by the Cadence virtuoso tool using UMC 40nm technology.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"602-609"},"PeriodicalIF":2.5,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the carrier trapping behavior and electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) under different bias conditions are studied based on the transient current. By considering the transient drain current of HEMTs at different temperatures, three trapping mechanisms are identified: (1) charge trapping in the AlGaN barrier layer, in the gate-drain region near the two-dimensional electron gas (2DEG) channel; (2) charge trapping in the GaN layer, in the gate-drain region near the gate; and (3) charge trapping on the surface of the AlGaN layer, in the gate-drain region near the gate. The influences of the source-gate and drain-gate voltages on trapping behavior are analyzed to further elucidate the trap locations. The experimental results show that charge capture is mainly affected by the drain-gate voltage. High electric field stress affects the local structure order inside the device, thus affecting the charge escape rate. The threshold voltage shift is mainly affected by the surface trap of the AlGaN layer near the gate.
{"title":"Trap Location and Stress Degradation Analysis of GaN High Electron Mobility Transistors Based on the Transient Current Method","authors":"Qian Wen;Lixing Zhou;Xianwei Meng;Shiwei Feng;Yamin Zhang","doi":"10.1109/TDMR.2024.3495987","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3495987","url":null,"abstract":"In this paper, the carrier trapping behavior and electrical characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) under different bias conditions are studied based on the transient current. By considering the transient drain current of HEMTs at different temperatures, three trapping mechanisms are identified: (1) charge trapping in the AlGaN barrier layer, in the gate-drain region near the two-dimensional electron gas (2DEG) channel; (2) charge trapping in the GaN layer, in the gate-drain region near the gate; and (3) charge trapping on the surface of the AlGaN layer, in the gate-drain region near the gate. The influences of the source-gate and drain-gate voltages on trapping behavior are analyzed to further elucidate the trap locations. The experimental results show that charge capture is mainly affected by the drain-gate voltage. High electric field stress affects the local structure order inside the device, thus affecting the charge escape rate. The threshold voltage shift is mainly affected by the surface trap of the AlGaN layer near the gate.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"624-630"},"PeriodicalIF":2.5,"publicationDate":"2024-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.
{"title":"Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform","authors":"Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky","doi":"10.1109/TDMR.2024.3488750","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3488750","url":null,"abstract":"As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"637-645"},"PeriodicalIF":2.5,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper simulates the damage of 22nm FDSOI devices under strong electromagnetic pulse in radiation environment. After the introduction of strong electromagnetic pulse in the non-radiating device, the drain - body junction in the center of the device is damaged due to thermal deposition. The results of the strong electromagnetic damage of the device after different total ionizing doses of radiation show that the trap charge trapped in the oxide layer enhances the inverse pattern of the device after radiation. At the same time when the strong electromagnetic pulse is introduced, the electric field intensity in the channel region decreases and the current density increases compared with that before radiation. As a result, the thermal power density of the device increases and the thermal damage time point of the device advances. Finally, the simulation results of different radiation regions show that the trap charge in the BOX layer is the main reason for the reliability reduction of the device.
{"title":"Study on Electromagnetic Pulse Damage of 22nm FDSOI in Radiation Environment","authors":"Chen Chong;Xing Li;Hongxia Liu;Wei Zhou;Menghao Huang","doi":"10.1109/TDMR.2024.3485095","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3485095","url":null,"abstract":"This paper simulates the damage of 22nm FDSOI devices under strong electromagnetic pulse in radiation environment. After the introduction of strong electromagnetic pulse in the non-radiating device, the drain - body junction in the center of the device is damaged due to thermal deposition. The results of the strong electromagnetic damage of the device after different total ionizing doses of radiation show that the trap charge trapped in the oxide layer enhances the inverse pattern of the device after radiation. At the same time when the strong electromagnetic pulse is introduced, the electric field intensity in the channel region decreases and the current density increases compared with that before radiation. As a result, the thermal power density of the device increases and the thermal damage time point of the device advances. Finally, the simulation results of different radiation regions show that the trap charge in the BOX layer is the main reason for the reliability reduction of the device.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"646-655"},"PeriodicalIF":2.5,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage $(V_{T})$ shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.
{"title":"Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress","authors":"Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3478220","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478220","url":null,"abstract":"This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage \u0000<inline-formula> <tex-math>$(V_{T})$ </tex-math></inline-formula>\u0000 shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"631-636"},"PeriodicalIF":2.5,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transformers have achieved remarkable success in diverse fields such as Natural Language Processing (NLP) and computer vision (CV). For pre-trained Transformer models involving text processing, embedding representations are important parameters, incurring a large volume of memory. Soft errors on embedding vectors can lead to incorrect inputs to Transformers, and if not corrected in time, accumulated errors may produce undesirable outcomes. This paper considers the dependability of text related Transformer models to accumulated errors on embedding parameters and takes three typical models in different applications as case studies: BERT based sentence emotion classification, T5 based text summarization, and CLIP based image classification. We first evaluate the dependability of the three models by injecting bit errors on embedding parameters; only errors on a few critical bits affect model performance. Based on this finding, we first propose an efficient selective protection for embedding parameters with small values, and then through scaling, we extend the scheme for models with large embedding parameters. Extensive simulation results show that the proposed protection scheme can effectively remove the impact of soft errors on task performance. In particular, the complexity overhead of the proposed scheme is negligible, and the additional memory overhead as encountered in the SEC scheme is avoided.
{"title":"Dependability and Protection of Transformer Models Against Soft Errors on Text Embeddings","authors":"Zhen Gao;Shuang Liu;Pedro Reviriego;Shanshan Liu;Fabrizio Lombardi","doi":"10.1109/TDMR.2024.3478753","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478753","url":null,"abstract":"Transformers have achieved remarkable success in diverse fields such as Natural Language Processing (NLP) and computer vision (CV). For pre-trained Transformer models involving text processing, embedding representations are important parameters, incurring a large volume of memory. Soft errors on embedding vectors can lead to incorrect inputs to Transformers, and if not corrected in time, accumulated errors may produce undesirable outcomes. This paper considers the dependability of text related Transformer models to accumulated errors on embedding parameters and takes three typical models in different applications as case studies: BERT based sentence emotion classification, T5 based text summarization, and CLIP based image classification. We first evaluate the dependability of the three models by injecting bit errors on embedding parameters; only errors on a few critical bits affect model performance. Based on this finding, we first propose an efficient selective protection for embedding parameters with small values, and then through scaling, we extend the scheme for models with large embedding parameters. Extensive simulation results show that the proposed protection scheme can effectively remove the impact of soft errors on task performance. In particular, the complexity overhead of the proposed scheme is negligible, and the additional memory overhead as encountered in the SEC scheme is avoided.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"54-65"},"PeriodicalIF":2.5,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a key vertical interconnection microstructure, Through-Silicon Via (TSV) plays an important role in three-dimension (3D) chips. The reliability issues of TSV are becoming more and more prominent in the increasingly harsh service environment, and the failure behavior of TSV under thermal cycle loading is the one to be solved urgently. In this study, the thermal expansion behavior and microstructure evolution along different paths and interfaces of TSV under thermal cycle loading are investigated base on Crystal Plasticity Element Method (CPFEM). Results reveal the evolution law of TSV grains and grain boundaries. The mechanical response along different path and interface of TSV is also clarified. Relevant results are expected to provide a certain reference for the failure analysis of TSV.
{"title":"Analysis of Thermal Expansion Behavior and Interface Evolution of TSV Under Thermal Cycle Loading Based on Crystal Plastic Finite Element Method","authors":"Kaihong Hou;Zhengwei Fan;Xun Chen;Shufeng Zhang;Yashun Wang;Yu Jiang","doi":"10.1109/TDMR.2024.3478183","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478183","url":null,"abstract":"As a key vertical interconnection microstructure, Through-Silicon Via (TSV) plays an important role in three-dimension (3D) chips. The reliability issues of TSV are becoming more and more prominent in the increasingly harsh service environment, and the failure behavior of TSV under thermal cycle loading is the one to be solved urgently. In this study, the thermal expansion behavior and microstructure evolution along different paths and interfaces of TSV under thermal cycle loading are investigated base on Crystal Plasticity Element Method (CPFEM). Results reveal the evolution law of TSV grains and grain boundaries. The mechanical response along different path and interface of TSV is also clarified. Relevant results are expected to provide a certain reference for the failure analysis of TSV.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"584-595"},"PeriodicalIF":2.5,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TDMR.2024.3467344
Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang
In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the ${mathrm { V}}_{mathrm { D,kink}}$ in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the ${mathrm { V}}_{mathrm { D,kink}}$ would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the ${mathrm { V}}_{mathrm { D,kink}}$ is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.
{"title":"Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs","authors":"Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang","doi":"10.1109/TDMR.2024.3467344","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467344","url":null,"abstract":"In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"544-548"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TDMR.2024.3468013
Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han
GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.
GaN HEMT器件具有高电子迁移率和优异的电学特性，具有广泛的应用前景。然而，由于缺乏对开关特性的可靠性分析，GaN HEMT器件在实际应用中无法发挥其最大潜力。在本文中，GaN HEMT器件是基于功率循环老化的。通过双脉冲测试，表征了GaN HEMT器件老化后的开关退化行为。试验结果表明：功率循环老化后，开关延时增大，米勒平台变长，开孔振铃减小。为探讨寄生电容对并联电容器开关特性的影响机理，采用双脉冲试验方法研究了寄生电容对并联电容器开关特性的影响。在分析寄生电容模型的基础上，推导了老化后陷阱引起的各寄生电容的退化趋势，并通过实验进行了验证。结果表明，逆压电效应和热电子效应引起的AlGaN层陷阱增加是老化后寄生电容变化的主要原因，而GaN HEMT器件的导通和关断电容具有完全不同的组成机制和变化趋势，导致各开关特性的退化趋势和程度不同。这可以为GaN HEMT器件在长期应用中的可靠性提供有价值的参考。
{"title":"Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging","authors":"Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han","doi":"10.1109/TDMR.2024.3468013","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468013","url":null,"abstract":"GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"610-617"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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