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Enhancing RRAM Reliability: Exploring the Effects of Al Doping on HfO2-Based Devices 提高RRAM可靠性:探索Al掺杂对hfo2基器件的影响
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-18 DOI: 10.1109/TDMR.2025.3581061
Andrea Baroni;Eduardo Pérez;Keerthi Dorai Swamy Reddy;Stefan Pechmann;Christian Wenger;Daniele Ielmini;Cristian Zambelli
This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures ( $125~{^{circ }}$ C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.
本研究提供了基于HfO2和al掺杂HfO2绝缘体的RRAM器件的综合评估,重点关注关键性能指标,包括成形成收率,编程后稳定性(PPS),快速漂移,耐久性和高温保留($125~{^{circ}}$ C)。铝掺杂显著提高了器件的可靠性和稳定性,提高了成形率,减少了编程和保留测试期间的电流漂移,并最大限度地减少了耐力循环期间的可变性。虽然与纯HfO2相比,Al5%:HfO2实现了大部分可观察到的优势,但Al7%:HfO2为需要极高可靠性的场景提供了增量优势。这些发现将al掺杂HfO2器件定位为基于内存和神经形态计算的rram系统的有前途的解决方案,突出了性能提升和制造复杂性增加之间的潜在权衡。这项工作强调了材料工程在特定应用环境中优化RRAM器件的重要性。
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引用次数: 0
Design of 2T DRAM Cell With Surrounding Poly-Si Capacitor for Enhanced Retention and Mitigated Coupling Effect 采用多晶硅电容的2T DRAM电池的设计,以增强保持和减轻耦合效应
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-11 DOI: 10.1109/TDMR.2025.3578692
Seonghwan Kong;Wonbo Shim
Two-transistors-zero-capacitor (2T0C) DRAM-based processing-in-memory (PIM) system experiences retention degradation and capacitive coupling effects because of its volatile characteristics and capacitorless structure. These challenges result in degraded reliability and significant energy consumption due to frequent refresh operations. In this work, we propose a cell structure with surrounding polycrystalline silicon capacitor (poly-Cap.) to enhance the storage node capacitance of the vertical-transistor on gate (VTG) DRAM cell introduced in our previous work. The poly-Cap. improves the retention characteristics and mitigates the capacitive coupling effects while maintaining its unit cell area. We modeled the VTG DRAM cell with the poly-Cap. and analyzed its device characteristics using TCAD simulations. Additionally, we evaluated the inference accuracy of the 2T DRAM-based PIM system using a customized simulation framework. We confirmed that the poly-Cap. increased the storage node capacitance by 31.9%, improved the retention characteristics by 83.3% and reduced the capacitive coupling effects by 52.4% during the write ‘1’ operation and 27.3% during the read ‘1’ operation.
基于双晶体管-零电容(2T0C) dram的PIM系统由于其易失性和无电容结构导致保留退化和电容耦合效应。由于频繁的刷新操作,这些挑战会导致可靠性下降和大量的能源消耗。在这项工作中,我们提出了一种围绕多晶硅电容器(poly-Cap)的电池结构,以增强我们之前工作中介绍的垂直晶体管门上晶体管(VTG) DRAM电池的存储节点电容。poly-Cap。改善保留特性和减轻电容耦合效应,同时保持其单位电池面积。我们用poly-Cap对VTG DRAM单元进行了建模。并利用TCAD仿真分析了其器件特性。此外,我们使用定制的仿真框架评估了基于2T dram的PIM系统的推理精度。我们确认了poly-Cap。在写“1”操作和读“1”操作期间,电容耦合效应分别降低了52.4%和27.3%,存储节点容量提高了31.9%,保持特性提高了83.3%。
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引用次数: 0
Exploration of the exciting world of multifunctional oxide-based electronic devices: from material to system-level applications 探索令人兴奋的多功能氧化物基电子器件世界:从材料到系统级应用
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3575823
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引用次数: 0
Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on: OFS-29 宣布IEEE/Optica出版集团光波技术杂志特刊:OFS-29
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3575821
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引用次数: 0
Call for Nominations for Editor-in-Chief IEEE Electron Device Letters IEEE电子设备通讯总编辑提名
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3558657
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引用次数: 0
IEEE Transactions on Device and Materials Reliability Information for Authors IEEE器件与材料可靠性信息学报
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3575830
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引用次数: 0
Reliability of Advanced Nodes 高级节点可靠性
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3575822
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引用次数: 0
IEEE Transactions on Device and Materials Reliability Publication Information IEEE器件与材料可靠性学报
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3558210
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引用次数: 0
Call for Nominations for Editor-in-Chief IEEE Transactions on Electron Devices(TED) IEEE电子设备汇刊(TED)总编辑提名公告
IF 2.5 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3558656
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引用次数: 0
Temperature Dependence of Single-Event Burnout Across Varying LET Levels 不同LET水平的单事件燃尽的温度依赖性
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-06-09 DOI: 10.1109/TDMR.2025.3578041
Fengkai Liu;Zhijie Zhou;Yadong Wei;Xiaodong Xu;Zhongli Liu;Jianqun Yang;Xingji Li
This study investigates the influence of temperature on single-event burnout (SEB) in n-channel 115-V-rated vertical-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) subjected to irradiation by heavy ions of krypton and tantalum. The experiments spanned a temperature range from 25°C to 200°C, and it is indicated that a marked reduction in SEB sensitivity as the temperature increased. Our analysis methodically examines the interplay among the parasitic bipolar junction transistor (BJT) feedback mechanism, avalanche multiplication, charge collection, and SEB triggering processes. We propose a hypothesis that elevated temperatures decrease carrier mobility, reduce carrier lifetime, and diminish the impact ionization rate, which collectively leads to a reduction in charge collection and attenuates the lateral base current, thereby lowering SEB sensitivity. This hypothesis was substantiated through technology computer-aided design (TCAD) simulations. The findings reveal a consistent pattern in the temperature’s effect on SEB across all linear energy transfer (LET) levels examined, providing essential insights for the utilization of power VDMOS transistors in high-temperature, intense-radiation environments such as those encountered in space applications.
本文研究了温度对氪和钽重离子辐照下n通道115 v额定垂直扩散金属氧化物半导体场效应晶体管(vdmosfet)单事件烧断(SEB)的影响。实验温度范围从25°C到200°C,结果表明,随着温度的升高,SEB的灵敏度显著降低。我们的分析系统地考察了寄生双极结晶体管(BJT)反馈机制、雪崩倍增、电荷收集和SEB触发过程之间的相互作用。我们提出了一个假设,升高的温度会降低载流子迁移率,降低载流子寿命,并降低冲击电离率,这些因素共同导致电荷收集减少和横向基极电流衰减,从而降低SEB灵敏度。通过计算机辅助设计(TCAD)模拟技术证实了这一假设。研究结果揭示了温度对所有线性能量传递(LET)水平的SEB影响的一致模式,为在高温、强辐射环境(如空间应用中遇到的环境)中使用功率VDMOS晶体管提供了重要的见解。
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引用次数: 0
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