Pub Date : 2025-08-12DOI: 10.1109/TDMR.2025.3597973
Dustin T. Hassenmayer;Patrick M. Lenahan;Edward S. Bielejec;Joshua M. Young;David J. Spry
We utilize Electrically Detected Magnetic Resonance (EDMR) and Near-Zero-Field Magnetoresistance (NZFMR) to identify the physical and chemical nature of atomic scale defects generated by proton bombardment of 4H-SiC Schottky diodes. We use EDMR and NZFMR to explore proton irradiation created deep level defects which contribute to trap-assisted tunneling through the Schottky barrier. We measure the spin-dependent response of the deep level defect for both an irradiated and unirradiated diode to compare the effects that proton irradiation has on device performance. We observe that the unirradiated diode has no response, and the irradiated diode has a large response. The maximum change in current ($Delta {I}$ /I) due to NZFMR is 0.44% which occurs at 1.3V forward bias. The nature of the response is consistent with several reports of spin-dependent trap-assisted tunneling (SDTAT) [11, 15, 23, 24]. The EDMR response has an isotropic g-value of 2.003 and is ~10G wide. We tentatively ascribe this response to a negatively charged silicon vacancy (${mathrm {V}}_{text {Si-}}$ ). Our work shows that EDMR and NZFMR have the sensitivity and analytical power to study the physical and chemical nature of point defects caused by particle irradiation in these devices. More Importantly, it suggests that these techniques may be widely applicable to investigations of particle irradiation on semiconductor devices.
{"title":"Detection of Proton Irradiation Damage in 4H-SiC Schottky Diodes Via Electrically Detected Magnetic Resonance and Near-Zero-Field Magnetoresistance","authors":"Dustin T. Hassenmayer;Patrick M. Lenahan;Edward S. Bielejec;Joshua M. Young;David J. Spry","doi":"10.1109/TDMR.2025.3597973","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3597973","url":null,"abstract":"We utilize Electrically Detected Magnetic Resonance (EDMR) and Near-Zero-Field Magnetoresistance (NZFMR) to identify the physical and chemical nature of atomic scale defects generated by proton bombardment of 4H-SiC Schottky diodes. We use EDMR and NZFMR to explore proton irradiation created deep level defects which contribute to trap-assisted tunneling through the Schottky barrier. We measure the spin-dependent response of the deep level defect for both an irradiated and unirradiated diode to compare the effects that proton irradiation has on device performance. We observe that the unirradiated diode has no response, and the irradiated diode has a large response. The maximum change in current (<inline-formula> <tex-math>$Delta {I}$ </tex-math></inline-formula>/I) due to NZFMR is 0.44% which occurs at 1.3V forward bias. The nature of the response is consistent with several reports of spin-dependent trap-assisted tunneling (SDTAT) [11, 15, 23, 24]. The EDMR response has an isotropic g-value of 2.003 and is ~10G wide. We tentatively ascribe this response to a negatively charged silicon vacancy (<inline-formula> <tex-math>${mathrm {V}}_{text {Si-}}$ </tex-math></inline-formula>). Our work shows that EDMR and NZFMR have the sensitivity and analytical power to study the physical and chemical nature of point defects caused by particle irradiation in these devices. More Importantly, it suggests that these techniques may be widely applicable to investigations of particle irradiation on semiconductor devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"394-400"},"PeriodicalIF":2.3,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-12DOI: 10.1109/TDMR.2025.3598012
Bowen Zhang;Xinyan Lu;Yibin Sun;Youzheng Wang;Yun-Hui Mei
The heat generated by IGBT modules during DC/AC power conversion requires the development of highly efficient direct-cooled thermal dissipation structures. Herein, direct-cooled IGBTs are realized using sintered silver (Ag) as the thermal interface materials (TIMs) between DBC substrate and heat sink. The high thermal homogeneity of Sintered Ag-IGBTs is first confirmed by the thermal performance differences derived from finite element simulations. The heat transfer advantage of sintered Ag enables fast thermal conduction from chip to heat sink, thus reducing the dynamic switching losses of Sintered Ag-IGBTs by 26%. Compared to SAC 305-IGBTs, the output current of Sintered Ag-IGBTs increased from 812 A to 848 A under the same driving conditions. Due to the low interfacial thermal resistance of sintered silver, the average thermal resistance reduction of 11.9% and the average chip junction temperature reduction of $5.5~^{circ }$ C are realized in Sintered Ag-IGBTs. The high output power and thermal reliability of direct-cooled IGBTs are expected to facilitate their high-power density applications.
{"title":"Sintered Silver-Based Direct-Cooled IGBTs With High Output Power and Thermal Reliability","authors":"Bowen Zhang;Xinyan Lu;Yibin Sun;Youzheng Wang;Yun-Hui Mei","doi":"10.1109/TDMR.2025.3598012","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3598012","url":null,"abstract":"The heat generated by IGBT modules during DC/AC power conversion requires the development of highly efficient direct-cooled thermal dissipation structures. Herein, direct-cooled IGBTs are realized using sintered silver (Ag) as the thermal interface materials (TIMs) between DBC substrate and heat sink. The high thermal homogeneity of Sintered Ag-IGBTs is first confirmed by the thermal performance differences derived from finite element simulations. The heat transfer advantage of sintered Ag enables fast thermal conduction from chip to heat sink, thus reducing the dynamic switching losses of Sintered Ag-IGBTs by 26%. Compared to SAC 305-IGBTs, the output current of Sintered Ag-IGBTs increased from 812 A to 848 A under the same driving conditions. Due to the low interfacial thermal resistance of sintered silver, the average thermal resistance reduction of 11.9% and the average chip junction temperature reduction of <inline-formula> <tex-math>$5.5~^{circ }$ </tex-math></inline-formula>C are realized in Sintered Ag-IGBTs. The high output power and thermal reliability of direct-cooled IGBTs are expected to facilitate their high-power density applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"734-741"},"PeriodicalIF":2.3,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-12DOI: 10.1109/TDMR.2025.3598109
Bowen Zhang;Lijia Wang;Yilong Xie;Yiqin Liu;Youzheng Wang;Yi Liu;Yun-Hui Mei
The high operation temperature and large voltage bias service environments of wide bandgap (WBG) devices often result in the failure of sintered silver layer due to electrochemical migration (ECM). Herein, novel silver-based paste was prepared by incorporating 5 wt% In particles (Ag-5%In), which effectively balanced the ECM lifetime and the reliability of bonding samples. During high temperatures (400 °C) and high voltages (400 V) ECM tests, the preferential formation of In2O3 in Ag-5%In paste effectively inhibited the oxidation and ionization processes of Ag, thereby prolonging the ECM failure time from 462 min to 839 min. In addition, the formation of Ag-In intermetallic compounds (IMCs) and the densification of interconnection layer resulted in high reliability of Ag-5%In paste during the thermal shock test (TST), with the average shear strength remaining around 24.6 MPa after 1000 TST cycles. The comprehensive ECM and mechanical reliability make the proposed Ag-5%In paste a promising packaging material for high-temperature and high-voltage applications of WBG devices.
{"title":"Simultaneous Enhancement of Electrochemical Migration Lifetime and Reliability of Sintered Silver","authors":"Bowen Zhang;Lijia Wang;Yilong Xie;Yiqin Liu;Youzheng Wang;Yi Liu;Yun-Hui Mei","doi":"10.1109/TDMR.2025.3598109","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3598109","url":null,"abstract":"The high operation temperature and large voltage bias service environments of wide bandgap (WBG) devices often result in the failure of sintered silver layer due to electrochemical migration (ECM). Herein, novel silver-based paste was prepared by incorporating 5 wt% In particles (Ag-5%In), which effectively balanced the ECM lifetime and the reliability of bonding samples. During high temperatures (400 °C) and high voltages (400 V) ECM tests, the preferential formation of In2O3 in Ag-5%In paste effectively inhibited the oxidation and ionization processes of Ag, thereby prolonging the ECM failure time from 462 min to 839 min. In addition, the formation of Ag-In intermetallic compounds (IMCs) and the densification of interconnection layer resulted in high reliability of Ag-5%In paste during the thermal shock test (TST), with the average shear strength remaining around 24.6 MPa after 1000 TST cycles. The comprehensive ECM and mechanical reliability make the proposed Ag-5%In paste a promising packaging material for high-temperature and high-voltage applications of WBG devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"535-544"},"PeriodicalIF":2.3,"publicationDate":"2025-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-06DOI: 10.1109/TDMR.2025.3596380
Dmytro Petryk;Peter Langendoerfer;Zoya Dyka
In this work, we provide an overview of our front-side Fault Injection (FI) experiments with different logic cells manufactured in two IHP BiCMOS technologies using Riscure equipment for laser FIs. We were able to inject faults into different types of cells including standard library cells as well as into two types of radiation tolerant flip-flops. Experimenting with radiation-tolerant flip-flops faults were injected illuminating areas with PMOS transistors in OFF state. We determined the cells areas, which were sensitive to the laser FI attacks. Only few works discussed this aspect in the past determining NMOS transistors as the sensitive part of the logic cells. Knowledge about the areas which are sensitive to the laser FI attacks can be generalized experimenting with other technologies and used in future by designers to implement corresponding countermeasure(s) at the initial stage of chip development.
{"title":"Sensitivity of Logic Cells to Laser Fault Injections: An Overview of Experimental Results for IHP Technologies","authors":"Dmytro Petryk;Peter Langendoerfer;Zoya Dyka","doi":"10.1109/TDMR.2025.3596380","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3596380","url":null,"abstract":"In this work, we provide an overview of our front-side Fault Injection (FI) experiments with different logic cells manufactured in two IHP BiCMOS technologies using Riscure equipment for laser FIs. We were able to inject faults into different types of cells including standard library cells as well as into two types of radiation tolerant flip-flops. Experimenting with radiation-tolerant flip-flops faults were injected illuminating areas with PMOS transistors in OFF state. We determined the cells areas, which were sensitive to the laser FI attacks. Only few works discussed this aspect in the past determining NMOS transistors as the sensitive part of the logic cells. Knowledge about the areas which are sensitive to the laser FI attacks can be generalized experimenting with other technologies and used in future by designers to implement corresponding countermeasure(s) at the initial stage of chip development.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"410-423"},"PeriodicalIF":2.3,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11115104","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an in-depth analysis of fast Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) in DRAM CMOS periphery devices, focusing on NMOS and PMOS transistors. Using rapid measurement techniques, we evaluate BTI degradation under both DC and AC stress modes. Our findings reveal that AC Negative BTI-Mode B (NBTI) shows frequency independence. Positive BTI (PBTI) in AC mode (A and B) also demonstrates frequency independence. Additionally, the study uncovers trends in TDDB behavior for NMOS and PMOS devices. PMOS TDDB performance improves at higher frequencies compared to DC, while NMOS TDDB shows degradation at lower frequencies with improved performance at higher frequencies. These results suggest a need for further investigation into the correlation between these reliability mechanisms to develop effective mitigation strategies. By exploring the relationships between BTI and TDDB, we aim to enhance the knowledge of those two similar (from the device point of view during stress) mechanisms
本文深入分析了DRAM CMOS外围器件中的快速偏置温度不稳定性（BTI）和时间相关介电击穿（TDDB），重点是NMOS和PMOS晶体管。使用快速测量技术，我们评估了BTI在直流和交流应力模式下的降解。我们的研究结果表明AC - BTI-Mode B （NBTI）具有频率无关性。交流模式（A和B）的正BTI （PBTI）也表现出频率无关性。此外，该研究还揭示了NMOS和PMOS器件的TDDB行为趋势。与直流相比，PMOS TDDB在较高频率下性能有所提高，而NMOS TDDB在较低频率下性能有所下降，但在较高频率下性能有所提高。这些结果表明，需要进一步研究这些可靠性机制之间的相关性，以制定有效的缓解策略。通过探索BTI和TDDB之间的关系，我们的目标是增强对这两种相似机制的认识（从器件在应力期间的角度来看）
{"title":"Assessing the Reliability of DRAM CMOS Periphery: Comparing AC and DC Conditions for BTI and TDDB","authors":"Alexandre Subirats;Mehran Samiee;Giovanni Ferrari;Uma Sharma;Takuya Imamoto;Masahiro Yokomichi;Shivani Srivastava;Karine Florent;Tim Owens","doi":"10.1109/TDMR.2025.3595501","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3595501","url":null,"abstract":"This paper presents an in-depth analysis of fast Bias Temperature Instability (BTI) and Time-Dependent Dielectric Breakdown (TDDB) in DRAM CMOS periphery devices, focusing on NMOS and PMOS transistors. Using rapid measurement techniques, we evaluate BTI degradation under both DC and AC stress modes. Our findings reveal that AC Negative BTI-Mode B (NBTI) shows frequency independence. Positive BTI (PBTI) in AC mode (A and B) also demonstrates frequency independence. Additionally, the study uncovers trends in TDDB behavior for NMOS and PMOS devices. PMOS TDDB performance improves at higher frequencies compared to DC, while NMOS TDDB shows degradation at lower frequencies with improved performance at higher frequencies. These results suggest a need for further investigation into the correlation between these reliability mechanisms to develop effective mitigation strategies. By exploring the relationships between BTI and TDDB, we aim to enhance the knowledge of those two similar (from the device point of view during stress) mechanisms","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"388-393"},"PeriodicalIF":2.3,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-04DOI: 10.1109/TDMR.2025.3595573
Madhulika Verma;Ankita Singh;Sachin Agrawal
This article presents a Triple Metal Gate-Dual Dielectric-GaAs Pocket-Heterojunction Tunnel Field Effect Transistor (TMG-DD-GaAs-pocket-HTFET) for low-power and high-speed applications. To enhance carrier confinement and suppress ambipolar current, the device integrates triple gates (M1, M2, and M3) with a dual-dielectric stack of HfO2/SiO2 on a single layer. Additionally, SiGe is utilized as the source material to improve tunneling efficiency, while GaAs is employed as the pocket material to enhance carrier injection and overall device performance. The device’s characteristics are investigated using the Silvaco-TCAD simulator, focusing on its switching behavior and subthreshold performance. Further, the device’s immunity under interface trap charge (ITC) like positive (P-ITC), negative (N-ITC), and without interface trap charge (W-ITC) conditions is investigated. At a gate and drain voltage of 0.5 V, the W-ITC configuration achieves a low threshold voltage (Vth) of 0.19 V, an ultra-low subthreshold swing (SS) of 2.53 mV/decade, and a high ION of $5.83times 10{^{text {-5}}}$ A, with an exceptional ION/IOFF ratio of $1.42times 10{^{{12}}}$ . The results show that the device’s performance is unaffected by the presence of positive or negative interface trap charges. These findings ensured that the proposed TMG-DD-GaAs-pocket-HTFET is a highly promising option for low-power, high-speed applications, with excellent scalability and enhanced performance. Key analog/RF parameters, including transconductance $(g_{m})$ , gate capacitance ($C_{gd}$ , $C_{gs}$ ), cut-off frequency $(f_{T})$ , transconductance frequency product (TFP), and gain-bandwidth product (GBP), have been calculated. Additionally, an in-depth analysis under W-ITC condition is performed to assess the impact of varying gate work functions, gate lengths, and pocket materials on the device’s performance.
{"title":"An Improved Steep-Slope Triple Metal Gate-Dual Dielectric-GaAs-Pocket-HTFET With Interface Trap Charges Analysis","authors":"Madhulika Verma;Ankita Singh;Sachin Agrawal","doi":"10.1109/TDMR.2025.3595573","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3595573","url":null,"abstract":"This article presents a Triple Metal Gate-Dual Dielectric-GaAs Pocket-Heterojunction Tunnel Field Effect Transistor (TMG-DD-GaAs-pocket-HTFET) for low-power and high-speed applications. To enhance carrier confinement and suppress ambipolar current, the device integrates triple gates (M1, M2, and M3) with a dual-dielectric stack of HfO2/SiO2 on a single layer. Additionally, SiGe is utilized as the source material to improve tunneling efficiency, while GaAs is employed as the pocket material to enhance carrier injection and overall device performance. The device’s characteristics are investigated using the Silvaco-TCAD simulator, focusing on its switching behavior and subthreshold performance. Further, the device’s immunity under interface trap charge (ITC) like positive (P-ITC), negative (N-ITC), and without interface trap charge (W-ITC) conditions is investigated. At a gate and drain voltage of 0.5 V, the W-ITC configuration achieves a low threshold voltage (Vth) of 0.19 V, an ultra-low subthreshold swing (SS) of 2.53 mV/decade, and a high ION of <inline-formula> <tex-math>$5.83times 10{^{text {-5}}}$ </tex-math></inline-formula> A, with an exceptional ION/IOFF ratio of <inline-formula> <tex-math>$1.42times 10{^{{12}}}$ </tex-math></inline-formula>. The results show that the device’s performance is unaffected by the presence of positive or negative interface trap charges. These findings ensured that the proposed TMG-DD-GaAs-pocket-HTFET is a highly promising option for low-power, high-speed applications, with excellent scalability and enhanced performance. Key analog/RF parameters, including transconductance <inline-formula> <tex-math>$(g_{m})$ </tex-math></inline-formula>, gate capacitance (<inline-formula> <tex-math>$C_{gd}$ </tex-math></inline-formula>, <inline-formula> <tex-math>$C_{gs}$ </tex-math></inline-formula>), cut-off frequency <inline-formula> <tex-math>$(f_{T})$ </tex-math></inline-formula>, transconductance frequency product (TFP), and gain-bandwidth product (GBP), have been calculated. Additionally, an in-depth analysis under W-ITC condition is performed to assess the impact of varying gate work functions, gate lengths, and pocket materials on the device’s performance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"668-676"},"PeriodicalIF":2.3,"publicationDate":"2025-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TDMR.2025.3594470
Ya-Zhi Hu;Ming-Dou Ker
This work presents a comprehensive study on the electrostatic discharge (ESD) and surge robustness of 4H-SiC vertical double-implanted MOSFETs (VDMOSFETs). The ESD analysis includes human-body-model (HBM) and transmission-line-pulse (TLP) testing across various stress modes, complemented by transient waveform measurements and TCAD simulations. The surge analysis also introduces the transient analysis and TCAD simulation. Both single and repetitive surge stress surge tests are conducted to evaluate electrical degradation behavior. In both HBM ESD and surge tests, GS and –DG modes are vulnerable to gate oxide breakdown. Physical failure analysis techniques, including Optical Beam Induced Resistance Change (OBIRCH), Scanning Electron Microscopy (SEM), and Focused Ion Beam (FIB) techniques, are used to identify damage locations and failure mechanisms of the failure samples.
{"title":"Investigation on Electrostatic Discharge and Surge Robustness of Silicon Carbide High-Voltage Devices","authors":"Ya-Zhi Hu;Ming-Dou Ker","doi":"10.1109/TDMR.2025.3594470","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3594470","url":null,"abstract":"This work presents a comprehensive study on the electrostatic discharge (ESD) and surge robustness of 4H-SiC vertical double-implanted MOSFETs (VDMOSFETs). The ESD analysis includes human-body-model (HBM) and transmission-line-pulse (TLP) testing across various stress modes, complemented by transient waveform measurements and TCAD simulations. The surge analysis also introduces the transient analysis and TCAD simulation. Both single and repetitive surge stress surge tests are conducted to evaluate electrical degradation behavior. In both HBM ESD and surge tests, GS and –DG modes are vulnerable to gate oxide breakdown. Physical failure analysis techniques, including Optical Beam Induced Resistance Change (OBIRCH), Scanning Electron Microscopy (SEM), and Focused Ion Beam (FIB) techniques, are used to identify damage locations and failure mechanisms of the failure samples.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"601-609"},"PeriodicalIF":2.3,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the 2-D numerical simulation results of the heavy-ion-induced single-event leakage current (SELC) degradation and single-event burnout (SEB) in the silicon-carbide (SiC) avalanche photodiode (APD). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics and spectral response characteristics in experiments. The region most sensitive to heavy ion is identified. Then, the SEB failure behavior of SiC APD is investigated. Based on the analysis of ion-induced SELC degradation or SEB failure, three hardening methods–modifying the mesa etch depth, introducing Low Carrier Lifetime Control (LCLC) region, and inserting buffer layer–are investigated. As a result, the effects of three hardening methods on the electrical properties and SEB performance for SiC APD are compared.
{"title":"Analysis of Single-Event Burnout in 4H-SiC Avalanche Photodiode","authors":"Wang-Zi-Xuan Zhen;Zhong-Qing Zhang;Cheng-Hao Yu;Hao-Min Guo;Masayuki Yamamoto;Da-Wei Wang;Bing Hong;Chun-Sheng Jiang;Wen-Sheng Zhao","doi":"10.1109/TDMR.2025.3593916","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3593916","url":null,"abstract":"This paper presents the 2-D numerical simulation results of the heavy-ion-induced single-event leakage current (SELC) degradation and single-event burnout (SEB) in the silicon-carbide (SiC) avalanche photodiode (APD). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics and spectral response characteristics in experiments. The region most sensitive to heavy ion is identified. Then, the SEB failure behavior of SiC APD is investigated. Based on the analysis of ion-induced SELC degradation or SEB failure, three hardening methods–modifying the mesa etch depth, introducing Low Carrier Lifetime Control (LCLC) region, and inserting buffer layer–are investigated. As a result, the effects of three hardening methods on the electrical properties and SEB performance for SiC APD are compared.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"430-440"},"PeriodicalIF":2.3,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145051067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-28DOI: 10.1109/TDMR.2025.3593375
Yi Jiang;Yanning Chen;Rui Su;Fang Liu;Bo Wu;Yongfeng Deng;Dawei Gao;Junkang Li;Rui Zhang
In this study, the bias temperature instability (BTI) degradation of Si p- and n-MOSFETs fabricated using a 55 nm CMOS process was systematically and quantitatively investigated over stress time $(T_{stress})$ . This analysis focused on key parameters, including threshold voltage shift $(Delta V_{th})$ , subthreshold swing degradation ($Delta $ SS), maximum transconductance reduction ($Delta Gm_{max}$ ), linear region current decrease $(Delta I_{dlin})$ , and 1/f noise performance degradation. By examining the dependence of these parameters on $T_{stress}$ , the corresponding BTI lifetime under weak BTI stress was evaluated. It was found that assessing BTI lifetime via 1/f noise required only 35 s and 50 s for Si p- and n-MOSFETs, respectively. Furthermore, comparing the predicted lifetime derived from degradation data at various $T_{stress}$ with the actual BTI lifetimes (2550 s for p-MOSFETs and 2200 s for n-MOSFETs), the 1/f noise method emerged as the fastest and most accurate approach. This is attributed to its superior linearity and degradation amplitude over $T_{stress}$ on log-log scale. These findings contribute to proposing a novel method for obtaining the BTI lifetime of MOSFETs regarding the 1/f noise degradation, particularly for analog/mixed-signal (AMS) and radio frequency (RF) applications.
{"title":"Evaluation of BTI Lifetime for MOSFETs in 55 nm CMOS Node by 1/f Noise Performance Degradation","authors":"Yi Jiang;Yanning Chen;Rui Su;Fang Liu;Bo Wu;Yongfeng Deng;Dawei Gao;Junkang Li;Rui Zhang","doi":"10.1109/TDMR.2025.3593375","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3593375","url":null,"abstract":"In this study, the bias temperature instability (BTI) degradation of Si p- and n-MOSFETs fabricated using a 55 nm CMOS process was systematically and quantitatively investigated over stress time <inline-formula> <tex-math>$(T_{stress})$ </tex-math></inline-formula>. This analysis focused on key parameters, including threshold voltage shift <inline-formula> <tex-math>$(Delta V_{th})$ </tex-math></inline-formula>, subthreshold swing degradation (<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>SS), maximum transconductance reduction (<inline-formula> <tex-math>$Delta Gm_{max}$ </tex-math></inline-formula>), linear region current decrease <inline-formula> <tex-math>$(Delta I_{dlin})$ </tex-math></inline-formula>, and 1/f noise performance degradation. By examining the dependence of these parameters on <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula>, the corresponding BTI lifetime under weak BTI stress was evaluated. It was found that assessing BTI lifetime via 1/f noise required only 35 s and 50 s for Si p- and n-MOSFETs, respectively. Furthermore, comparing the predicted lifetime derived from degradation data at various <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula> with the actual BTI lifetimes (2550 s for p-MOSFETs and 2200 s for n-MOSFETs), the 1/f noise method emerged as the fastest and most accurate approach. This is attributed to its superior linearity and degradation amplitude over <inline-formula> <tex-math>$T_{stress}$ </tex-math></inline-formula> on log-log scale. These findings contribute to proposing a novel method for obtaining the BTI lifetime of MOSFETs regarding the 1/f noise degradation, particularly for analog/mixed-signal (AMS) and radio frequency (RF) applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"424-429"},"PeriodicalIF":2.3,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-25DOI: 10.1109/TDMR.2025.3592624
Rui Zhou;Tong An;Fei Qin
Certain insulated gate bipolar transistor (IGBT) modules, such as automotive-grade IGBT modules, are often subjected to harsh service environments. Generally, two factors, temperature variation and vibration, exist simultaneously. Under the combined effects of thermal stress and dynamic mechanical stress, the process of crack extension in Al bonding wires accelerates, leading to the premature failure of IGBT modules. However, little is known about the lifetime prediction method that can be used for IGBT modules under combined power cycling–vibration loading conditions. First, this paper establishes a lifetime prediction method that is applicable for predicting the lifetime of IGBT modules under power cycling conditions; this method includes a power loss model, an RC thermal network model and a collector–emitter on-resistance $(r_{mathrm { ce}})$ degradation model. Then, the effect of vibration on the lifetime of the IGBT module is considered in the lifetime prediction method by equating the vibration stress with the thermal stress via finite element (FE) analysis. The method considers the service conditions under combined power cycling–vibration conditions and the self-acceleration effect of Al bond wire damage accumulation on the lifetime of IGBT modules. Using comparisons with experimental results, it is verified that the lifetime prediction method can accurately and efficiently predict the life of an IGBT module under both power cycling conditions and combined power cycling–vibration conditions.
{"title":"Lifetime Prediction Method for IGBT Modules Under Combined Power Cycling–Vibration Conditions","authors":"Rui Zhou;Tong An;Fei Qin","doi":"10.1109/TDMR.2025.3592624","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3592624","url":null,"abstract":"Certain insulated gate bipolar transistor (IGBT) modules, such as automotive-grade IGBT modules, are often subjected to harsh service environments. Generally, two factors, temperature variation and vibration, exist simultaneously. Under the combined effects of thermal stress and dynamic mechanical stress, the process of crack extension in Al bonding wires accelerates, leading to the premature failure of IGBT modules. However, little is known about the lifetime prediction method that can be used for IGBT modules under combined power cycling–vibration loading conditions. First, this paper establishes a lifetime prediction method that is applicable for predicting the lifetime of IGBT modules under power cycling conditions; this method includes a power loss model, an RC thermal network model and a collector–emitter on-resistance <inline-formula> <tex-math>$(r_{mathrm { ce}})$ </tex-math></inline-formula> degradation model. Then, the effect of vibration on the lifetime of the IGBT module is considered in the lifetime prediction method by equating the vibration stress with the thermal stress via finite element (FE) analysis. The method considers the service conditions under combined power cycling–vibration conditions and the self-acceleration effect of Al bond wire damage accumulation on the lifetime of IGBT modules. Using comparisons with experimental results, it is verified that the lifetime prediction method can accurately and efficiently predict the life of an IGBT module under both power cycling conditions and combined power cycling–vibration conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"714-722"},"PeriodicalIF":2.3,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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