As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.
{"title":"Total Ionizing Dose Effects on DC/RF Performances of Emerging Vertical Back-Gate CMOS Platform","authors":"Yue Ma;Jinshun Bi;Biyao Zhao;Linjie Fan;Jianjian Wang;Gangping Yan;Ziming Xu;Baihong Chen;Hanying Deng;Zhiqiang Li;Viktor Stempitsky","doi":"10.1109/TDMR.2024.3488750","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3488750","url":null,"abstract":"As the scaling down of the silicon (Si)-based transistors is reaching its physical limits, the vertical-structure complementary metal-oxide-semiconductor (VCMOS) process has emerged as a promising technology due its comparative advantages, in terms of aggressive scalability. Along these lines, in this work, an emerging nano-scale vertical back-gate (VBG) CMOS platform with gate length depending on the deposition process instead of the accuracy of the lithography process was proposed. In addition, the total ionizing dose (TID) effects on both the direct current and radio frequency characteristics of the proposed VBG MOSFETs were investigated by performing technology computer aided design (TCAD) simulations. Besides, a high integration-density inverter was implemented by the VBG CMOS platform as well. Both the DC and transient performances of the proposed inverter under TID effects were also characterized. From the simulated results it was demonstrated that although the VBG CMOS platform has the potential to be applied in digital integrated circuits (ICs) and RF ICs, the sensitivity to TID is still a problem to be mitigated. This work provides valuable guidelines for the TID-hardened design of VBG MOSFETs and circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"637-645"},"PeriodicalIF":2.5,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper simulates the damage of 22nm FDSOI devices under strong electromagnetic pulse in radiation environment. After the introduction of strong electromagnetic pulse in the non-radiating device, the drain - body junction in the center of the device is damaged due to thermal deposition. The results of the strong electromagnetic damage of the device after different total ionizing doses of radiation show that the trap charge trapped in the oxide layer enhances the inverse pattern of the device after radiation. At the same time when the strong electromagnetic pulse is introduced, the electric field intensity in the channel region decreases and the current density increases compared with that before radiation. As a result, the thermal power density of the device increases and the thermal damage time point of the device advances. Finally, the simulation results of different radiation regions show that the trap charge in the BOX layer is the main reason for the reliability reduction of the device.
{"title":"Study on Electromagnetic Pulse Damage of 22nm FDSOI in Radiation Environment","authors":"Chen Chong;Xing Li;Hongxia Liu;Wei Zhou;Menghao Huang","doi":"10.1109/TDMR.2024.3485095","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3485095","url":null,"abstract":"This paper simulates the damage of 22nm FDSOI devices under strong electromagnetic pulse in radiation environment. After the introduction of strong electromagnetic pulse in the non-radiating device, the drain - body junction in the center of the device is damaged due to thermal deposition. The results of the strong electromagnetic damage of the device after different total ionizing doses of radiation show that the trap charge trapped in the oxide layer enhances the inverse pattern of the device after radiation. At the same time when the strong electromagnetic pulse is introduced, the electric field intensity in the channel region decreases and the current density increases compared with that before radiation. As a result, the thermal power density of the device increases and the thermal damage time point of the device advances. Finally, the simulation results of different radiation regions show that the trap charge in the BOX layer is the main reason for the reliability reduction of the device.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"646-655"},"PeriodicalIF":2.5,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage $(V_{T})$ shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.
{"title":"Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress","authors":"Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3478220","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478220","url":null,"abstract":"This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage \u0000<inline-formula> <tex-math>$(V_{T})$ </tex-math></inline-formula>\u0000 shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"631-636"},"PeriodicalIF":2.5,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a key vertical interconnection microstructure, Through-Silicon Via (TSV) plays an important role in three-dimension (3D) chips. The reliability issues of TSV are becoming more and more prominent in the increasingly harsh service environment, and the failure behavior of TSV under thermal cycle loading is the one to be solved urgently. In this study, the thermal expansion behavior and microstructure evolution along different paths and interfaces of TSV under thermal cycle loading are investigated base on Crystal Plasticity Element Method (CPFEM). Results reveal the evolution law of TSV grains and grain boundaries. The mechanical response along different path and interface of TSV is also clarified. Relevant results are expected to provide a certain reference for the failure analysis of TSV.
{"title":"Analysis of Thermal Expansion Behavior and Interface Evolution of TSV Under Thermal Cycle Loading Based on Crystal Plastic Finite Element Method","authors":"Kaihong Hou;Zhengwei Fan;Xun Chen;Shufeng Zhang;Yashun Wang;Yu Jiang","doi":"10.1109/TDMR.2024.3478183","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3478183","url":null,"abstract":"As a key vertical interconnection microstructure, Through-Silicon Via (TSV) plays an important role in three-dimension (3D) chips. The reliability issues of TSV are becoming more and more prominent in the increasingly harsh service environment, and the failure behavior of TSV under thermal cycle loading is the one to be solved urgently. In this study, the thermal expansion behavior and microstructure evolution along different paths and interfaces of TSV under thermal cycle loading are investigated base on Crystal Plasticity Element Method (CPFEM). Results reveal the evolution law of TSV grains and grain boundaries. The mechanical response along different path and interface of TSV is also clarified. Relevant results are expected to provide a certain reference for the failure analysis of TSV.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"584-595"},"PeriodicalIF":2.5,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TDMR.2024.3467344
Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang
In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the ${mathrm { V}}_{mathrm { D,kink}}$ in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the ${mathrm { V}}_{mathrm { D,kink}}$ would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the ${mathrm { V}}_{mathrm { D,kink}}$ is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.
{"title":"Investigating the Arc-Shaped Kink Drain Voltage of Drain Current With Capacitance-Voltage Measurement Method in GaN HEMTs","authors":"Jui-Tse Hsu;Shawn S. H. Hsu;Ting-Chang Chang;Chen-Hsin Lien;Ting-Tzu Kuo;Chien-Hung Yeh;Jia-Hong Lin;Ya-Huan Lee;Cheng-Hsien Lin;Wei-Chieh Hung;I-Yu Huang","doi":"10.1109/TDMR.2024.3467344","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467344","url":null,"abstract":"In this study, the measure-stress-measure (MSM) technique under the arc-shaped kink drain voltage (VD,kink) conditions is applied to investigate the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 in GaN high electron mobility transistors (HEMTs). Forward and reverse transfer curves indicate that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 would change with gate voltages increasing. However, no previous study has investigated the exact location of traps that would dominate the loci of VD,kink. The results suggest that the trend of on-state current (Ion) degradation is caused by threshold voltage (Vt) shift. Hence, it can be determined that the \u0000<inline-formula> <tex-math>${mathrm { V}}_{mathrm { D,kink}}$ </tex-math></inline-formula>\u0000 is related to the degree of impact ionization, which is dominant by the holes generation in the buffer. In addition, the capacitance-voltage (C-V) measurements reveal that holes generated through impact ionization at the gate edge are responsible for the shift in VD,kink. This physical mechanism is further supported by temperature-dependent analysis. Finally, the results offer a novel C-V measurement to characterize and model the physical mechanisms of the kink effect, which is governed by hot carrier degradation in GaN HEMTs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"544-548"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-30DOI: 10.1109/TDMR.2024.3468013
Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han
GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.
GaN HEMT器件具有高电子迁移率和优异的电学特性，具有广泛的应用前景。然而，由于缺乏对开关特性的可靠性分析，GaN HEMT器件在实际应用中无法发挥其最大潜力。在本文中，GaN HEMT器件是基于功率循环老化的。通过双脉冲测试，表征了GaN HEMT器件老化后的开关退化行为。试验结果表明：功率循环老化后，开关延时增大，米勒平台变长，开孔振铃减小。为探讨寄生电容对并联电容器开关特性的影响机理，采用双脉冲试验方法研究了寄生电容对并联电容器开关特性的影响。在分析寄生电容模型的基础上，推导了老化后陷阱引起的各寄生电容的退化趋势，并通过实验进行了验证。结果表明，逆压电效应和热电子效应引起的AlGaN层陷阱增加是老化后寄生电容变化的主要原因，而GaN HEMT器件的导通和关断电容具有完全不同的组成机制和变化趋势，导致各开关特性的退化趋势和程度不同。这可以为GaN HEMT器件在长期应用中的可靠性提供有价值的参考。
{"title":"Investigation of Switching Characteristics Degradation of GaN HEMT Under Power Cycling Aging","authors":"Shengwei Gao;Xiaoyu Fu;Xingtao Sun;Tian Jinrui;Yesen Han","doi":"10.1109/TDMR.2024.3468013","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468013","url":null,"abstract":"GaN HEMT devices have wide application prospects because of their high electron mobility and excellent electrical characteristics. However, due to the lack of reliability analysis of the switching characteristics, GaN HEMT devices are unable to realize their maximum potential in practical applications. In this paper, GaN HEMT devices are aged based on power cycling. The switching degradation behavior of GaN HEMT devices after aging is characterized by double pulse test. The test results show that the switching delay increases, the Miller platform lengthens, and the opening ringing decreases after power cycle aging. In order to explore the degradation mechanism, the effects of parasitic capacitance on the switching characteristics are characterized by double pulse test of parallel capacitors. Based on the analysis of the parasitic capacitance model, the degradation trend of each parasitic capacitance caused by trap after aging is deduced and verified by experiment. The results show that the trap increase of AlGaN layer caused by inverse piezoelectric effect and hot-electron effect is the main reason for the change of parasitic capacitance after aging, while the on-state and off-state capacitance of GaN HEMT devices have completely different composition mechanism and change trends, which lead to different trends and degrees of degradation of each switching characteristic. This can provide a valuable reference for the reliability of GaN HEMT devices in long-term applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"610-617"},"PeriodicalIF":2.5,"publicationDate":"2024-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A SiC trench junction barrier Schottky diode with multiple P-shield layers and an embedded N+ region (MPNT-JBS) is proposed and investigated for enhancing single-event burnout (SEB) tolerance. The Schottky contact at the sidewall of the trench and the embedded N+ region in MPNT-JBS accelerate the extraction and recombination of holes. The mitigated accumulation of holes contributes to the reduction of the strong electric field near the metal/SiC interface, thus favoring a decrease in the high temperature. Under 50% of the rated voltage ( $V_{mathrm { Cathode}}{=}600$ V), the maximum temperature near the metal/SiC interface in MPNT-JBS decreases by 78% and 71% compared to SiC JBS diode with multilayer N-buffer (MB-JBS), corresponding to the instances when heavy ions with a linear energy transfer (LET) value of 0.53 pC/ $mu $ m strike the middle of the Schottky contact and the P+ region, respectively. In addition, the multilayer P-shield of MPNT-JBS suppresses the peak temperature near the PN junction by enlarging the energy dissipation area and lowering the transient heat power near the PN junction. Compared to MB-JBS, the maximum temperature near the PN junction in MPNT-JBS decreases from 1890 K to 1454 K when heavy ions strike the middle of the P+ region ( $V_{mathrm { Cathode}}{=}600$ V). These results indicate that MPNT-JBS provides potential for enhancing SEB tolerance.
{"title":"A SiC Trench Schottky Diode With Accelerated Hole Extraction and Recombination Structure for Enhancing Single-Event Burnout Tolerance","authors":"Rui Yang;Xiaochuan Deng;Haibo Wu;Xu Li;Xuan Li;Song Bai;Yi Wen;Bo Zhang","doi":"10.1109/TDMR.2024.3468468","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3468468","url":null,"abstract":"A SiC trench junction barrier Schottky diode with multiple P-shield layers and an embedded N+ region (MPNT-JBS) is proposed and investigated for enhancing single-event burnout (SEB) tolerance. The Schottky contact at the sidewall of the trench and the embedded N+ region in MPNT-JBS accelerate the extraction and recombination of holes. The mitigated accumulation of holes contributes to the reduction of the strong electric field near the metal/SiC interface, thus favoring a decrease in the high temperature. Under 50% of the rated voltage (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V), the maximum temperature near the metal/SiC interface in MPNT-JBS decreases by 78% and 71% compared to SiC JBS diode with multilayer N-buffer (MB-JBS), corresponding to the instances when heavy ions with a linear energy transfer (LET) value of 0.53 pC/\u0000<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>\u0000 m strike the middle of the Schottky contact and the P+ region, respectively. In addition, the multilayer P-shield of MPNT-JBS suppresses the peak temperature near the PN junction by enlarging the energy dissipation area and lowering the transient heat power near the PN junction. Compared to MB-JBS, the maximum temperature near the PN junction in MPNT-JBS decreases from 1890 K to 1454 K when heavy ions strike the middle of the P+ region (\u0000<inline-formula> <tex-math>$V_{mathrm { Cathode}}{=}600$ </tex-math></inline-formula>\u0000 V). These results indicate that MPNT-JBS provides potential for enhancing SEB tolerance.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"549-555"},"PeriodicalIF":2.5,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-25DOI: 10.1109/TDMR.2024.3467249
Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park
High-pressure deuterium annealing (HPDA) has been proposed as a promising process to enhance device performance and reliability. However, additional thermal stress after the HPDA can lead to de-passivation of Si-D bonds at the gate dielectric interface. In this study, electrical characterization of deuterium annealed MOSFETs after repetitive thermal stress conditions is performed to obtain guidelines for conducting post-metal annealing. MOSFETs are fabricated on silicon wafer to verify the passivation as well as de-passivation of deuterium. Device parameters including subthreshold swing (SS), on-state current $(I_{mathrm { ON}})$ , off-state current $(I_{mathrm { OFF}})$ , and gate leakage $(I_{mathrm { G}})$ , are comprehensively compared. Finally, hot-carrier injection (HCI) stress is applied to compare the changes in stress immunity resulting from deuterium de-passivation.
{"title":"Investigation of Deuterium De-Passivation by Repetitive Thermal Stress in CMOS Fabrication","authors":"Ju-Won Yeon;Sung-Su Yoon;Hyo-Jun Park;Tae-Hyun Kil;Dong-Hyun Wang;Khwang-Sun Lee;Dae-Han Jung;Ja-Yun Ku;Jun-Young Park","doi":"10.1109/TDMR.2024.3467249","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467249","url":null,"abstract":"High-pressure deuterium annealing (HPDA) has been proposed as a promising process to enhance device performance and reliability. However, additional thermal stress after the HPDA can lead to de-passivation of Si-D bonds at the gate dielectric interface. In this study, electrical characterization of deuterium annealed MOSFETs after repetitive thermal stress conditions is performed to obtain guidelines for conducting post-metal annealing. MOSFETs are fabricated on silicon wafer to verify the passivation as well as de-passivation of deuterium. Device parameters including subthreshold swing (SS), on-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { ON}})$ </tex-math></inline-formula>\u0000, off-state current \u0000<inline-formula> <tex-math>$(I_{mathrm { OFF}})$ </tex-math></inline-formula>\u0000, and gate leakage \u0000<inline-formula> <tex-math>$(I_{mathrm { G}})$ </tex-math></inline-formula>\u0000, are comprehensively compared. Finally, hot-carrier injection (HCI) stress is applied to compare the changes in stress immunity resulting from deuterium de-passivation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"618-623"},"PeriodicalIF":2.5,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TDMR.2024.3467116
Chih-Cherng Liao;Ching-Ho Li;Karuna Nidhi;Chieh-Yao Chuang;Hsien-Feng Liao;Yeh-Ning Jou;Ke-Horng Chen;Jian-Hsing Lee
Although power supply stressed with respect to another supply is one test items of the electrostatic-discharge (ESD) qualification. However, a current path still exists that has not been reported earlier. From the failure analysis result, the damage is located at the high-voltage N-Well (HVNW) guard-ring of the zapped power domain. Based on the TCAD simulation, the failure mechanism is identified, and shows good agreement with silicon. It proves that the ESD current can only flow through the internal circuit of the zapped power domain and P+ guard-ring (VSS) to become a quiescent current before the power clamp device turns on. So, the internal circuit of the zapped power domain and P+ guard-ring become a substrate triggering circuit to turn on the parasitic npn bipolar between two different power domains, resulting in most ESD current flowing through HVNW guard-rings to induce the damage.
{"title":"The Failure Mechanism of Internal Circuit During ESD Striking a Power to Another Power","authors":"Chih-Cherng Liao;Ching-Ho Li;Karuna Nidhi;Chieh-Yao Chuang;Hsien-Feng Liao;Yeh-Ning Jou;Ke-Horng Chen;Jian-Hsing Lee","doi":"10.1109/TDMR.2024.3467116","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3467116","url":null,"abstract":"Although power supply stressed with respect to another supply is one test items of the electrostatic-discharge (ESD) qualification. However, a current path still exists that has not been reported earlier. From the failure analysis result, the damage is located at the high-voltage N-Well (HVNW) guard-ring of the zapped power domain. Based on the TCAD simulation, the failure mechanism is identified, and shows good agreement with silicon. It proves that the ESD current can only flow through the internal circuit of the zapped power domain and P+ guard-ring (VSS) to become a quiescent current before the power clamp device turns on. So, the internal circuit of the zapped power domain and P+ guard-ring become a substrate triggering circuit to turn on the parasitic npn bipolar between two different power domains, resulting in most ESD current flowing through HVNW guard-rings to induce the damage.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"472-479"},"PeriodicalIF":2.5,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-24DOI: 10.1109/TDMR.2024.3467096
Hang Xu;Jianbin Guo;Tianyang Feng;Yafen Yang;David Wei Zhang
In this article, a 60-V split-gate trench vertical double diffused metal-oxide-semiconductor field-effect transistor (SGTVDMOS, SGTMOS) with low on-resistance is designed and manufactured. The device adopts an ultra-deep split gate trench with a grounded bottom shield gate. The electrical parameters degradations subsequent to repeated off-state avalanche and short circuit current pulses are investigated and compared for the first time. After avalanche voltage stress, crucial parameters such as threshold voltage (Vt), Miller capacitance (CGD) remain unaffected. However, a noteworthy change is observed in blocking characteristics, manifested as an increase in breakdown voltage. Conversely, after subjecting the device to short-circuit pulse current stress, a minor reduction in $rm V_{t}$ is noted, while the breakdown characteristics remain constant. Technology computer-aided design (TCAD) simulation and actual test analysis are combined to reveal the degradation mechanism, it has been determined that electron injection degradation occurs under both stresses. However, distinct degradation phenomena occur due to the disparate positions of electron injection. During avalanche stress, electrons within the polysilicon (shield gate) tunnel into the oxide layer of the bottom shielding gate, while hot electron injection occurs near the active trench gate during a continuous short-circuit pulses.
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