Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3371835
{"title":"Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers","authors":"","doi":"10.1109/TDMR.2024.3371835","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3371835","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"155-155"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463653","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3374489
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TDMR.2024.3374489","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3374489","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"156-156"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463703","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3366775
{"title":"Blank Page","authors":"","doi":"10.1109/TDMR.2024.3366775","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3366775","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"C4-C4"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3374231
Le Liu;Fengjuan Wang;Xiangkun Yin;Chuanhong Sun;Xiang Li;Yue Li;Ningmei Yu;Yuan Yang
Three-dimensional integrated circuits (3D ICs) offer performance advantages due to their reduced wiring overcomes the drawbacks of 2D IC and a vital structure called through-silicon via (TSV) is used to connect the adjacent layers vertically. However, the 3D structure will inevitably lead to thermal issues, and poor routing management in 3D ICs will lead to the increase of thermal stress in 3D IC chips and the deterioration of system stability. In this paper, based on thermal equalization, the chip-silicon interposer-printed circuit board (PCB) assembly structure is simulated and analyzed combined with layout design to investigate the impact of layout, solder ball selection, and TSV layout on the routing of 3D IC layout. The simulation results demonstrate our routing optimization method achieves optimized thermal stress, less large local deformation, reduced temperature, and higher system stability.
三维集成电路（3D IC）具有性能优势，因为它减少了布线，克服了二维集成电路的缺点，并使用一种称为硅通孔（TSV）的重要结构垂直连接相邻层。然而，三维结构不可避免地会导致热问题，三维集成电路中不良的布线管理会导致三维集成电路芯片热应力的增加和系统稳定性的下降。本文在热均衡的基础上，结合布局设计，对芯片-硅片互插板-印刷电路板（PCB）组装结构进行了仿真分析，研究了布局、焊球选择和 TSV 布局对 3D IC 布局布线的影响。仿真结果表明，我们的布线优化方法可优化热应力，减少局部大变形，降低温度，提高系统稳定性。
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Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3366730
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2024.3366730","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3366730","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"C3-C3"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463674","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3366774
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2024.3366774","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3366774","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"C2-C2"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463654","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.1109/TDMR.2024.3395907
Michael Waltl;Bernhard Stampfer;Tibor Grasser
Charge trapping at oxide defects poses a serious reliability concern in MOS transistors. For scaled technology nodes, the impact of charge-trapping events on the device behavior becomes even more severe. These events can be seen as discrete steps in the device current, allowing for single-defect analysis. In this context, random telegraph noise (RTN) analysis and time-dependent defect spectroscopy (TDDS) have become very popular in exploring the physical origin of charge trapping at single defects. To improve the accuracy of single-defect analysis, we conduct a Monte Carlo analysis of trap occupancy, enabling us to extract information about the charge emission time of fixed oxide traps from charge capture time data recorded under different stress conditions. The newly gained knowledge is beneficial for accurately calibrating defect models used to explain the charge-trapping dynamics of defects.
氧化物缺陷处的电荷捕获是 MOS 晶体管可靠性的一个严重问题。对于按比例放大的技术节点，电荷捕获事件对器件行为的影响变得更加严重。这些事件可视为器件电流中的离散阶跃，从而可进行单缺陷分析。在这种情况下，随机电报噪声（RTN）分析和随时间变化的缺陷光谱（TDDS）在探索单个缺陷电荷捕获的物理起源方面变得非常流行。为了提高单缺陷分析的准确性，我们对陷阱占用率进行了蒙特卡洛分析，使我们能够从不同应力条件下记录的电荷捕获时间数据中提取有关固定氧化物陷阱电荷发射时间的信息。新获得的知识有利于准确校准用于解释缺陷电荷捕获动态的缺陷模型。
{"title":"Extraction of Charge Trapping Kinetics of Defects From Single-Defect Measurements","authors":"Michael Waltl;Bernhard Stampfer;Tibor Grasser","doi":"10.1109/TDMR.2024.3395907","DOIUrl":"10.1109/TDMR.2024.3395907","url":null,"abstract":"Charge trapping at oxide defects poses a serious reliability concern in MOS transistors. For scaled technology nodes, the impact of charge-trapping events on the device behavior becomes even more severe. These events can be seen as discrete steps in the device current, allowing for single-defect analysis. In this context, random telegraph noise (RTN) analysis and time-dependent defect spectroscopy (TDDS) have become very popular in exploring the physical origin of charge trapping at single defects. To improve the accuracy of single-defect analysis, we conduct a Monte Carlo analysis of trap occupancy, enabling us to extract information about the charge emission time of fixed oxide traps from charge capture time data recorded under different stress conditions. The newly gained knowledge is beneficial for accurately calibrating defect models used to explain the charge-trapping dynamics of defects.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"168-173"},"PeriodicalIF":2.5,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10517280","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140832517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-27DOI: 10.1109/TDMR.2024.3370631
Yangtao Long;Mingtao Lv;Hu He
With the advancement of Moore’s Law, the impact reliability of solder joints has emerged as a critical concern due to the reduction in their size. The board-level drop test, based on the JEDEC standard, is widely employed by researchers to assess the impact performance of electronic packages. Typically, these tests are conducted with boards placed horizontally. However, real-world service environments involve impacts at various angles that can lead to different failure mechanisms in solder joints. In this study, we investigate the impact reliability of microbump interconnect structures under different impact angles. By considering plastic strain analysis, we demonstrate that drop impacts at other angles can be equivalently represented by the scenario with drop angle $alpha =$ 0° impact. Subsequently, we analyze the failure mechanism of microbumps during drop tests and propose a predictive model for their drop life under varying impact angles. Our results indicate that as the drop angle increases, there is a transition in the driving force for microbump failures from tensile and compressive stress to shear stress. The proposed life prediction model exhibits an error rate below 25% and effectively forecasts the drop life of microbumps in advanced packaging.
{"title":"Failure Mechanism and Predictive Modeling for Microbump Interconnects Drop Life Under Diverse Impact Angles in Advanced Packaging","authors":"Yangtao Long;Mingtao Lv;Hu He","doi":"10.1109/TDMR.2024.3370631","DOIUrl":"10.1109/TDMR.2024.3370631","url":null,"abstract":"With the advancement of Moore’s Law, the impact reliability of solder joints has emerged as a critical concern due to the reduction in their size. The board-level drop test, based on the JEDEC standard, is widely employed by researchers to assess the impact performance of electronic packages. Typically, these tests are conducted with boards placed horizontally. However, real-world service environments involve impacts at various angles that can lead to different failure mechanisms in solder joints. In this study, we investigate the impact reliability of microbump interconnect structures under different impact angles. By considering plastic strain analysis, we demonstrate that drop impacts at other angles can be equivalently represented by the scenario with drop angle \u0000<inline-formula> <tex-math>$alpha =$ </tex-math></inline-formula>\u0000 0° impact. Subsequently, we analyze the failure mechanism of microbumps during drop tests and propose a predictive model for their drop life under varying impact angles. Our results indicate that as the drop angle increases, there is a transition in the driving force for microbump failures from tensile and compressive stress to shear stress. The proposed life prediction model exhibits an error rate below 25% and effectively forecasts the drop life of microbumps in advanced packaging.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"241-249"},"PeriodicalIF":2.5,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140003582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-19DOI: 10.1109/TDMR.2024.3367353
T. Takeshita;E. Murakami
The improvement of an mc-Si solar cell through reverse bias and high temperature (BT) aging was investigated using laser beam-induced current (LBIC) and electroluminescence (EL) techniques. We demonstrated that the dark current of the cell decreased with increasing aging time, which led to an increase in the maximum power after BT aging. The improvement in the maximum power was presumed to be due to a reduction in the shunt current in the equivalent circuit model, and we found that the recombination centers in the vicinity of the surface decreased with BT aging. Applying a reverse bias and a high temperature successfully improved the solar cells.
{"title":"Analysis of Multicrystalline Si Solar Cell Improvement Using Laser-Beam-Induced Current Technique","authors":"T. Takeshita;E. Murakami","doi":"10.1109/TDMR.2024.3367353","DOIUrl":"10.1109/TDMR.2024.3367353","url":null,"abstract":"The improvement of an mc-Si solar cell through reverse bias and high temperature (BT) aging was investigated using laser beam-induced current (LBIC) and electroluminescence (EL) techniques. We demonstrated that the dark current of the cell decreased with increasing aging time, which led to an increase in the maximum power after BT aging. The improvement in the maximum power was presumed to be due to a reduction in the shunt current in the equivalent circuit model, and we found that the recombination centers in the vicinity of the surface decreased with BT aging. Applying a reverse bias and a high temperature successfully improved the solar cells.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"219-224"},"PeriodicalIF":2.5,"publicationDate":"2024-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-16DOI: 10.1109/TDMR.2024.3366782
Atif Alkhazali;Mohammad M. Hamasha;Haitham Khaled;Awni Alkhazaleh;Morad Etier
Molybdenum chips are vital in manufacturing photovoltaic cells and electronics because they offer a combination of high reliability, corrosion resistance, and exceptional electrical conductivity. These qualities make them suitable for applications demanding these characteristics. This study delves into the behavior of thin molybdenum films deposited on plastic substrates under increasing stress. Films of 100 nm and 200 nm thicknesses were stretched, revealing intricate relationships between crack formation, film thickness, and electrical conductivity. Scanning electron microscopy captured the evolution of cracks, initially forming perpendicular to stress and later branching at roughly 30 degrees, hinting at anisotropic material behavior. Thicker films displayed lower crack density and less branching, highlighting their enhanced stress resistance. Further, secondary cracks short between the original cracks was developed. Percentage change of electrical resistance mirrored this trend, gradually increasing with strain before a sharp spike and eventual disconnection due to crack-induced conductivity loss. Thinner films succumbed to failure at lower strains. These findings offer valuable insights into the design and optimization of molybdenum-based microelectronic devices and sensors, paving the way for further quantitative analysis to fully elucidate the intricate mechanisms at play.
{"title":"Electro-Mechanical Properties of Molybdenum Thin Film on Polyethylene Terephthalate Subjected to Tensile Stress","authors":"Atif Alkhazali;Mohammad M. Hamasha;Haitham Khaled;Awni Alkhazaleh;Morad Etier","doi":"10.1109/TDMR.2024.3366782","DOIUrl":"10.1109/TDMR.2024.3366782","url":null,"abstract":"Molybdenum chips are vital in manufacturing photovoltaic cells and electronics because they offer a combination of high reliability, corrosion resistance, and exceptional electrical conductivity. These qualities make them suitable for applications demanding these characteristics. This study delves into the behavior of thin molybdenum films deposited on plastic substrates under increasing stress. Films of 100 nm and 200 nm thicknesses were stretched, revealing intricate relationships between crack formation, film thickness, and electrical conductivity. Scanning electron microscopy captured the evolution of cracks, initially forming perpendicular to stress and later branching at roughly 30 degrees, hinting at anisotropic material behavior. Thicker films displayed lower crack density and less branching, highlighting their enhanced stress resistance. Further, secondary cracks short between the original cracks was developed. Percentage change of electrical resistance mirrored this trend, gradually increasing with strain before a sharp spike and eventual disconnection due to crack-induced conductivity loss. Thinner films succumbed to failure at lower strains. These findings offer valuable insights into the design and optimization of molybdenum-based microelectronic devices and sensors, paving the way for further quantitative analysis to fully elucidate the intricate mechanisms at play.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"233-240"},"PeriodicalIF":2.5,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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