This paper focuses on two types of three-transistor structures, known as PNN and PPN, which represent the number of PMOS and NMOS transistors in each configuration. These structures are characterized by their unidirectional flip at the output nodes, as they are spatially surrounded by N-type and P-type diffusion regions respectively. This characteristic makes them suitable for designing radiation-hardened circuits, particularly for Single Event Upset (SEU) tolerance. Three dimensional (3-D) simulations demonstrate that when exposed to energetic particles, the node surrounded by N-type diffusion remains immune to 0 $rightarrow $ 1 flips, while the node surrounded by P-type diffusion remains immune to 1 $rightarrow $ 0 flips. Additionally, the proposed three-transistor blocks ensure that a conducting path from the voltage supply to ground is never formed, thereby preventing excessive power consumption. Building upon these distinct structures, we propose two area-efficient Single-Node-Upset (SNU) tolerant latches, and two Double-Node-Upset (DNU) recoverable latches. Extensive simulations confirm that our proposed latches, referred to as SNUTL-PNN, SNUTL-PPN, DNURL-PNN and DNURL-PPN, exhibit outstanding self-recovery capability in terms of their output nodes. A comparison with other designs reveals that the latches presented in this paper demonstrate advantages in area and power consumption. Moreover, we applied a variant of PNN and PPN to the dynamic flip-flop, True Single Phase Clock (TSPC), which usually operates with little power and at high speeds. Our introduced hardened scheme occupies minimal area, possess short propagation delays, and exhibit relatively low power consumption under normal operating conditions.
本文的重点是两种三晶体管结构，即 PNN 和 PPN，它们分别代表每个配置中 PMOS 和 NMOS 晶体管的数量。这些结构的特点是输出节点单向翻转，因为它们在空间上分别被 N 型和 P 型扩散区包围。这一特性使它们适用于设计辐射加固电路，特别是单事件猝发（SEU）耐受性。三维（3-D）仿真表明，当暴露在高能粒子中时，被N型扩散环绕的节点仍能抵御0次翻转，而被P型扩散环绕的节点仍能抵御1次翻转。此外，所提出的三晶体管块可确保永远不会形成从电源到地的导电路径，从而防止功耗过高。在这些独特结构的基础上，我们提出了两个面积效率高的单节点猝发（SNU）容错锁存器和两个双节点猝发（DNU）可恢复锁存器。大量仿真证实，我们提出的锁存器（分别称为 SNUTL-PNN、SNUTL-PPN、DNURL-PNN 和 DNURL-PPN）在输出节点方面表现出卓越的自恢复能力。与其他设计相比，本文提出的锁存器在面积和功耗方面更具优势。此外，我们还将 PNN 和 PPN 的变体应用于动态触发器 True Single Phase Clock (TSPC)，该触发器通常以较低的功耗高速运行。我们引入的加固方案占用的面积最小，传播延迟短，在正常工作条件下功耗相对较低。
{"title":"Utilizing Two Three-Transistor Structures for Designing Radiation Hardened Circuits","authors":"Xin Liu;Jiaxin Chen;Yinyu Liu;Ke Gu;Siqi Wang;Jianhui Bu;Quanfeng Zhou","doi":"10.1109/TDMR.2023.3344767","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344767","url":null,"abstract":"This paper focuses on two types of three-transistor structures, known as PNN and PPN, which represent the number of PMOS and NMOS transistors in each configuration. These structures are characterized by their unidirectional flip at the output nodes, as they are spatially surrounded by N-type and P-type diffusion regions respectively. This characteristic makes them suitable for designing radiation-hardened circuits, particularly for Single Event Upset (SEU) tolerance. Three dimensional (3-D) simulations demonstrate that when exposed to energetic particles, the node surrounded by N-type diffusion remains immune to 0\u0000<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>\u00001 flips, while the node surrounded by P-type diffusion remains immune to 1\u0000<inline-formula> <tex-math>$rightarrow $ </tex-math></inline-formula>\u00000 flips. Additionally, the proposed three-transistor blocks ensure that a conducting path from the voltage supply to ground is never formed, thereby preventing excessive power consumption. Building upon these distinct structures, we propose two area-efficient Single-Node-Upset (SNU) tolerant latches, and two Double-Node-Upset (DNU) recoverable latches. Extensive simulations confirm that our proposed latches, referred to as SNUTL-PNN, SNUTL-PPN, DNURL-PNN and DNURL-PPN, exhibit outstanding self-recovery capability in terms of their output nodes. A comparison with other designs reveals that the latches presented in this paper demonstrate advantages in area and power consumption. Moreover, we applied a variant of PNN and PPN to the dynamic flip-flop, True Single Phase Clock (TSPC), which usually operates with little power and at high speeds. Our introduced hardened scheme occupies minimal area, possess short propagation delays, and exhibit relatively low power consumption under normal operating conditions.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-19DOI: 10.1109/TDMR.2023.3344639
Mingyue Zheng;Wangyong Chen;Yaoyang Lyu;Linlin Cai
Thermal challenges are increasingly significant for advanced technology, and the operating environment with large temperature variation also acts as one of the crucial threats to the system’s performance and reliability. To improve the temperature immunity of digital circuits, in this work, the supply voltage (VDD) making the delay immune to temperature variation is identified, which differs from the zero-temperature-coefficient (ZTC) point used in analog applications and is defined as the zero-temperature-delay (ZTD) point. The dependencies and optimal selection of ZTD point in digital circuits are studied by simulation. The influence factors including standard cell types and circuit operations have been investigated accordingly. Moreover, the exploration of ZTD point with different delay metrics is discussed, which is the basis of the selection of ZTD point at standard cell level. The ZTD point changes due to the five PVT corners and the selection of the ZTD point under these PVT corners are studied. Taking three kinds of delay chains and benchmark circuits as an example, the ZTD point in the critical path of the circuit is further investigated. The simulation results confirm that utilizing the ZTD voltage during the design of digital circuits can provide a better temperature-resistant solution, which makes sense for temperature immunity digital applications.
{"title":"Reliability and Optimization Simulation Study of Zero-Temperature-Delay Point in Digital Circuits for Advanced Technology","authors":"Mingyue Zheng;Wangyong Chen;Yaoyang Lyu;Linlin Cai","doi":"10.1109/TDMR.2023.3344639","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344639","url":null,"abstract":"Thermal challenges are increasingly significant for advanced technology, and the operating environment with large temperature variation also acts as one of the crucial threats to the system’s performance and reliability. To improve the temperature immunity of digital circuits, in this work, the supply voltage (VDD) making the delay immune to temperature variation is identified, which differs from the zero-temperature-coefficient (ZTC) point used in analog applications and is defined as the zero-temperature-delay (ZTD) point. The dependencies and optimal selection of ZTD point in digital circuits are studied by simulation. The influence factors including standard cell types and circuit operations have been investigated accordingly. Moreover, the exploration of ZTD point with different delay metrics is discussed, which is the basis of the selection of ZTD point at standard cell level. The ZTD point changes due to the five PVT corners and the selection of the ZTD point under these PVT corners are studied. Taking three kinds of delay chains and benchmark circuits as an example, the ZTD point in the critical path of the circuit is further investigated. The simulation results confirm that utilizing the ZTD voltage during the design of digital circuits can provide a better temperature-resistant solution, which makes sense for temperature immunity digital applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-15DOI: 10.1109/TDMR.2023.3343503
Christoph Weimer;Gerhard G. Fischer;Michael Schröter
This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.
{"title":"Characterization, Analysis, and Modeling of Long-Term RF Reliability and Degradation of SiGe HBTs for High Power Density Applications","authors":"Christoph Weimer;Gerhard G. Fischer;Michael Schröter","doi":"10.1109/TDMR.2023.3343503","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3343503","url":null,"abstract":"This paper aims at determining RF operating limits of SiGe HBTs. Long-term stress tests consisting of RF large-signal stress and periodic measurements of small-signal parameters are performed. Reliable dynamic large-signal transistor operation is demonstrated beyond conventional static safe operating limits. In addition, RF operating limits are identified and degradation of SiGe HBTs accelerated by extreme RF stress is systematically characterized, analyzed and modeled. RF-stress-caused degradation is shown to significantly affect the collector current and demonstrated to be different from electrothermal breakdown caused by DC stress. A modeling approach for estimating SiGe HBT degradation under RF large-signal operating conditions is proposed and shown to agree very well with experimental data.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-12DOI: 10.1109/TDMR.2023.3341241
{"title":"2023 Index IEEE Transactions on Device and Materials Reliability Vol. 23","authors":"","doi":"10.1109/TDMR.2023.3341241","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3341241","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10355055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138577947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-08DOI: 10.1109/TDMR.2023.3340711
Anis Fatema;Shirley Chauhan;Mohee Datta Gupta;Aftab M. Hussain
Pressure sensors are subjected to continuous force and stress that may affect the operation of the sensor in the long run. Reliability is a crucial factor that must be considered when designing and fabricating any sensor. It is essential to test the material used in the sensor to assess the reliability of the complete product. In this work, we report the long-term reliability of a flexible pressure sensor mat using a carbon-impregnated polymer, velostat, which is a flexible, light, and thin polymer composite material with piezoresistive properties. We focus on the analysis of the performance of a flexible pressure sensor array under long-term and repeated loading. Tests were performed every fortnight for 210 days. We have observed that the material characteristics of the velostat material change on repeated application of pressure up to a certain time frame. For a given loading, once the material settles, the change in resistance of the material becomes consistent for a given application of pressure. We have also analyzed the changes in the parameters associated with the 2-parameter model, and have analyzed the effect of crosstalk on the sensor matrix for different pitch lengths to select the best pitch that will give us the minimum crosstalk. We have observed that the error rate of the sensor pixels decreased by 53 percentage points in 210 days. The results obtained from the experimental tests for reliability reveal a practical possibility of implementing velostat-based pressure sensors in wearable and healthcare devices and provide steps to take while calibrating an as-fabricated velostat-based sensor.
{"title":"Investigation of the Long-Term Reliability of a Velostat-Based Flexible Pressure Sensor Array for 210 Days","authors":"Anis Fatema;Shirley Chauhan;Mohee Datta Gupta;Aftab M. Hussain","doi":"10.1109/TDMR.2023.3340711","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340711","url":null,"abstract":"Pressure sensors are subjected to continuous force and stress that may affect the operation of the sensor in the long run. Reliability is a crucial factor that must be considered when designing and fabricating any sensor. It is essential to test the material used in the sensor to assess the reliability of the complete product. In this work, we report the long-term reliability of a flexible pressure sensor mat using a carbon-impregnated polymer, velostat, which is a flexible, light, and thin polymer composite material with piezoresistive properties. We focus on the analysis of the performance of a flexible pressure sensor array under long-term and repeated loading. Tests were performed every fortnight for 210 days. We have observed that the material characteristics of the velostat material change on repeated application of pressure up to a certain time frame. For a given loading, once the material settles, the change in resistance of the material becomes consistent for a given application of pressure. We have also analyzed the changes in the parameters associated with the 2-parameter model, and have analyzed the effect of crosstalk on the sensor matrix for different pitch lengths to select the best pitch that will give us the minimum crosstalk. We have observed that the error rate of the sensor pixels decreased by 53 percentage points in 210 days. The results obtained from the experimental tests for reliability reveal a practical possibility of implementing velostat-based pressure sensors in wearable and healthcare devices and provide steps to take while calibrating an as-fabricated velostat-based sensor.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-07DOI: 10.1109/TDMR.2023.3340426
Jaber Al Rashid;Mohsen Koohestani;Laurent Saintis;Mihaela Barreau
This paper presents an approach to develop degradation and reliability models of analog integrated circuit (IC) voltage regulators based on the long-term evolution of the electromagnetic compatibility (EMC) performance degradation due to the stress time-dependent accelerated degradation test (ADT). The ADT plan is designed and conducted on six samples of both UA78L05 and L78L05 ICs placed inside a climatic chamber combining both the thermal step-stress (i.e., 70-110 °C) and constant electrical overstress (i.e., 9 and 12 V) conditions for a total stress duration of 950 hours. All the selected UA78L05 and L78L05 samples are subjected to the direct power injection (DPI) measurement test under nominal conditions in order to characterize their immunity to electromagnetic interference (EMI). The statistical degradation data (i.e., the average injected power) of the aged samples is computed across the entire DPI frequency range for a variety of stress time duration. The proposed log-linear accelerated life-stress test (ALT) model is combined with the Weibull unreliability distribution function model to estimate the failure lifetime data against the applied voltage stress at three different failure threshold criterion. At various constant voltage overstress and threshold constraints, the lifetime reliability performance parameters (i.e., time-to-failure, probability of failure, model constants) of the tested device under tests (DUTs) were evaluated based on the measured degradation data. It is demonstrated that, for a limited number of samples under the combined influence of thermal step-stress with voltage overstress conditions, the proposed reliability model predicts with a very acceptable accuracy the lifetime reliability of both UA78L05 and L78L05 tested ICs, developed based on the conducted immunity degradation data. The physics-based modeling approach is utilized to develop the model for the degradation paths based on the observed monotonic degradation of the measured degradation data as well as the conditions of the thermal step-stress ADT. In order to estimate the unknown parameters of the developed degradation model, the maximum likelihood estimation (MLE) method is combined with a genetic optimisation algorithm.
{"title":"Degradation and Reliability Modeling of EM Robustness of Voltage Regulators Based on ADT: An Approach and a Case Study","authors":"Jaber Al Rashid;Mohsen Koohestani;Laurent Saintis;Mihaela Barreau","doi":"10.1109/TDMR.2023.3340426","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340426","url":null,"abstract":"This paper presents an approach to develop degradation and reliability models of analog integrated circuit (IC) voltage regulators based on the long-term evolution of the electromagnetic compatibility (EMC) performance degradation due to the stress time-dependent accelerated degradation test (ADT). The ADT plan is designed and conducted on six samples of both UA78L05 and L78L05 ICs placed inside a climatic chamber combining both the thermal step-stress (i.e., 70-110 °C) and constant electrical overstress (i.e., 9 and 12 V) conditions for a total stress duration of 950 hours. All the selected UA78L05 and L78L05 samples are subjected to the direct power injection (DPI) measurement test under nominal conditions in order to characterize their immunity to electromagnetic interference (EMI). The statistical degradation data (i.e., the average injected power) of the aged samples is computed across the entire DPI frequency range for a variety of stress time duration. The proposed log-linear accelerated life-stress test (ALT) model is combined with the Weibull unreliability distribution function model to estimate the failure lifetime data against the applied voltage stress at three different failure threshold criterion. At various constant voltage overstress and threshold constraints, the lifetime reliability performance parameters (i.e., time-to-failure, probability of failure, model constants) of the tested device under tests (DUTs) were evaluated based on the measured degradation data. It is demonstrated that, for a limited number of samples under the combined influence of thermal step-stress with voltage overstress conditions, the proposed reliability model predicts with a very acceptable accuracy the lifetime reliability of both UA78L05 and L78L05 tested ICs, developed based on the conducted immunity degradation data. The physics-based modeling approach is utilized to develop the model for the degradation paths based on the observed monotonic degradation of the measured degradation data as well as the conditions of the thermal step-stress ADT. In order to estimate the unknown parameters of the developed degradation model, the maximum likelihood estimation (MLE) method is combined with a genetic optimisation algorithm.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-07DOI: 10.1109/TDMR.2023.3340231
Toshihiro Kuge;Masataka Yahagi;Junichi Koike
The intermetallic compound CuAl2 is a promising alternative to advanced Cu interconnections because of low electrical resistivity, short electron mean free path, good electromigration reliability, and good gap-filling property. In this study, to further examine the feasibility of CuAl2 interconnects for future technology node, a comprehensive study of the time-dependent dielectric breakdown (TDDB) was conducted on CuAl2 and compared with NiAl and Cu/TaN. The self-formation of a proper thickness of an AlOx interface layer by reaction with SiO2 brought about excellent TDDB reliability in CuAl2/SiO2. Voltage ramp test was also carried out to understand the electron transport mechanism in CuAl2 stressed under the same condition as that of the TDDB test. Leakage current versus voltage relation revealed the Cu ion drift into SiO2, which gave rise to Schottky emission as an electron transport mechanism across SiO2 and the accumulation of Cu ions eventually led to TDDB failure.
{"title":"A Comprehensive Evaluation of Time-Dependent Dielectric Breakdown of CuAl₂ on SiO₂ for Advanced Interconnect Application","authors":"Toshihiro Kuge;Masataka Yahagi;Junichi Koike","doi":"10.1109/TDMR.2023.3340231","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340231","url":null,"abstract":"The intermetallic compound CuAl2 is a promising alternative to advanced Cu interconnections because of low electrical resistivity, short electron mean free path, good electromigration reliability, and good gap-filling property. In this study, to further examine the feasibility of CuAl2 interconnects for future technology node, a comprehensive study of the time-dependent dielectric breakdown (TDDB) was conducted on CuAl2 and compared with NiAl and Cu/TaN. The self-formation of a proper thickness of an AlOx interface layer by reaction with SiO2 brought about excellent TDDB reliability in CuAl2/SiO2. Voltage ramp test was also carried out to understand the electron transport mechanism in CuAl2 stressed under the same condition as that of the TDDB test. Leakage current versus voltage relation revealed the Cu ion drift into SiO2, which gave rise to Schottky emission as an electron transport mechanism across SiO2 and the accumulation of Cu ions eventually led to TDDB failure.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The junctionless multi-nanowire (JL-MNW) gate-all-around (GAA) field-effect transistor (FET) has become an emerging device in the advanced node of modern semiconductor devices because of its inherent operational mechanism properties. Therefore, in this paper, the Sentaurus TCAD simulator is calibrated with a compact thermal conductivity model using experimentally measured I-V characteristic data of JL-MNW GAA FET and electro-thermal characteristics of the experimental device are mapped into the contour plots. The non-uniform lattice temperature distribution is observed in an experimental device, and the change of peak lattice temperature $(Delta text{T}~_{mathrm{ L,,max}}$ ) is linearly increased with DC power. Further, in the sub-5nm technology node, the self-heating effect (SHE) is analyzed with variations of device active areas, such as vertical nanowire stacking and poly gate thickness (TP) between two nanowires in a DC operation. This work reveals that the device’s physical parameter variation affects overall performance in sub-5 nm technology nodes, such as ON-current (ION) degradation and delay time. But its thermal reliability is better than the inversion mode GAA FET, such as the peak of lattice temperature (T $_{mathrm{ L,,max}}$ ) and thermal resistance (RTH). These are extensively investigated using the Figure of Merit (FoM). Furthermore, the thermal reliability of the experimental device and advanced node JL-MNW GAA FETs are also analyzed in terms of hot carrier injection (HCI) lifetime and bias temperature instability (BTI) lifetime degradation with respect to the $text{T}_{mathrm{ L,max}}$ and TP. Considering these results, the junctionless device is expected to be an attractive candidate to improve the performance and reliability in advanced nodes simultaneously.
{"title":"Self-Heating Mapping of the Experimental Device and Its Optimization in Advance Sub-5 nm Node Junctionless Multi-Nanowire FETs","authors":"Nitish Kumar;Shraddha Pali;Ankur Gupta;Pushpapraj Singh","doi":"10.1109/TDMR.2023.3340032","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3340032","url":null,"abstract":"The junctionless multi-nanowire (JL-MNW) gate-all-around (GAA) field-effect transistor (FET) has become an emerging device in the advanced node of modern semiconductor devices because of its inherent operational mechanism properties. Therefore, in this paper, the Sentaurus TCAD simulator is calibrated with a compact thermal conductivity model using experimentally measured I-V characteristic data of JL-MNW GAA FET and electro-thermal characteristics of the experimental device are mapped into the contour plots. The non-uniform lattice temperature distribution is observed in an experimental device, and the change of peak lattice temperature \u0000<inline-formula> <tex-math>$(Delta text{T}~_{mathrm{ L,,max}}$ </tex-math></inline-formula>\u0000) is linearly increased with DC power. Further, in the sub-5nm technology node, the self-heating effect (SHE) is analyzed with variations of device active areas, such as vertical nanowire stacking and poly gate thickness (TP) between two nanowires in a DC operation. This work reveals that the device’s physical parameter variation affects overall performance in sub-5 nm technology nodes, such as ON-current (ION) degradation and delay time. But its thermal reliability is better than the inversion mode GAA FET, such as the peak of lattice temperature (T \u0000<inline-formula> <tex-math>$_{mathrm{ L,,max}}$ </tex-math></inline-formula>\u0000) and thermal resistance (RTH). These are extensively investigated using the Figure of Merit (FoM). Furthermore, the thermal reliability of the experimental device and advanced node JL-MNW GAA FETs are also analyzed in terms of hot carrier injection (HCI) lifetime and bias temperature instability (BTI) lifetime degradation with respect to the \u0000<inline-formula> <tex-math>$text{T}_{mathrm{ L,max}}$ </tex-math></inline-formula>\u0000 and TP. Considering these results, the junctionless device is expected to be an attractive candidate to improve the performance and reliability in advanced nodes simultaneously.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3338877
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TDMR.2023.3338877","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3338877","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346022","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-06DOI: 10.1109/TDMR.2023.3336491
{"title":"Blank Page","authors":"","doi":"10.1109/TDMR.2023.3336491","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3336491","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":null,"pages":null},"PeriodicalIF":2.0,"publicationDate":"2023-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10346027","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138502159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：