In this study, an amorphous p-type N-doped Ga2O3 thin film has been achieved using pulsed laser deposition and Ga2O3:GaN=1:1 (at%) mixed ceramic target. The bonding states of the films after nitrogen incorporation were investigated using X-ray photoelectron spectroscopy, which revealed the lattice oxygen sites substituted by nitrogen. Ultraviolet photoelectron spectroscopy analysis shows a p-type feature of N-doped Ga2O3 film and a weak n-type unintentional doped pure Ga2O3 film. The thin film transistors have been fabricated using pure and N-doped Ga2O3 films to further confirm their n-type and p-type conductive properties, respectively. The N-doped Ga2O3-based TFTs displays p-type characteristics with a field effect mobility of $2.13times 10{^{text {-3}}}$ cm2/V$cdot $ s, an on/off ratio of $2.78times 10{^{{4}}}$ and a sub-threshold swing of 0.15 V/dec. Finally, a full amorphous Ga2O3 films-based pn homojunction diode has been fulfilled and explored in detail, which displays a good rectifying characteristic with a rectification ratio of $1.46times 10{^{{2}}}$ and an ideality factor of 5.19.
{"title":"The Achievement of Pulse Laser Deposited Amorphous P-Type N-Doped Ga₂O₃ for Applying in Thin Film Transistor and Homojunction Diode","authors":"Teng-Min Fan;Chen Wang;Cong Yi;Chen-Hao Zhou;Yu-Li Su;Yun-Shao Cho;Dong-Sing Wuu;Shui-Yang Lien","doi":"10.1109/TDMR.2025.3559225","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3559225","url":null,"abstract":"In this study, an amorphous p-type N-doped Ga2O3 thin film has been achieved using pulsed laser deposition and Ga2O3:GaN=1:1 (at%) mixed ceramic target. The bonding states of the films after nitrogen incorporation were investigated using X-ray photoelectron spectroscopy, which revealed the lattice oxygen sites substituted by nitrogen. Ultraviolet photoelectron spectroscopy analysis shows a p-type feature of N-doped Ga2O3 film and a weak n-type unintentional doped pure Ga2O3 film. The thin film transistors have been fabricated using pure and N-doped Ga2O3 films to further confirm their n-type and p-type conductive properties, respectively. The N-doped Ga2O3-based TFTs displays p-type characteristics with a field effect mobility of <inline-formula> <tex-math>$2.13times 10{^{text {-3}}}$ </tex-math></inline-formula> cm2/V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s, an on/off ratio of <inline-formula> <tex-math>$2.78times 10{^{{4}}}$ </tex-math></inline-formula> and a sub-threshold swing of 0.15 V/dec. Finally, a full amorphous Ga2O3 films-based pn homojunction diode has been fulfilled and explored in detail, which displays a good rectifying characteristic with a rectification ratio of <inline-formula> <tex-math>$1.46times 10{^{{2}}}$ </tex-math></inline-formula> and an ideality factor of 5.19.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"281-287"},"PeriodicalIF":2.5,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-07DOI: 10.1109/TDMR.2025.3558283
Fengchuan Wang;Cheng Chen;Zhihao Ye;Qikai Fang;Gang Yang
Wireless power transmission (WPT) technology is rapidly evolving and promising. However, its system is prone to fault due to aging and failure of power electronic devices, so the study of effective fault diagnosis and prediction methods is crucial for stable operation of the system. In this paper, the external aging output characteristics of typical devices in WPT system are firstly introduced. Secondly, the existing fault diagnosis methods of WPT system and the typical power electronics fault diagnosis and prediction methods that can be learned from are reviewed, while the application of these methods in WPT system is evaluated. Finally, the future development trend of WPT fault diagnosis and prediction technology is outlooked.
{"title":"Magnetically Coupled Resonant Wireless Power Transmission System: A Review of Fault Diagnosis Methods","authors":"Fengchuan Wang;Cheng Chen;Zhihao Ye;Qikai Fang;Gang Yang","doi":"10.1109/TDMR.2025.3558283","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3558283","url":null,"abstract":"Wireless power transmission (WPT) technology is rapidly evolving and promising. However, its system is prone to fault due to aging and failure of power electronic devices, so the study of effective fault diagnosis and prediction methods is crucial for stable operation of the system. In this paper, the external aging output characteristics of typical devices in WPT system are firstly introduced. Secondly, the existing fault diagnosis methods of WPT system and the typical power electronics fault diagnosis and prediction methods that can be learned from are reviewed, while the application of these methods in WPT system is evaluated. Finally, the future development trend of WPT fault diagnosis and prediction technology is outlooked.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"180-188"},"PeriodicalIF":2.5,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive study on the relation between die-attach and thermal/electrical parameters of GaN RF devices. This correlation is investigated through Multiphysics simulations and experimental data. Particularly, thermal analysis is performed by means of Quantum Focus Instrument (QFI) Infrascope able to detect the surface temperature of the device. Then, 3-D finite element method thermal simulations are performed to support the observed heat distribution. A strong association between drain current drift and temperature escalation is demonstrated by comparing two devices with significantly different die-attaches. Particularly, we observe an increase in the drain current with increasing self-heating effects, conversely to what generally expected for thermal derating. However, this correlation is then explained thanks to the analysis of threshold voltage shift with temperature that supports the experimental evidence.
{"title":"Die-Attach Influence on Thermal/Electrical Parameters of GaN RF Device","authors":"Giacomo Cappellini;Giuseppe D’Arrigo;Viviana Cerantonio;Marcello Cioni;Alessandro Chini;Sonia Zappala;Simone Strano;Leonardo Gervasi;Marcello Giuffrida;Cristina Miccoli;Cristina Tringali;Maria Eloisa Castagna;Ferdinando Iucolano","doi":"10.1109/TDMR.2025.3556383","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3556383","url":null,"abstract":"This paper presents a comprehensive study on the relation between die-attach and thermal/electrical parameters of GaN RF devices. This correlation is investigated through Multiphysics simulations and experimental data. Particularly, thermal analysis is performed by means of Quantum Focus Instrument (QFI) Infrascope able to detect the surface temperature of the device. Then, 3-D finite element method thermal simulations are performed to support the observed heat distribution. A strong association between drain current drift and temperature escalation is demonstrated by comparing two devices with significantly different die-attaches. Particularly, we observe an increase in the drain current with increasing self-heating effects, conversely to what generally expected for thermal derating. However, this correlation is then explained thanks to the analysis of threshold voltage shift with temperature that supports the experimental evidence.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"308-313"},"PeriodicalIF":2.5,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low $C_{mathrm { gd}}$ . During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum $dI_{mathrm { D}}$ /dt and 44.1% reduction in overshoot voltage $(V_{mathrm { O}})$ with same $E_{mathrm { off}}$ , reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.
{"title":"A Novel Dual-Mode Dual Trench MOSFET With Self-Adjustable Field Plate for Low EMI Noise and High Dynamic Avalanche Robustness","authors":"Tongyang Wang;Zehong Li;Yishang Zhao;Ziming Xia;Yige Zheng;Jun Ye;Xuan Xiao","doi":"10.1109/TDMR.2025.3556015","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3556015","url":null,"abstract":"A novel dual-mode dual trench MOSFET (DDT-MOSFET) featuring shorted P-doping field plate (PFP) and N-doping field plate (NFP) is proposed. A parasitic depletion region capacitor and a parasitic MOSFET are introduced in the self-adjustable field plate (SFP). During turn-on, the DDT-MOSFET is in the split gate trench (SGT) mode with an electron inversion layer in the PFP, achieving low <inline-formula> <tex-math>$C_{mathrm { gd}}$ </tex-math></inline-formula>. During turn-off, the DDT-MOSFET is in the insulator pillar superjunction (I-SJ) mode with depleted PFP, achieving low electromagnetic interference (EMI) noise and high breakdown voltage (BV). Mode conversion is realized by the introduction of the SFP. By TCAD simulation, during turn-off, the proposed structure exhibits 33.9% improvement in BV, 42.8% reduction in maximum <inline-formula> <tex-math>$dI_{mathrm { D}}$ </tex-math></inline-formula>/dt and 44.1% reduction in overshoot voltage <inline-formula> <tex-math>$(V_{mathrm { O}})$ </tex-math></inline-formula> with same <inline-formula> <tex-math>$E_{mathrm { off}}$ </tex-math></inline-formula>, reducing EMI noise and improving dynamic avalanche robustness without deterioration of other electrical characteristics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"274-280"},"PeriodicalIF":2.5,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hot carrier injection (HCI) has been strategically leveraged to enhance the stability of SRAM physically unclonable functions (PUFs). Since the effects of HCI are not constant, exhibiting cell-to-cell variability, a comprehensive distribution model is essential to harness HCI effectively. This article presents a statistical distribution model of mismatch after HCI burn-in and examines the impact of transistor size of PUF on the distribution shape, yielding enhanced stability and shorter HCI burn-in time. The proposed mismatch model after HCI burn-in integrates the native distribution with a Poisson distribution for number of captured electrons and a Gamma distribution for the effect of captured electrons. Model calculations based on size effects reveal that over three times reduction in HCI burn-in duration by enhancing the size to quadruple times: a 15-min for quadruple-size transistor SRAM PUF compared to 46-min for single-size PUF. The model is confirmed by the real chip measurement. The PUFs with several sized transistors are fabricated in a 130-nm standard CMOS process. Experimental results show that quadruple-size transistor SRAM PUF reaches 1.82E−09 unstable cell ratio after 18-min HCI burn-in, which align with the model based expectation. Furthermore, robust stability is exhibited even the worst VT corner (0.6V / $-40^{circ }mathrm {C}$ ), demonstrating zero bit error (BER<7.81E−08).
热载流子注入（HCI）已被战略性地用于提高SRAM物理不可克隆功能（puf）的稳定性。由于HCI的影响不是恒定的，表现出细胞间的可变性，因此一个全面的分布模型对于有效利用HCI至关重要。本文提出了HCI老化后失配的统计分布模型，并研究了PUF晶体管尺寸对分布形状的影响，从而提高了稳定性和缩短了HCI老化时间。提出的HCI老化后失配模型将捕获电子数的泊松分布和捕获电子效应的伽玛分布与自然分布相结合。基于尺寸效应的模型计算表明，通过将尺寸增加到四倍，HCI烧蚀时间减少了三倍以上：四尺寸晶体管SRAM PUF为15分钟，而单尺寸PUF为46分钟。该模型通过实际芯片测量得到了验证。puf具有多个尺寸的晶体管，采用130纳米标准CMOS工艺制造。实验结果表明，经过18 min HCI老化后，四倍尺寸晶体管SRAM PUF达到1.82 2e−09的不稳定电池比，符合基于模型的预期。此外，即使在最坏的VT角（0.6V / $-40^{circ} maththrm {C}$），也表现出鲁棒的稳定性，显示零比特误差（BER<7.81E−08）。
{"title":"Statistical Model and Transistor Size Effect of Hot Carrier Injection for Stability Reinforced SRAM Physically Unclonable Function","authors":"Shufan Xu;Kunyang Liu;Kiichi Niitsu;Hirofumi Shinohara","doi":"10.1109/TDMR.2025.3574796","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574796","url":null,"abstract":"Hot carrier injection (HCI) has been strategically leveraged to enhance the stability of SRAM physically unclonable functions (PUFs). Since the effects of HCI are not constant, exhibiting cell-to-cell variability, a comprehensive distribution model is essential to harness HCI effectively. This article presents a statistical distribution model of mismatch after HCI burn-in and examines the impact of transistor size of PUF on the distribution shape, yielding enhanced stability and shorter HCI burn-in time. The proposed mismatch model after HCI burn-in integrates the native distribution with a Poisson distribution for number of captured electrons and a Gamma distribution for the effect of captured electrons. Model calculations based on size effects reveal that over three times reduction in HCI burn-in duration by enhancing the size to quadruple times: a 15-min for quadruple-size transistor SRAM PUF compared to 46-min for single-size PUF. The model is confirmed by the real chip measurement. The PUFs with several sized transistors are fabricated in a 130-nm standard CMOS process. Experimental results show that quadruple-size transistor SRAM PUF reaches 1.82E−09 unstable cell ratio after 18-min HCI burn-in, which align with the model based expectation. Furthermore, robust stability is exhibited even the worst VT corner (0.6V / <inline-formula> <tex-math>$-40^{circ }mathrm {C}$ </tex-math></inline-formula>), demonstrating zero bit error (BER<7.81E−08).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"481-491"},"PeriodicalIF":2.3,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11017744","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-29DOI: 10.1109/TDMR.2025.3574776
Mattia Rossetti;Laura Atzeni;Rita Zappa
Instability phenomena in dense one-time-programmable memories based on the breakdown of ultra-thin silicon dioxide layers are discussed. During stress at programming condition, cell IV characteristics are found to evolve between quasi-linear and highly non-linear characteristics. Extensive characterization of this instability is carried on as a function of stress duration and programming conditions to maximize post-breakdown current and guarantee values above the program-verify threshold. Read current instability is also observed during reading cycles and associated to a switching behavior between two or more states of the breakdown path that has been minimized by a proper cell design. Post-breakdown IV characteristics of the OTP cell are modeled based on the quantum-point contact model. Peculiar temperature dependence of the IV characteristics of programmed cells is nicely described by the proposed model.
{"title":"Post-Breakdown IV Characteristics and Instabilities in Dense OTP Anti-Fuse Memories","authors":"Mattia Rossetti;Laura Atzeni;Rita Zappa","doi":"10.1109/TDMR.2025.3574776","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574776","url":null,"abstract":"Instability phenomena in dense one-time-programmable memories based on the breakdown of ultra-thin silicon dioxide layers are discussed. During stress at programming condition, cell IV characteristics are found to evolve between quasi-linear and highly non-linear characteristics. Extensive characterization of this instability is carried on as a function of stress duration and programming conditions to maximize post-breakdown current and guarantee values above the program-verify threshold. Read current instability is also observed during reading cycles and associated to a switching behavior between two or more states of the breakdown path that has been minimized by a proper cell design. Post-breakdown IV characteristics of the OTP cell are modeled based on the quantum-point contact model. Peculiar temperature dependence of the IV characteristics of programmed cells is nicely described by the proposed model.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"610-616"},"PeriodicalIF":2.3,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-28DOI: 10.1109/TDMR.2025.3574447
Erwan Basiron;Adlil Aizat Ismail;Azman Jalar;Maria Abu Bakar;Azman Ahmad
In the realm of electronic device manufacturing, one persistent challenge is the lack of a universal TCT (Temperature Cycle Test) solder joints crack assessment that is suitable for all types of electronic components. This gap becomes particularly complex when multiple components are assembled into a single board. Therefore, this paper proposed an approach by normalizing the solder joints cracks, index $eta $ value as benchmarking value for solder joint cracks in components following TCT. This work used four types of components include controller, NAND, double data rate random-access memory (DDR-RAM) and power management integrated circuit (PMIC). All of these components subjected to three different TCT conditions (A) −40 to $85~{^{^{circ }} }$ C, 10 mins soak, 12.5 mins ramp, 500 cycles, (B) 0 to $100~{^{^{circ }} }$ C, 15 mins soak, 15 mins ramp, 750 cycles and (C) 0 to $100~{^{^{circ }} }$ C, 15 mins soak, 15 mins ramp, 900 cycles to determine relative severity of the SSD design, and its critical components solder joint performance. Solder joints crack percentage is calculated from inspection post DnP and analysed to compare the severity. The normalize solder joints, index $mathrm {{eta } }$ were calculated and used to analyse all the components post TCT. It was found that TCT profile C is more stringent with solder joint cracks $4.1x$ higher than TCT profile A and $2.5mathrm { x}$ higher than TCT profile B. The highest index $eta $ value of 5.2 from TCT profile C indicates that it is the most stringent of all tested TCT profiles, compared to TCT profile B at 2.67 and TCT profile A at 1.13. The findings from this study provide valuable insights into selecting effective TCT profiles, allowing for optimized testing procedures that save time and resources. This approach is particularly beneficial for specific components, including controller, NAND, DDR-RAM and PMIC packages. Furthermore, normalizing solder joint cracks using the index $eta $ value as a benchmarking metric can be applied to other types of electronic components.
{"title":"Board Level-Component Solder Joints Normalized Crack Severity Index of Solid-State Drive With Different Reliability Temperature Cycle Test Profiles","authors":"Erwan Basiron;Adlil Aizat Ismail;Azman Jalar;Maria Abu Bakar;Azman Ahmad","doi":"10.1109/TDMR.2025.3574447","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574447","url":null,"abstract":"In the realm of electronic device manufacturing, one persistent challenge is the lack of a universal TCT (Temperature Cycle Test) solder joints crack assessment that is suitable for all types of electronic components. This gap becomes particularly complex when multiple components are assembled into a single board. Therefore, this paper proposed an approach by normalizing the solder joints cracks, index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value as benchmarking value for solder joint cracks in components following TCT. This work used four types of components include controller, NAND, double data rate random-access memory (DDR-RAM) and power management integrated circuit (PMIC). All of these components subjected to three different TCT conditions (A) −40 to <inline-formula> <tex-math>$85~{^{^{circ }} }$ </tex-math></inline-formula>C, 10 mins soak, 12.5 mins ramp, 500 cycles, (B) 0 to <inline-formula> <tex-math>$100~{^{^{circ }} }$ </tex-math></inline-formula>C, 15 mins soak, 15 mins ramp, 750 cycles and (C) 0 to <inline-formula> <tex-math>$100~{^{^{circ }} }$ </tex-math></inline-formula>C, 15 mins soak, 15 mins ramp, 900 cycles to determine relative severity of the SSD design, and its critical components solder joint performance. Solder joints crack percentage is calculated from inspection post DnP and analysed to compare the severity. The normalize solder joints, index <inline-formula> <tex-math>$mathrm {{eta } }$ </tex-math></inline-formula>were calculated and used to analyse all the components post TCT. It was found that TCT profile C is more stringent with solder joint cracks <inline-formula> <tex-math>$4.1x$ </tex-math></inline-formula> higher than TCT profile A and <inline-formula> <tex-math>$2.5mathrm { x}$ </tex-math></inline-formula> higher than TCT profile B. The highest index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value of 5.2 from TCT profile C indicates that it is the most stringent of all tested TCT profiles, compared to TCT profile B at 2.67 and TCT profile A at 1.13. The findings from this study provide valuable insights into selecting effective TCT profiles, allowing for optimized testing procedures that save time and resources. This approach is particularly beneficial for specific components, including controller, NAND, DDR-RAM and PMIC packages. Furthermore, normalizing solder joint cracks using the index <inline-formula> <tex-math>$eta $ </tex-math></inline-formula> value as a benchmarking metric can be applied to other types of electronic components.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"473-480"},"PeriodicalIF":2.3,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increasing demand for emerging technologies like artificial intelligence and big data, the significance of advanced chip integration and packaging has grown considerably. Sn-Bi based solders have gained significant attention and have been explored for multi-layer stacked packaging, but they are prone to significant coarsening during service, and the effects of grain and phase anisotropy become more pronounced. These factors impact the performance and reliability of Sn-Bi solder interconnects. This study develops a numerical model to investigate microstructure coarsening in Sn-Bi solder bump interconnects, focusing on its effect on mechanical behavior and crack propagation. The simulated coarsening behavior aligns with experimental observations. Results show that, under shear loading, the Sn-rich phase experiences higher stress initially, while the Bi-rich phase bears greater stress later, leading to stress concentrations mainly in the Bi-rich phase or at the phase interfaces. Thermal aging exacerbates the uneven distribution of stress. Plastic strain is greater in the Sn-rich phase, and cracks primarily initiate and propagate in the Bi-rich phase. Coarsening accelerates crack growth, affecting the stress-strain response. This study provides insights into the effects of phase coarsening and inhomogeneous deformation in Sn-Bi solder interconnects, which may contribute to interconnect design and reliability analysis in three-dimensional packaging.
{"title":"Influence of Phase Coarsening on Inhomogeneous Deformation and Fracture Behavior in Sn–Bi Solder Interconnects","authors":"Shuibao Liang;Han Jiang;Zhihong Zhong;Yaohua Xu;Saranarayanan Ramachandran","doi":"10.1109/TDMR.2025.3574560","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3574560","url":null,"abstract":"With the increasing demand for emerging technologies like artificial intelligence and big data, the significance of advanced chip integration and packaging has grown considerably. Sn-Bi based solders have gained significant attention and have been explored for multi-layer stacked packaging, but they are prone to significant coarsening during service, and the effects of grain and phase anisotropy become more pronounced. These factors impact the performance and reliability of Sn-Bi solder interconnects. This study develops a numerical model to investigate microstructure coarsening in Sn-Bi solder bump interconnects, focusing on its effect on mechanical behavior and crack propagation. The simulated coarsening behavior aligns with experimental observations. Results show that, under shear loading, the Sn-rich phase experiences higher stress initially, while the Bi-rich phase bears greater stress later, leading to stress concentrations mainly in the Bi-rich phase or at the phase interfaces. Thermal aging exacerbates the uneven distribution of stress. Plastic strain is greater in the Sn-rich phase, and cracks primarily initiate and propagate in the Bi-rich phase. Coarsening accelerates crack growth, affecting the stress-strain response. This study provides insights into the effects of phase coarsening and inhomogeneous deformation in Sn-Bi solder interconnects, which may contribute to interconnect design and reliability analysis in three-dimensional packaging.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"585-593"},"PeriodicalIF":2.3,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-26DOI: 10.1109/TDMR.2025.3573599
Yi Wang;Jiahao Yin;Yaohua Xu;Chunmei Hu
The complex architecture of double interlocked storage cell (DICE) static random access memories (SRAM), which consists of 12 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), presents challenges in manufacturing test. Manufacturing defects can cause faults in DICE SRAMs, and undetected faults may lead to test escapes, resulting in early in-field failures. These issues can prevent DICE SRAMs from meeting the applications requiring high quality in sectors such as aerospace. This paper proposes a new type of SEU fault for DICE SRAM, analyzing how physical defects influence its SEU resilience, which forms a new fault space together with parameter faults and functional faults.This paper presents a detailed analysis and fault modeling of resistive defects that may occur in DICE SRAMs and proposes a novel test algorithm to enhance fault coverage and reduce test escapes during manufacturing test. First, we define and classify the fault space, including functional faults, parameter faults, and single event upset (SEU) faults, and outline the methodology to validate faults within this space. Next, we inject resistive defects into the SPICE netlist of DICE SRAMs, conduct SPICE simulation, and inspect its corresponding behavior. Furthermore, through the analysis of the fault modeling results of DICE SRAMs and evaluating the test coverage and limitations of existing test solutions, we propose a new test algorithm. This results in a substantial increase in dynamic fault coverage from 20.57% to 28.37% and an overall improvement in fault coverage from 33.88% to 39.89% when compared to the March C+ algorithm, while reducing the possibility of test escape for parameter faults (including HSNM and RSNM faults) and SEU faults. In summary, the findings of the paper are effective in detecting the realistic faults in DICE SRAMs, thereby bolstering the effectiveness of DICE SRAMs test for critical applications.
{"title":"Resistive Defect Analysis and Fault Modeling of DICE Memory in Commercial 40-nm CMOS Technology","authors":"Yi Wang;Jiahao Yin;Yaohua Xu;Chunmei Hu","doi":"10.1109/TDMR.2025.3573599","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3573599","url":null,"abstract":"The complex architecture of double interlocked storage cell (DICE) static random access memories (SRAM), which consists of 12 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), presents challenges in manufacturing test. Manufacturing defects can cause faults in DICE SRAMs, and undetected faults may lead to test escapes, resulting in early in-field failures. These issues can prevent DICE SRAMs from meeting the applications requiring high quality in sectors such as aerospace. This paper proposes a new type of SEU fault for DICE SRAM, analyzing how physical defects influence its SEU resilience, which forms a new fault space together with parameter faults and functional faults.This paper presents a detailed analysis and fault modeling of resistive defects that may occur in DICE SRAMs and proposes a novel test algorithm to enhance fault coverage and reduce test escapes during manufacturing test. First, we define and classify the fault space, including functional faults, parameter faults, and single event upset (SEU) faults, and outline the methodology to validate faults within this space. Next, we inject resistive defects into the SPICE netlist of DICE SRAMs, conduct SPICE simulation, and inspect its corresponding behavior. Furthermore, through the analysis of the fault modeling results of DICE SRAMs and evaluating the test coverage and limitations of existing test solutions, we propose a new test algorithm. This results in a substantial increase in dynamic fault coverage from 20.57% to 28.37% and an overall improvement in fault coverage from 33.88% to 39.89% when compared to the March C+ algorithm, while reducing the possibility of test escape for parameter faults (including HSNM and RSNM faults) and SEU faults. In summary, the findings of the paper are effective in detecting the realistic faults in DICE SRAMs, thereby bolstering the effectiveness of DICE SRAMs test for critical applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"510-519"},"PeriodicalIF":2.3,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-24DOI: 10.1109/TDMR.2025.3554369
Lisheng Wang;Gert Rietveld;Raymond J. E. Hueting
Silver (Ag) sintering is becoming more critical for future wide bandgap (WBG) power module substrate attachments. However, sintered Ag joints with plated aluminum (Al) heatsinks and directly bonded aluminum (DBA) substrates presently suffer from poor reliability. To resolve this problem, this work studies the reliability of plated (Nickel) Ni/Ag metallization on Al for sintered Ag joints and proposes a new plated Ni/Copper (Cu)/Ag metallization stack for improved reliability. The shear strength and thermal shock (TS) reliability of the sintered Ag joints for different metallization layers are studied, and microstructural and elemental analyses were performed to analyze the failure modes. The results show that the reliability of the sintered Ag joints by the traditional Ni/Ag metallization is rather limited because of poor adhesion between Ni and Ag. In contrast, the shear strength of the new Ni/Cu/Ag metallized sintered Ag joints is consistently above 40 MPa up to 500 TS cycles, with the dominant failure modes formed by Al/Ni delamination and cohesive failure. Preparing sintered Ag joints with the Ni/Cu/Ag metallization with longer sintering times removed the unwanted delamination failure mode and only left the preferred cohesive failure mode; moreover, the shear strength improved significantly, with values reaching 130 MPa. Furthermore, a new failure mode appears in the sintered Ag joint of the Ni/Cu/Ag stack, implying that the Al/Ni metallization weakness there is less of a limiting factor. This proves that our new metallization stack resolves present delamination issues in Ag sintered joints with Al heatsinks and DBA substrates and thereby supports exploiting the full potential of sintered Ag joints.
{"title":"Thermal Shock Reliability of Silver-Sintered Bonding of Metal-Plated Aluminum Surfaces","authors":"Lisheng Wang;Gert Rietveld;Raymond J. E. Hueting","doi":"10.1109/TDMR.2025.3554369","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3554369","url":null,"abstract":"Silver (Ag) sintering is becoming more critical for future wide bandgap (WBG) power module substrate attachments. However, sintered Ag joints with plated aluminum (Al) heatsinks and directly bonded aluminum (DBA) substrates presently suffer from poor reliability. To resolve this problem, this work studies the reliability of plated (Nickel) Ni/Ag metallization on Al for sintered Ag joints and proposes a new plated Ni/Copper (Cu)/Ag metallization stack for improved reliability. The shear strength and thermal shock (TS) reliability of the sintered Ag joints for different metallization layers are studied, and microstructural and elemental analyses were performed to analyze the failure modes. The results show that the reliability of the sintered Ag joints by the traditional Ni/Ag metallization is rather limited because of poor adhesion between Ni and Ag. In contrast, the shear strength of the new Ni/Cu/Ag metallized sintered Ag joints is consistently above 40 MPa up to 500 TS cycles, with the dominant failure modes formed by Al/Ni delamination and cohesive failure. Preparing sintered Ag joints with the Ni/Cu/Ag metallization with longer sintering times removed the unwanted delamination failure mode and only left the preferred cohesive failure mode; moreover, the shear strength improved significantly, with values reaching 130 MPa. Furthermore, a new failure mode appears in the sintered Ag joint of the Ni/Cu/Ag stack, implying that the Al/Ni metallization weakness there is less of a limiting factor. This proves that our new metallization stack resolves present delamination issues in Ag sintered joints with Al heatsinks and DBA substrates and thereby supports exploiting the full potential of sintered Ag joints.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"203-211"},"PeriodicalIF":2.5,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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