Pub Date : 2024-02-16DOI: 10.1109/TDMR.2024.3366592
Nalin Vilochan Mishra;Aditya Sankar Medury
The effect of Radiation on the semiconductor-oxide interface, inducing interface trap states, has generally only been experimentally measured, which makes it difficult to quantify the impact of this radiation on device electrostatics. For an Ultra-Thin-Body (UTB) MOS device, the 1-D Band structure along the direction of confinement, if solved self-consistently with the 1-D Poisson’s equation, while varying the band edge energy $(Delta E_{edge})$ at the $Si-SiO_{2}$ interface, can enable the quantification of the effect of interface trap states on channel electrostatics, while also accounting for Quantum Confinement Effects. In this work, we present an approach to correlate the radiation dose to the band edge energy $(Delta E_{edge})$ , thus enabling the channel thickness dependent band structure-based approach to be used to quantify the effect of these radiation-induced traps on the device electrostatics. We show a methodology that co-relates the interface charge induced by $Delta E_{edge}$ variation and the charge yield, due to different radiating particles, on the $Si-SiO_{2}$ interface. After identifying appropriate values of $Delta E_{edge}$ for different particles and doses, the degradation due to radiation on the channel electrostatics can be accurately simulated, for a wide range of channel thicknesses with the atomistic band structure-based methodology. We also show an approach to extend this methodology to lower device temperatures, thus effectively quantifying the effect of radiation dose on UTB device electrostatics for a wide range of device temperatures.
{"title":"Correlation of Radiation-Induced Interface Traps With Band Edge Energy Through Band Structure-Based Analysis of Electrostatics of UTB SOI Devices","authors":"Nalin Vilochan Mishra;Aditya Sankar Medury","doi":"10.1109/TDMR.2024.3366592","DOIUrl":"10.1109/TDMR.2024.3366592","url":null,"abstract":"The effect of Radiation on the semiconductor-oxide interface, inducing interface trap states, has generally only been experimentally measured, which makes it difficult to quantify the impact of this radiation on device electrostatics. For an Ultra-Thin-Body (UTB) MOS device, the 1-D Band structure along the direction of confinement, if solved self-consistently with the 1-D Poisson’s equation, while varying the band edge energy \u0000<inline-formula> <tex-math>$(Delta E_{edge})$ </tex-math></inline-formula>\u0000 at the \u0000<inline-formula> <tex-math>$Si-SiO_{2}$ </tex-math></inline-formula>\u0000 interface, can enable the quantification of the effect of interface trap states on channel electrostatics, while also accounting for Quantum Confinement Effects. In this work, we present an approach to correlate the radiation dose to the band edge energy \u0000<inline-formula> <tex-math>$(Delta E_{edge})$ </tex-math></inline-formula>\u0000, thus enabling the channel thickness dependent band structure-based approach to be used to quantify the effect of these radiation-induced traps on the device electrostatics. We show a methodology that co-relates the interface charge induced by \u0000<inline-formula> <tex-math>$Delta E_{edge}$ </tex-math></inline-formula>\u0000 variation and the charge yield, due to different radiating particles, on the \u0000<inline-formula> <tex-math>$Si-SiO_{2}$ </tex-math></inline-formula>\u0000 interface. After identifying appropriate values of \u0000<inline-formula> <tex-math>$Delta E_{edge}$ </tex-math></inline-formula>\u0000 for different particles and doses, the degradation due to radiation on the channel electrostatics can be accurately simulated, for a wide range of channel thicknesses with the atomistic band structure-based methodology. We also show an approach to extend this methodology to lower device temperatures, thus effectively quantifying the effect of radiation dose on UTB device electrostatics for a wide range of device temperatures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"225-232"},"PeriodicalIF":2.5,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-14DOI: 10.1109/TDMR.2024.3365960
Fengkai Liu;Cuancuan Zhu;Zhongli Liu;Jianqun Yang;Yadong Wei;Yubao Zhang;Xingji Li
Hydrogen molecules in the SiO2 layer and the Si-SiO2 interface play a key role in the reliability of Si-based devices by affecting the formation of defects. This paper focuses on the effect of hydrogen molecule release on the negative bias temperature instability (NBTI) by low-temperature pre-treatment (LTPT) in p-channel power vertical-double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET). The negative bias temperature stress (NBTS) and LTPT are observed to be able to shift the threshold voltage. The number of defects is separated by the subthreshold midgap technique (SMGT). The evolution of atoms at low temperature and the formation of defects during NBTS are verified through simulation and theoretical analysis, respectively. Additionally, it is also validated by a hydrogen-soaking pre-treatment (HSPT) experiment. The LTPT makes it easier for reactive hydrogen atoms to form hydrogen molecules. This process can promote the conversion of oxide charges to interface traps during NBTS and may even exacerbate the instability. Furthermore, although LTPT has been proven to improve device performance, it is not effective in mitigating instability during NBTS. Overall, this discovery points to a superior method of reducing NBTI by decreasing hydrogen-related impurities during the manufacturing and packaging processes of p-channel power VDMOS transistors.
{"title":"Effect of Hydrogen Molecule Release on NBTI by Low-Temperature Pre-Treatment in P-Channel Power VDMOS Transistors","authors":"Fengkai Liu;Cuancuan Zhu;Zhongli Liu;Jianqun Yang;Yadong Wei;Yubao Zhang;Xingji Li","doi":"10.1109/TDMR.2024.3365960","DOIUrl":"10.1109/TDMR.2024.3365960","url":null,"abstract":"Hydrogen molecules in the SiO2 layer and the Si-SiO2 interface play a key role in the reliability of Si-based devices by affecting the formation of defects. This paper focuses on the effect of hydrogen molecule release on the negative bias temperature instability (NBTI) by low-temperature pre-treatment (LTPT) in p-channel power vertical-double-diffused metal-oxide-semiconductor field-effect transistor (VDMOSFET). The negative bias temperature stress (NBTS) and LTPT are observed to be able to shift the threshold voltage. The number of defects is separated by the subthreshold midgap technique (SMGT). The evolution of atoms at low temperature and the formation of defects during NBTS are verified through simulation and theoretical analysis, respectively. Additionally, it is also validated by a hydrogen-soaking pre-treatment (HSPT) experiment. The LTPT makes it easier for reactive hydrogen atoms to form hydrogen molecules. This process can promote the conversion of oxide charges to interface traps during NBTS and may even exacerbate the instability. Furthermore, although LTPT has been proven to improve device performance, it is not effective in mitigating instability during NBTS. Overall, this discovery points to a superior method of reducing NBTI by decreasing hydrogen-related impurities during the manufacturing and packaging processes of p-channel power VDMOS transistors.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"211-218"},"PeriodicalIF":2.5,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study aims to explore the solder fatigue lifetime of a developed high-voltage (1.7 kV/100 A) SiC power MOSFET module for on-board chargers (OBCs) subjected to power cycling test (PCT) in accordance with AQG 324. To achieve this goal, a design for reliability (DfR) methodology is established, which couples three-dimensional (3D) thermal computational fluid dynamics (CFD) analysis with 3D transient thermal-mechanical finite element analysis (FEA). The time-dependent viscoplastic behavior of the solder layer is taken into consideration in this FEA by virtue of the Anand model. In addition, a modified physical fatigue lifetime model based on Coffin-Manson formula considering the correlation between a failure criterion and a physical damage characteristic is proposed to effectively estimate the solder fatigue lifetime. The coefficients of the modified physical lifetime model are derived by curve-fitting the experimental solder fatigue lifetime data of a commercial 1.2 kV/25 A SiC power MOSFET module and the corresponding calculated equivalent strain increments using the DfR methodology. The proposed DfR methodology together with the constructed fatigue lifetime model are tested on the prediction of the solder fatigue lifetime of the developed high voltage SiC power module, and their validity are demonstrated by comparing the predicted results with the corresponding PCT experimental results. Finally, parametric analysis is performed to seek a design guideline for enhanced solder fatigue lifetime of the developed SiC power MOSFET module.
本研究旨在探索用于车载充电器（OBC）的已开发高压（1.7 kV/100 A）SiC 功率 MOSFET 模块的焊料疲劳寿命，该模块需按照 AQG 324 标准进行功率循环测试（PCT）。为实现这一目标，建立了可靠性设计 (DfR) 方法，该方法将三维热计算流体动力学 (CFD) 分析与三维瞬态热机械有限元分析 (FEA) 相结合。借助 Anand 模型，该有限元分析考虑到了焊料层随时间变化的粘塑性行为。此外，还提出了基于 Coffin-Manson 公式的修正物理疲劳寿命模型，该模型考虑了失效标准与物理损伤特征之间的相关性，可有效估算焊料疲劳寿命。修正物理寿命模型的系数是通过对商用 1.2 kV/25 A SiC 功率 MOSFET 模块的实验性焊料疲劳寿命数据和使用 DfR 方法计算出的相应等效应变增量进行曲线拟合得出的。通过将预测结果与相应的 PCT 实验结果进行比较，证明了所提出的 DfR 方法和所构建的疲劳寿命模型在预测所开发的高压 SiC 功率模块的焊料疲劳寿命方面的有效性。最后，还进行了参数分析，以寻求提高所开发 SiC 功率 MOSFET 模块焊接疲劳寿命的设计准则。
{"title":"Power Cycling Modeling and Lifetime Evaluation of SiC Power MOSFET Module Using a Modified Physical Lifetime Model","authors":"Hsien-Chie Cheng;Ji-Yuan Syu;He-Hong Wang;Yan-Cheng Liu;Kuo-Shu Kao;Tao-Chih Chang","doi":"10.1109/TDMR.2024.3364695","DOIUrl":"10.1109/TDMR.2024.3364695","url":null,"abstract":"This study aims to explore the solder fatigue lifetime of a developed high-voltage (1.7 kV/100 A) SiC power MOSFET module for on-board chargers (OBCs) subjected to power cycling test (PCT) in accordance with AQG 324. To achieve this goal, a design for reliability (DfR) methodology is established, which couples three-dimensional (3D) thermal computational fluid dynamics (CFD) analysis with 3D transient thermal-mechanical finite element analysis (FEA). The time-dependent viscoplastic behavior of the solder layer is taken into consideration in this FEA by virtue of the Anand model. In addition, a modified physical fatigue lifetime model based on Coffin-Manson formula considering the correlation between a failure criterion and a physical damage characteristic is proposed to effectively estimate the solder fatigue lifetime. The coefficients of the modified physical lifetime model are derived by curve-fitting the experimental solder fatigue lifetime data of a commercial 1.2 kV/25 A SiC power MOSFET module and the corresponding calculated equivalent strain increments using the DfR methodology. The proposed DfR methodology together with the constructed fatigue lifetime model are tested on the prediction of the solder fatigue lifetime of the developed high voltage SiC power module, and their validity are demonstrated by comparing the predicted results with the corresponding PCT experimental results. Finally, parametric analysis is performed to seek a design guideline for enhanced solder fatigue lifetime of the developed SiC power MOSFET module.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"142-153"},"PeriodicalIF":2.0,"publicationDate":"2024-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency $(f_{mathrm{ SRF}})$ and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations (14) – (15) are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the $f_{mathrm{ SRF}}$ of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and $R_{rm D_{}SRF}$ . The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.
{"title":"Aging and Sintered Layer Defect Detection of Discrete MOSFETs Using Frequency Domain Reflectometry Associated With Parasitic Resistance","authors":"Minghui Yun;Daoguo Yang;Miao Cai;Haidong Yan;Jiabing Yu;Mengyuan Liu;Siliang He;Guoqi Zhang","doi":"10.1109/TDMR.2024.3363713","DOIUrl":"10.1109/TDMR.2024.3363713","url":null,"abstract":"Metal-oxide-semiconductor field-effect transistors (MOSFETs) undergo fatigue degradation under high thermal and electrical stresses. This process results in changes in their parasitic parameters, which can be detected using frequency domain reflectometry (FDR). Frequency domain impedance analysis is employed to characterize the various quality states of Si and SiC MOSFETs obtained from accelerated aging experiments. Results demonstrate a consistent increase in parasitic resistance as the devices degrade. By determining the drain-source parasitic resistance at the self-resonant frequency \u0000<inline-formula> <tex-math>$(f_{mathrm{ SRF}})$ </tex-math></inline-formula>\u0000 and the drain-source on-resistance for MOSFETs with varying degradation degrees, positive linear numerical fitting equations \u0000<xref>(14)</xref>\u0000–\u0000<xref>(15)</xref>\u0000 are established to predict MOSFET degradation under zero DC bias voltage. In addition, FDR technology is used to identify the drain parasitic resistance at the \u0000<inline-formula> <tex-math>$f_{mathrm{ SRF}}$ </tex-math></inline-formula>\u0000 of MOSFET samples with different sizes of defects in the sintered silver layer. These results reveal a positive correlation between the quality of the sintered silver layer and \u0000<inline-formula> <tex-math>$R_{rm D_{}SRF}$ </tex-math></inline-formula>\u0000. The proposed approach is an effective quality screening technology for power semiconductor devices without requiring power-on treatment.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"129-141"},"PeriodicalIF":2.0,"publicationDate":"2024-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In practical electronic setups, most circuits are operating under dynamic condition, thus the aging models derived under static bias could lead to unexpected deviation from the real circumstance and even errors. Here in this paper, we studied the device degradation under long-period dynamic stress, which aims to mimic the device degradation at alternating voltages. Combined with the degradation characterization, models considering partial recovery after stress removal and degradation at different stress levels are developed. By comparing the test data with the model calculation, it can be seen that the calculation error of the model is within 3%, which meets the requirement of practical engineering. The proposed models could benefit the reliability design against dynamic hot carrier degradation for modern circuits.
{"title":"Characterization and Modeling of Hot Carrier Degradation Under Dynamic Operation Voltage","authors":"Yanning Chen;Kai Wang;Jin Shao;Fang Liu;Xinhuan Yang;Jianyu Zhang;Qianqian Sang;Chuanzheng Wang;Yuanfu Zhao","doi":"10.1109/TDMR.2024.3359187","DOIUrl":"10.1109/TDMR.2024.3359187","url":null,"abstract":"In practical electronic setups, most circuits are operating under dynamic condition, thus the aging models derived under static bias could lead to unexpected deviation from the real circumstance and even errors. Here in this paper, we studied the device degradation under long-period dynamic stress, which aims to mimic the device degradation at alternating voltages. Combined with the degradation characterization, models considering partial recovery after stress removal and degradation at different stress levels are developed. By comparing the test data with the model calculation, it can be seen that the calculation error of the model is within 3%, which meets the requirement of practical engineering. The proposed models could benefit the reliability design against dynamic hot carrier degradation for modern circuits.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"123-128"},"PeriodicalIF":2.0,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-10DOI: 10.1109/TDMR.2024.3352001
Kuo-Shen Chen;Wen-Chun Wu
Stress and warping analyses are frequently required in modern semiconductor and packaging processing. Accurately predicting the structural stress and warping topology is crucial for improving processing reliability. Simple analytic models and their revised forms are typically used for quick estimation. However, these revised analytical forms often rely on considering just a single modification factor, which may not align with practical semiconductor and electronic packaging scenarios and lack appropriate analytical solutions. Consequently, extensive and costly 3D finite element simulations are commonly conducted. In theory, machine learning could offer an effective gray-box estimation solution for such problems. Nevertheless, the performance and impact on parameter settings must be justified and evaluated. To address these concerns, we use typical substrate/film stress/warpage problems as examples to demonstrate the effectiveness of data-driven mechanics prediction. This approach integrates the Stoney equation as the kernel and utilizes an artificial neural network to predict the correction factor based on practical considerations. We apply this approach to three cases of substrate-film structures, including multi-layered film, thicker film, and viscoelastic film, to assess its feasibility and performance. Furthermore, we concurrently address all three practical concerns using the same artificial intelligence scheme. Our findings indicate that the machine-learning prediction can achieve a successful rate of up to 99% for accuracy better than 95%. With the feasibility demonstrated, we propose a scheme that combines this data-driven approach with Green’s function to address the warpage of substrates with discrete film segments. Additionally, we have developed a topology reconstruction method by extending the proposed machine-learning approach for general 3D warpage prediction in related packaging engineering applications.
现代半导体和封装加工中经常需要进行应力和翘曲分析。准确预测结构应力和翘曲拓扑对于提高加工可靠性至关重要。简单的分析模型及其修正形式通常用于快速估算。然而，这些修正的分析模型通常只考虑单一的修正因素，可能与实际的半导体和电子封装情况不符，也缺乏适当的分析解决方案。因此，通常需要进行大量昂贵的 3D 有限元模拟。理论上，机器学习可以为此类问题提供有效的灰盒估算解决方案。不过，必须对其性能和对参数设置的影响进行论证和评估。为了解决这些问题，我们以典型的基底/薄膜应力/扭曲问题为例，展示了数据驱动力学预测的有效性。这种方法将斯通尼方程作为内核，并利用人工神经网络根据实际情况预测修正系数。我们将这种方法应用于三种基底薄膜结构，包括多层薄膜、较厚薄膜和粘弹性薄膜，以评估其可行性和性能。此外，我们还使用同一人工智能方案同时解决了这三个实际问题。我们的研究结果表明，机器学习预测的成功率可达 99%，准确率优于 95%。在证明了可行性之后，我们提出了一种将这种数据驱动方法与格林函数相结合的方案，以解决具有离散薄膜段的基板的翘曲问题。此外，我们还开发了一种拓扑重建方法，通过扩展所提出的机器学习方法，用于相关包装工程应用中的一般三维翘曲预测。
{"title":"Data-Driven Stress/Warpage Analyses Based on Stoney Equation for Packaging Applications","authors":"Kuo-Shen Chen;Wen-Chun Wu","doi":"10.1109/TDMR.2024.3352001","DOIUrl":"10.1109/TDMR.2024.3352001","url":null,"abstract":"Stress and warping analyses are frequently required in modern semiconductor and packaging processing. Accurately predicting the structural stress and warping topology is crucial for improving processing reliability. Simple analytic models and their revised forms are typically used for quick estimation. However, these revised analytical forms often rely on considering just a single modification factor, which may not align with practical semiconductor and electronic packaging scenarios and lack appropriate analytical solutions. Consequently, extensive and costly 3D finite element simulations are commonly conducted. In theory, machine learning could offer an effective gray-box estimation solution for such problems. Nevertheless, the performance and impact on parameter settings must be justified and evaluated. To address these concerns, we use typical substrate/film stress/warpage problems as examples to demonstrate the effectiveness of data-driven mechanics prediction. This approach integrates the Stoney equation as the kernel and utilizes an artificial neural network to predict the correction factor based on practical considerations. We apply this approach to three cases of substrate-film structures, including multi-layered film, thicker film, and viscoelastic film, to assess its feasibility and performance. Furthermore, we concurrently address all three practical concerns using the same artificial intelligence scheme. Our findings indicate that the machine-learning prediction can achieve a successful rate of up to 99% for accuracy better than 95%. With the feasibility demonstrated, we propose a scheme that combines this data-driven approach with Green’s function to address the warpage of substrates with discrete film segments. Additionally, we have developed a topology reconstruction method by extending the proposed machine-learning approach for general 3D warpage prediction in related packaging engineering applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"112-122"},"PeriodicalIF":2.0,"publicationDate":"2024-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.
{"title":"A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process","authors":"Jiang Xu;Zeyu Lei;Chenchen Zhang;Xin Wan;Zhuojun Chen","doi":"10.1109/TDMR.2024.3349621","DOIUrl":"10.1109/TDMR.2024.3349621","url":null,"abstract":"The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"105-111"},"PeriodicalIF":2.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139953277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/TDMR.2023.3344019
Kevin Goodman;Roberto S. Aga;Rachel Aga;Robert Cooper;Lei R. Cao;Emily Heckman
Advancements in printable electronics technology allow the technique to populate laboratories on a widespread scale due to advantages printing electronics holds over customary fabrication methods. For utilization of printed electronics in cosmic environments it behooves end-users to understand the effects of ionizing radiation on these materials as such a threat to microelectronics can be quite detrimental even to the point of failure. This article contains results from exposing aerosol-jet printed graphene to gamma radiation and examines these effects when combined with aging to understand if printed graphene is a suitable candidate for space environments. It documents the effects of radiation on electrical properties of the printed graphene, and it demonstrates the roles of aging and exposure to ambient environment on these effects. Accompanying data taken of the majority hole carrier concentration show an increase of 3.57%, mobility 4.5%, and work function 2.21% from ionizing radiation. While these values are noticeable, aging alone increased the work function by 1.66%, and resistance by 22.9%. While the change observed in resistance is substantial, pacifying the graphene resulted in only a 5% change in resistance. This indicates the graphene ink proves resilient to gamma irradiation up to 1 Mrad(Si) when the discussed methods are implored. The findings indicate this method of aerosol-jet printing graphene based conductive inks demonstrates robustness against gamma radiation making the method a plausible alternative to traditional lithographic techniques even when utilized in environments where gamma radiation is prevalent such as space.
{"title":"Investigation on Electrical Properties of Printed Graphene Subjected to Aging, Ambient Environment and Gamma Radiation","authors":"Kevin Goodman;Roberto S. Aga;Rachel Aga;Robert Cooper;Lei R. Cao;Emily Heckman","doi":"10.1109/TDMR.2023.3344019","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3344019","url":null,"abstract":"Advancements in printable electronics technology allow the technique to populate laboratories on a widespread scale due to advantages printing electronics holds over customary fabrication methods. For utilization of printed electronics in cosmic environments it behooves end-users to understand the effects of ionizing radiation on these materials as such a threat to microelectronics can be quite detrimental even to the point of failure. This article contains results from exposing aerosol-jet printed graphene to gamma radiation and examines these effects when combined with aging to understand if printed graphene is a suitable candidate for space environments. It documents the effects of radiation on electrical properties of the printed graphene, and it demonstrates the roles of aging and exposure to ambient environment on these effects. Accompanying data taken of the majority hole carrier concentration show an increase of 3.57%, mobility 4.5%, and work function 2.21% from ionizing radiation. While these values are noticeable, aging alone increased the work function by 1.66%, and resistance by 22.9%. While the change observed in resistance is substantial, pacifying the graphene resulted in only a 5% change in resistance. This indicates the graphene ink proves resilient to gamma irradiation up to 1 Mrad(Si) when the discussed methods are implored. The findings indicate this method of aerosol-jet printing graphene based conductive inks demonstrates robustness against gamma radiation making the method a plausible alternative to traditional lithographic techniques even when utilized in environments where gamma radiation is prevalent such as space.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"98-104"},"PeriodicalIF":2.0,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140066453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-25DOI: 10.1109/TDMR.2023.3346752
Syed Farah Naz;Debabrata Mondal;Ambika Prasad Shah
Extremely energetic particles in the nuclear environment make memory cells prone to soft errors. Also, attackers extract secret data of SRAM cells via side-channel attacks (SCAs), and leakage power analysis attacks (LPAs) seriously threaten security systems. This paper indicates a highly effective radiation-hardened and LPA-resilient (RHLR12T) SRAM cell that is both radiation-resistant by design and LPA-resilient for nuclear applications. It offers better speed, enhanced writing stability and higher overlap percentage than other considered SRAM cells, such as 6T, Quatro, We-Quatro, and RHMD10T, utilising United Microelectronics Corporation (UMC) 45nm CMOS technology at the supply voltage of 1.0V and $27mathrm {^{circ }}text{C}$ operating temperature. The proposed cell gives $1.141mathrm {times }$ higher write stability, $1.55mathrm {times }$ lower write access time, $1.11mathrm {times }$ increased critical charge and $1.51mathrm {times }$ better overlap percentage than the RHMD10T SRAM cell.
{"title":"Side-Channel Attack Resilient RHBD 12T SRAM Cell for Secure Nuclear Environment","authors":"Syed Farah Naz;Debabrata Mondal;Ambika Prasad Shah","doi":"10.1109/TDMR.2023.3346752","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3346752","url":null,"abstract":"Extremely energetic particles in the nuclear environment make memory cells prone to soft errors. Also, attackers extract secret data of SRAM cells via side-channel attacks (SCAs), and leakage power analysis attacks (LPAs) seriously threaten security systems. This paper indicates a highly effective radiation-hardened and LPA-resilient (RHLR12T) SRAM cell that is both radiation-resistant by design and LPA-resilient for nuclear applications. It offers better speed, enhanced writing stability and higher overlap percentage than other considered SRAM cells, such as 6T, Quatro, We-Quatro, and RHMD10T, utilising United Microelectronics Corporation (UMC) 45nm CMOS technology at the supply voltage of 1.0V and \u0000<inline-formula> <tex-math>$27mathrm {^{circ }}text{C}$ </tex-math></inline-formula>\u0000 operating temperature. The proposed cell gives \u0000<inline-formula> <tex-math>$1.141mathrm {times }$ </tex-math></inline-formula>\u0000 higher write stability, \u0000<inline-formula> <tex-math>$1.55mathrm {times }$ </tex-math></inline-formula>\u0000 lower write access time, \u0000<inline-formula> <tex-math>$1.11mathrm {times }$ </tex-math></inline-formula>\u0000 increased critical charge and \u0000<inline-formula> <tex-math>$1.51mathrm {times }$ </tex-math></inline-formula>\u0000 better overlap percentage than the RHMD10T SRAM cell.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"59-67"},"PeriodicalIF":2.0,"publicationDate":"2023-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-22DOI: 10.1109/TDMR.2023.3346190
Meng Zhang;Fei Wu;Qin Yu;Changsheng Xie
Although three-dimensional (3D) NAND flash memory has demonstrated impressive benefits including high capacity and storage density, data reliability is now a major worry because of long-term storage and ongoing cell wear-out. Low-density parity-check (LDPC) codes are frequently utilized in flash storage systems because of their superior error correcting capabilities to guarantee data reliability. LDPC codes can be hard-decoded or soft-decoded with significant differences depending on the raw bit error rate (RBER). By using fine-grained memory sensing operations, high RBER leads to increased decoding iterations for hard-decoding and more read levels for soft-decoding. In order to reduce the number of decoding iterations and read levels by lowering the RBER, this paper proposes an unbalanced inter-page errors aware read strategy for 3D NAND flash memory, called PEAR. A preliminary experiment is initially carried out to demonstrate that high RBER causes an increase in the number of decoding iterations and read levels. The substantial RBER fluctuation between pages is next analyzed from the viewpoint of the threshold voltage shift. Finally, PEAR properly places the read voltages between the two states with the most and second-most electrons in accordance with the phenomenon of threshold voltage drift, enabling the employment of hard-decoding with low read levels and successfully avoiding soft-decoding procedures with larger RBER. According to simulation results, PEAR can dramatically reduce RBER, decoding iterations, read levels, and read latency.
{"title":"PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3-D NAND Flash","authors":"Meng Zhang;Fei Wu;Qin Yu;Changsheng Xie","doi":"10.1109/TDMR.2023.3346190","DOIUrl":"https://doi.org/10.1109/TDMR.2023.3346190","url":null,"abstract":"Although three-dimensional (3D) NAND flash memory has demonstrated impressive benefits including high capacity and storage density, data reliability is now a major worry because of long-term storage and ongoing cell wear-out. Low-density parity-check (LDPC) codes are frequently utilized in flash storage systems because of their superior error correcting capabilities to guarantee data reliability. LDPC codes can be hard-decoded or soft-decoded with significant differences depending on the raw bit error rate (RBER). By using fine-grained memory sensing operations, high RBER leads to increased decoding iterations for hard-decoding and more read levels for soft-decoding. In order to reduce the number of decoding iterations and read levels by lowering the RBER, this paper proposes an unbalanced inter-page errors aware read strategy for 3D NAND flash memory, called PEAR. A preliminary experiment is initially carried out to demonstrate that high RBER causes an increase in the number of decoding iterations and read levels. The substantial RBER fluctuation between pages is next analyzed from the viewpoint of the threshold voltage shift. Finally, PEAR properly places the read voltages between the two states with the most and second-most electrons in accordance with the phenomenon of threshold voltage drift, enabling the employment of hard-decoding with low read levels and successfully avoiding soft-decoding procedures with larger RBER. According to simulation results, PEAR can dramatically reduce RBER, decoding iterations, read levels, and read latency.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"49-58"},"PeriodicalIF":2.0,"publicationDate":"2023-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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