The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I$_{text {ON}}$ ) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V$_{text {DS}} = 0.3$ V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.
{"title":"Negative Capacitance Vertical Dopingless TFET and Its Analog/RF Analysis Using Interface Trap Charges","authors":"Vibhash Choudhary;Sachin Agrawal;Manoj Kumar;Madhulika Verma","doi":"10.1109/TDMR.2025.3533004","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3533004","url":null,"abstract":"The increasing demand for low-power devices has developed a huge interest in the Tunnel Field-Effect Transistor (TFET). However, challenges such as low ON current (I<inline-formula> <tex-math>$_{text {ON}}$ </tex-math></inline-formula>) and random dopant fluctuations limit its demand. To address these limitations, this paper proposed a charge plasma based ferroelectric negative capacitance vertical dopingless TFET (NC-VDL-TFET). In the proposed device, initially, dielectric engineering and architectural modification are used to improve the ION. The simulation result shows that these modifications increased the ION by 16.13%. Afterwards, a silicon-doped HfO2 ferroelectric material is employed above the gate oxide, which results in further improvement of 96.63% in ION. The overall simulation results demonstrate a significant improvement in DC and analog/RF characteristics at a low voltage supply (V<inline-formula> <tex-math>$_{text {DS}} = 0.3$ </tex-math></inline-formula>V), making the proposed device a potential candidate for future integrated circuits. Further, a detailed investigation of interface trap charges (ITCs) on the proposed device is analysed for reliability purposes. The simulated results performed for Analog/RF analysis show the proposed device is immune towards the impact of ITCs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"163-172"},"PeriodicalIF":2.5,"publicationDate":"2025-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-14DOI: 10.1109/TDMR.2025.3528093
{"title":"2024 Index IEEE Transactions on Device and Materials Reliability Vol. 24","authors":"","doi":"10.1109/TDMR.2025.3528093","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3528093","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"665-682"},"PeriodicalIF":2.5,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10841807","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142975942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-13DOI: 10.1109/TDMR.2025.3528903
Dhananjay Prakash;Neha Kamal;Avinash Lahgere
In this paper, a comprehensive TCAD-based single event effect (SEE) study on tunnel field effect transistor (TFET) based one transistor dynamic random access memory (1T DRAM) and crossbar memory array is demonstrated through well-calibrated 2-D TCAD simulations. The simulation study reveals that the regions near Gate 2 are more susceptible to SEE. In addition, in comparison to without SEE, when a high energy particle (HEP) strikes the device, the read “1” (R1) current remains the same, however, the read “0” (R0) current increases $sim ~10times $ at 358 K. As a result, the read current ratio (IR1/I$_{mathrm {R0}}$ ) and the sense margin (SM) decreases. The IR1/IR0 ratio with SEE is found to be $sim ~10^{2}$ , which is $10times $ lower than ratio without SEE. In addition, the impact of various parameters such as linear energy transfer (LET), HEP strike time, HEP strike moment, and HEP radius on TFET-based 1T DRAM performance is also evaluated. Moreover, for a 2 x 2 crossbar memory array, the combination of SEE with word line disturbance mechanism causes $sim ~10times $ reduction in the R1 current at 358 K. Our findings will pave the way for further exploration and designing radiation-hardened TFET-based 1T DRAM for future low-power space applications.
{"title":"Comprehensive TCAD-Based Single Event Effect Study of TFET-Based 1T DRAM and Crossbar Memory Array","authors":"Dhananjay Prakash;Neha Kamal;Avinash Lahgere","doi":"10.1109/TDMR.2025.3528903","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3528903","url":null,"abstract":"In this paper, a comprehensive TCAD-based single event effect (SEE) study on tunnel field effect transistor (TFET) based one transistor dynamic random access memory (1T DRAM) and crossbar memory array is demonstrated through well-calibrated 2-D TCAD simulations. The simulation study reveals that the regions near Gate 2 are more susceptible to SEE. In addition, in comparison to without SEE, when a high energy particle (HEP) strikes the device, the read “1” (R1) current remains the same, however, the read “0” (R0) current increases <inline-formula> <tex-math>$sim ~10times $ </tex-math></inline-formula> at 358 K. As a result, the read current ratio (IR1/I<inline-formula> <tex-math>$_{mathrm {R0}}$ </tex-math></inline-formula>) and the sense margin (SM) decreases. The IR1/IR0 ratio with SEE is found to be <inline-formula> <tex-math>$sim ~10^{2}$ </tex-math></inline-formula>, which is <inline-formula> <tex-math>$10times $ </tex-math></inline-formula> lower than ratio without SEE. In addition, the impact of various parameters such as linear energy transfer (LET), HEP strike time, HEP strike moment, and HEP radius on TFET-based 1T DRAM performance is also evaluated. Moreover, for a 2 x 2 crossbar memory array, the combination of SEE with word line disturbance mechanism causes <inline-formula> <tex-math>$sim ~10times $ </tex-math></inline-formula> reduction in the R1 current at 358 K. Our findings will pave the way for further exploration and designing radiation-hardened TFET-based 1T DRAM for future low-power space applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"156-162"},"PeriodicalIF":2.5,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The total ionizing dose (TID) responses of $0.35~mu $ m and $0.13~mu $ m SiGe HBTs at liquid-nitrogen temperature (78 K) were investigated using 10 keV X-rays. For the first time, we compared the annealing behaviors of SiGe HBTs irradiated at 78 K and room temperature (297 K). The results reconfirm that SiGe HBTs have superior TID tolerance up to Mrad(Si) levels, and the current gain degradation of DUTs irradiated at 78 K is much less than those irradiated at 297 K. However, the $0.35~mu $ m SiGe HBTs irradiated at 78 K show further degradation after room temperature annealing (RTA) due to the thermal activation of oxide charge migration and the long-term buildup of interface traps. The $0.13~mu $ m SiGe HBTs irradiated at 78 K show minor change after RTA, which can be attributed to the competition between interface trap creation and annealing.
用10 keV x射线研究了液氮温度（78 K）下$0.35~mu $ m和$0.13~mu $ m SiGe HBTs的总电离剂量（TID）响应。我们首次比较了78 K和297 K下SiGe HBTs的退火行为，结果再次证实了SiGe HBTs在Mrad（Si）水平下具有优越的TID耐受性，并且78 K下的电流增益衰减远小于297 K下的。然而，在78 K下辐照的$0.35~mu $ m SiGe HBTs在室温退火（RTA）后，由于氧化物电荷迁移的热激活和界面陷阱的长期积累，表现出进一步的降解。78 K下辐照的$0.13~mu $ m SiGe HBTs在RTA后变化不大，这可归因于界面陷阱产生和退火之间的竞争。
{"title":"Cryogenic Total Ionizing Dose Effects and Annealing Behaviors of SiGe HBTs","authors":"Jianan Wei;Peijian Zhang;Xiaohui Yi;Min Hong;Xiaojun Fu;Xinyue Tang;Kun Qian;Xiaolei Zhang;Wenlong Liao;Jiandong Zang;Lei Zhang;Ting Luo;Yunchen Wu","doi":"10.1109/TDMR.2024.3523303","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3523303","url":null,"abstract":"The total ionizing dose (TID) responses of <inline-formula> <tex-math>$0.35~mu $ </tex-math></inline-formula>m and <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m SiGe HBTs at liquid-nitrogen temperature (78 K) were investigated using 10 keV X-rays. For the first time, we compared the annealing behaviors of SiGe HBTs irradiated at 78 K and room temperature (297 K). The results reconfirm that SiGe HBTs have superior TID tolerance up to Mrad(Si) levels, and the current gain degradation of DUTs irradiated at 78 K is much less than those irradiated at 297 K. However, the <inline-formula> <tex-math>$0.35~mu $ </tex-math></inline-formula>m SiGe HBTs irradiated at 78 K show further degradation after room temperature annealing (RTA) due to the thermal activation of oxide charge migration and the long-term buildup of interface traps. The <inline-formula> <tex-math>$0.13~mu $ </tex-math></inline-formula>m SiGe HBTs irradiated at 78 K show minor change after RTA, which can be attributed to the competition between interface trap creation and annealing.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"150-155"},"PeriodicalIF":2.5,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-30DOI: 10.1109/TDMR.2024.3524100
Y. D. Wei;G. Z. Liu;J. H. Wei;W. Zhao;Y. Q. Wei;Y. Zhou;Z. Y. Sui;M. J. Liu;H. Ju;Y. Gao;H. Yang;J. P. Sun;Y. Liu
In this paper, the 2T SONOS FLASH is designed and fabricated based on 180 nm embedded FLASH process which includes one MOSFET and one SONOS FLASH transistor. The FLASH transistors are programmed and erased by band-to-band tunneling-induced hot electron and Fowler-Nordheim to realize different levels, and the mechanisms of the electrical degradation caused by radiation are investigated by the mid-gap technique. In order to clarify the degradation mechanism from the physical level, the first principle calculations are performed from the atomic and electronic term. The electric fields and the external environment are proved to play a crucial role in the charge loss. The higher electric fields can exacerbate the formation of the oxide charge, and the anti-radiation hardness can be achieved with oxygen-rich environment. The external field can efficiently change the electronic properties of $alpha $ -SiO2 with oxygen vacancy and hydrogen. This study provides a novel perspective of electrical degradations on the SONOS FLASH unit in different levels from both the experiments and theoretical simulations, which can be helpful for the design of advanced computational chips in space.
{"title":"Degradation Behavior and Mechanism of SONOS FLASH by Total Ionization Dose Effects","authors":"Y. D. Wei;G. Z. Liu;J. H. Wei;W. Zhao;Y. Q. Wei;Y. Zhou;Z. Y. Sui;M. J. Liu;H. Ju;Y. Gao;H. Yang;J. P. Sun;Y. Liu","doi":"10.1109/TDMR.2024.3524100","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3524100","url":null,"abstract":"In this paper, the 2T SONOS FLASH is designed and fabricated based on 180 nm embedded FLASH process which includes one MOSFET and one SONOS FLASH transistor. The FLASH transistors are programmed and erased by band-to-band tunneling-induced hot electron and Fowler-Nordheim to realize different levels, and the mechanisms of the electrical degradation caused by radiation are investigated by the mid-gap technique. In order to clarify the degradation mechanism from the physical level, the first principle calculations are performed from the atomic and electronic term. The electric fields and the external environment are proved to play a crucial role in the charge loss. The higher electric fields can exacerbate the formation of the oxide charge, and the anti-radiation hardness can be achieved with oxygen-rich environment. The external field can efficiently change the electronic properties of <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>-SiO2 with oxygen vacancy and hydrogen. This study provides a novel perspective of electrical degradations on the SONOS FLASH unit in different levels from both the experiments and theoretical simulations, which can be helpful for the design of advanced computational chips in space.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"128-133"},"PeriodicalIF":2.5,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deep Neural Network (DNN) hardware accelerators are essential in a spectrum of safety-critical edge-AI applications with stringent reliability, energy efficiency, and latency requirements. Multiplication is the most resource-hungry operation in the neural network’s processing elements. This paper proposes a scalable adaptive fault-tolerant approximate multiplier (AdAM) tailored for ASIC-based DNN accelerators at the algorithm and circuit levels. AdAM employs an adaptive adder that relies on an unconventional use of input Leading One Detector (LOD) values for fault detection by optimizing unutilized adder resources. A gate-level optimized LOD design and a hybrid adder design are also proposed as a part of the adaptive multiplier to improve the hardware performance. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the Triple Modular Redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR while at the same time utilizing $2.74 times $ less area and with 39.06% less power-delay product compared to the exact multiplier. Moreover, it has similar area, delay, and power consumption parameters compared to the state-of-the-art approximate multipliers with similar accuracy while providing fault detection and mitigation capability.
{"title":"AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators","authors":"Mahdi Taheri;Natalia Cherezova;Samira Nazari;Ali Azarpeyvand;Tara Ghasempouri;Masoud Daneshtalab;Jaan Raik;Maksim Jenihhin","doi":"10.1109/TDMR.2024.3523386","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3523386","url":null,"abstract":"Deep Neural Network (DNN) hardware accelerators are essential in a spectrum of safety-critical edge-AI applications with stringent reliability, energy efficiency, and latency requirements. Multiplication is the most resource-hungry operation in the neural network’s processing elements. This paper proposes a scalable adaptive fault-tolerant approximate multiplier (AdAM) tailored for ASIC-based DNN accelerators at the algorithm and circuit levels. AdAM employs an adaptive adder that relies on an unconventional use of input Leading One Detector (LOD) values for fault detection by optimizing unutilized adder resources. A gate-level optimized LOD design and a hybrid adder design are also proposed as a part of the adaptive multiplier to improve the hardware performance. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the Triple Modular Redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR while at the same time utilizing <inline-formula> <tex-math>$2.74 times $ </tex-math></inline-formula> less area and with 39.06% less power-delay product compared to the exact multiplier. Moreover, it has similar area, delay, and power consumption parameters compared to the state-of-the-art approximate multipliers with similar accuracy while providing fault detection and mitigation capability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"66-75"},"PeriodicalIF":2.5,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-27DOI: 10.1109/TDMR.2024.3523341
Kaining Kuang;Xinhua Guo;Zhengyan Zhou;Chunzhen Li;Xiuwan Li
In electric vehicles (EVs), film capacitors are installed in the traction inverter to reduce ripple current. However, the lifespan of commercial film capacitors is highly sensitive to temperature fluctuations. The high ambient temperature within the traction inverter often leads to the premature failure of these capacitors, severely impacting the reliability of the traction drive system. In existing studies, the internal losses of capacitors have often been treated as constant, overlooking variations caused by changes in operating conditions and aging, which results in discrepancies between predicted and actual lifespans. This paper first proposes a new finite element analysis (FEA) modelling strategy to more accurately determine the hotspot temperature rise by considering the distribution of losses within the capacitor core. Next, based on the Federal Testing Procedure -75 (FTP-75) driving cycle, the operating profile of capacitors during EV operation is obtained. Following that, the cumulative damage of the capacitor is evaluated according to Miner’s rule, and the lifespan of the film capacitors is assessed. This method can offer a reference for capacitor replacements planning.
{"title":"Mission Profile-Based Hotspot Temperature and Lifespan Estimation of DC-Link Capacitors Used in Automotive Traction Inverters","authors":"Kaining Kuang;Xinhua Guo;Zhengyan Zhou;Chunzhen Li;Xiuwan Li","doi":"10.1109/TDMR.2024.3523341","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3523341","url":null,"abstract":"In electric vehicles (EVs), film capacitors are installed in the traction inverter to reduce ripple current. However, the lifespan of commercial film capacitors is highly sensitive to temperature fluctuations. The high ambient temperature within the traction inverter often leads to the premature failure of these capacitors, severely impacting the reliability of the traction drive system. In existing studies, the internal losses of capacitors have often been treated as constant, overlooking variations caused by changes in operating conditions and aging, which results in discrepancies between predicted and actual lifespans. This paper first proposes a new finite element analysis (FEA) modelling strategy to more accurately determine the hotspot temperature rise by considering the distribution of losses within the capacitor core. Next, based on the Federal Testing Procedure -75 (FTP-75) driving cycle, the operating profile of capacitors during EV operation is obtained. Following that, the cumulative damage of the capacitor is evaluated according to Miner’s rule, and the lifespan of the film capacitors is assessed. This method can offer a reference for capacitor replacements planning.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"134-143"},"PeriodicalIF":2.5,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a novel radiation hardened SOI LDMOS with dual P-type layers is proposed. Based on irradiation charge field modulation, two P-type layers are introduced at the surface and bottom in N-drift region for suppressing shifts of both specific on-resistance $(R_{textrm {on,sp}})$ and breakdown voltage (BV). Irradiation charge field is shielded by the P-type layers at low drain voltage and electron behavior in the bulk is protected against the modulation, resulting in $R_{textrm {on,sp}}$ shifting less significantly. Besides, net charge density in drift region is reduced by the P-type layers, and then surface electric field is weakened at source side, resulting in a non-monotonic shift in BV. A low net charge density with high donor doping concentration in P-N-P drift region is pursued instead of charge balance required in traditional design. Simulated optimized results show that $R_{textrm {on,sp}}$ shifts only 11.4% at TID ${=} 300$ krad(Si).
{"title":"Radiation Hardened SOI LDMOS With Dual P-Type Layers Shielding Irradiation Charge Field","authors":"Xin Zhou;Jie Shen;Ziqiu Tong;Zhao Qi;Ming Qiao;Zhaoji Li;Bo Zhang","doi":"10.1109/TDMR.2024.3523577","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3523577","url":null,"abstract":"In this paper, a novel radiation hardened SOI LDMOS with dual P-type layers is proposed. Based on irradiation charge field modulation, two P-type layers are introduced at the surface and bottom in N-drift region for suppressing shifts of both specific on-resistance <inline-formula> <tex-math>$(R_{textrm {on,sp}})$ </tex-math></inline-formula> and breakdown voltage (BV). Irradiation charge field is shielded by the P-type layers at low drain voltage and electron behavior in the bulk is protected against the modulation, resulting in <inline-formula> <tex-math>$R_{textrm {on,sp}}$ </tex-math></inline-formula> shifting less significantly. Besides, net charge density in drift region is reduced by the P-type layers, and then surface electric field is weakened at source side, resulting in a non-monotonic shift in BV. A low net charge density with high donor doping concentration in P-N-P drift region is pursued instead of charge balance required in traditional design. Simulated optimized results show that <inline-formula> <tex-math>$R_{textrm {on,sp}}$ </tex-math></inline-formula> shifts only 11.4% at TID <inline-formula> <tex-math>${=} 300$ </tex-math></inline-formula>krad(Si).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 1","pages":"144-149"},"PeriodicalIF":2.5,"publicationDate":"2024-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TDMR.2024.3520737
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/TDMR.2024.3520737","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3520737","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"664-664"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812357","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TDMR.2024.3516717
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2024.3516717","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3516717","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"C2-C2"},"PeriodicalIF":2.5,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812356","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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