Pub Date : 2023-10-13DOI: 10.1109/TDMR.2023.3324348
Abdul Shabir;Cher Ming Tan;Preetpal Singh
Silicone possesses good thermal and chemical stability, hydrophobicity, and thus it has a wide range of application. It is also employed as encapsulant and housing for high power LEDs which are increasingly common for various kind of lighting applications. In outdoor applications of high-power LEDs, UV irradiation from sunlight is presence. There are also UV LEDs for other lighting applications, and these LEDs are using silicone as encapsulant to protect the semiconductor chips within. However, the effect of UV irradiation on the reliability of silicone is seldom studied. This work studied the reliability of silicone packaging in LEDs under UV irradiation, and through detailed failure analysis, we found that the silicone does degrade under the UV irradiation that affect the reliability of the LEDs. The degradation mechanisms of silicone and the degradation rate due to UV are found to depend on the type of high-power LEDs, with blue LED degrades faster than white counterpart. Ab-initio analysis using density functional theory is employed to have a deeper insight on the degradation mechanisms and the analysis results explain well our experimental observations. Basically, the silicone degradation mechanism in the presence of UV irradiation is a progression of moisture assisted hydrolysis, condensation and thermal oxidation.
{"title":"Degradation Physics of Silicone Under UV-A Irradiation","authors":"Abdul Shabir;Cher Ming Tan;Preetpal Singh","doi":"10.1109/TDMR.2023.3324348","DOIUrl":"10.1109/TDMR.2023.3324348","url":null,"abstract":"Silicone possesses good thermal and chemical stability, hydrophobicity, and thus it has a wide range of application. It is also employed as encapsulant and housing for high power LEDs which are increasingly common for various kind of lighting applications. In outdoor applications of high-power LEDs, UV irradiation from sunlight is presence. There are also UV LEDs for other lighting applications, and these LEDs are using silicone as encapsulant to protect the semiconductor chips within. However, the effect of UV irradiation on the reliability of silicone is seldom studied. This work studied the reliability of silicone packaging in LEDs under UV irradiation, and through detailed failure analysis, we found that the silicone does degrade under the UV irradiation that affect the reliability of the LEDs. The degradation mechanisms of silicone and the degradation rate due to UV are found to depend on the type of high-power LEDs, with blue LED degrades faster than white counterpart. Ab-initio analysis using density functional theory is employed to have a deeper insight on the degradation mechanisms and the analysis results explain well our experimental observations. Basically, the silicone degradation mechanism in the presence of UV irradiation is a progression of moisture assisted hydrolysis, condensation and thermal oxidation.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"584-590"},"PeriodicalIF":2.0,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136305428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-12DOI: 10.1109/TDMR.2023.3323977
Moufu Kong;Zeyu Cheng;Zewei Hu;Ning Yu;Bo Yi;Hongqiang Yang
In this paper, a new ultra-low specific on-resistance quasi SiC MOSFET is proposed. Compared with the conventional SiC MOSFET, the proposed quasi SiC MOSFET has no problems caused by low channel mobility and gate oxide reliability. And compared with the conventional SiC JFET, the proposed quasi SiC MOSFET is a normally-off device without the controllability issue of the normally-on device. Through simulation, it is found that the specific on-resistance $(R_{mathrm{ on,sp}})$ of the proposed quasi SiC MOSFET is 2.46m $Omega cdot $ cm 2, while the $R_{mathrm{ on,sp}}$ of the conventional SiC MOSFET is 3.29 $text{m}Omega cdot $ cm 2, with a reduction of more than 25% at almost the same breakdown voltage. In the forward conduction state, the saturation current of the proposed quasi SiC MOSFET is smaller than that of the conventional SiC MOSFET at $V_{mathrm{ GS}},,=$ 15V and 20V, which shows that the proposed quasi SiC MOSFET has a better safe operating area (SOA) and better short-circuit capability. Compared with the conventional SiC MOSFET, the Figure-of-Merit (FOM) of the proposed device is improved by 38%. In addition, since the proposed structure is sustaining voltage by the high voltage JFET cell without a gate oxide layer, it is suggested that the proposed device does not have gate oxide reliability problems.
{"title":"A New SiC Quasi MOSFET for Ultra-Low Specific On-Resistance and Improved Reliability","authors":"Moufu Kong;Zeyu Cheng;Zewei Hu;Ning Yu;Bo Yi;Hongqiang Yang","doi":"10.1109/TDMR.2023.3323977","DOIUrl":"10.1109/TDMR.2023.3323977","url":null,"abstract":"In this paper, a new ultra-low specific on-resistance quasi SiC MOSFET is proposed. Compared with the conventional SiC MOSFET, the proposed quasi SiC MOSFET has no problems caused by low channel mobility and gate oxide reliability. And compared with the conventional SiC JFET, the proposed quasi SiC MOSFET is a normally-off device without the controllability issue of the normally-on device. Through simulation, it is found that the specific on-resistance \u0000<inline-formula> <tex-math>$(R_{mathrm{ on,sp}})$ </tex-math></inline-formula>\u0000 of the proposed quasi SiC MOSFET is 2.46m\u0000<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>\u0000cm 2, while the \u0000<inline-formula> <tex-math>$R_{mathrm{ on,sp}}$ </tex-math></inline-formula>\u0000 of the conventional SiC MOSFET is 3.29 \u0000<inline-formula> <tex-math>$text{m}Omega cdot $ </tex-math></inline-formula>\u0000cm 2, with a reduction of more than 25% at almost the same breakdown voltage. In the forward conduction state, the saturation current of the proposed quasi SiC MOSFET is smaller than that of the conventional SiC MOSFET at \u0000<inline-formula> <tex-math>$V_{mathrm{ GS}},,=$ </tex-math></inline-formula>\u0000 15V and 20V, which shows that the proposed quasi SiC MOSFET has a better safe operating area (SOA) and better short-circuit capability. Compared with the conventional SiC MOSFET, the Figure-of-Merit (FOM) of the proposed device is improved by 38%. In addition, since the proposed structure is sustaining voltage by the high voltage JFET cell without a gate oxide layer, it is suggested that the proposed device does not have gate oxide reliability problems.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"577-583"},"PeriodicalIF":2.0,"publicationDate":"2023-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136302835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The negative bias temperature instability (NBTI) of the top-gated p-type carbon nanotube (CNT) thin film transistors (TFTs) with yttrium oxide (Y2O3) dielectric is investigated under different gate bias, stress and relaxation time for the first time. Positive and fast reversible threshold voltage shift along with significant degradation of subthreshold and trans-conductance are observed. The effects of ambient condition are basically excluded by experimental results, and the NBTI in these CNT devices is believed to be primarily due to the generation of considerable interface traps and border traps near dielectric/CNT interface, highlighting the importance of the interface optimization for CNT TFTs in the future. The hysteresis characteristics during stress and recovery are discussed as well, to further explore the stress-induced-traps properties. All these results may provide a reference for the future study on the gate oxide reliability of CNT TFTs with Y2O3 dielectric.
{"title":"Negative Bias Temperature Instability in Top-Gated Carbon Nanotube Thin Film Transistors With Y2O3 Gate Dielectric","authors":"Yuwei Wang;Sha Wang;Huaidong Ye;Wenhao Zhang;Li Xiang","doi":"10.1109/TDMR.2023.3322157","DOIUrl":"10.1109/TDMR.2023.3322157","url":null,"abstract":"The negative bias temperature instability (NBTI) of the top-gated p-type carbon nanotube (CNT) thin film transistors (TFTs) with yttrium oxide (Y2O3) dielectric is investigated under different gate bias, stress and relaxation time for the first time. Positive and fast reversible threshold voltage shift along with significant degradation of subthreshold and trans-conductance are observed. The effects of ambient condition are basically excluded by experimental results, and the NBTI in these CNT devices is believed to be primarily due to the generation of considerable interface traps and border traps near dielectric/CNT interface, highlighting the importance of the interface optimization for CNT TFTs in the future. The hysteresis characteristics during stress and recovery are discussed as well, to further explore the stress-induced-traps properties. All these results may provide a reference for the future study on the gate oxide reliability of CNT TFTs with Y2O3 dielectric.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"571-576"},"PeriodicalIF":2.0,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136004404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-29DOI: 10.1109/TDMR.2023.3320976
Pragna Bhaskar;Ethan Shackelford;Emily K. McGuinness;Mohan Kathaperumal;Mark D. Losego;Madhavan Swaminathan
This paper explores the effect of vapor phase infiltration (VPI) on ultra-low-k (ULK) dielectric materials. Adhesion of metals to these ultra-low-k polymers is an important factor in the fabrication of multilayer redistribution layer (RDL) structures and also the reliability of RDLs. ULK polymers have lower adhesion to metal films than the current industry standard, Ajinomoto Buildup Film (ABF). Earlier studies have shown an improvement in adhesion strength between metal films and benzocyclobutene-based polymers when a VPI treatment is used. In this study we evaluate the effect of VPI on other ULK polymers, having dielectric constants less than 2.5.
{"title":"Effect of Vapor Phase Infiltration on Metal-Polymer Adhesion for Ultra-Low-k Dielectric Materials","authors":"Pragna Bhaskar;Ethan Shackelford;Emily K. McGuinness;Mohan Kathaperumal;Mark D. Losego;Madhavan Swaminathan","doi":"10.1109/TDMR.2023.3320976","DOIUrl":"10.1109/TDMR.2023.3320976","url":null,"abstract":"This paper explores the effect of vapor phase infiltration (VPI) on ultra-low-k (ULK) dielectric materials. Adhesion of metals to these ultra-low-k polymers is an important factor in the fabrication of multilayer redistribution layer (RDL) structures and also the reliability of RDLs. ULK polymers have lower adhesion to metal films than the current industry standard, Ajinomoto Buildup Film (ABF). Earlier studies have shown an improvement in adhesion strength between metal films and benzocyclobutene-based polymers when a VPI treatment is used. In this study we evaluate the effect of VPI on other ULK polymers, having dielectric constants less than 2.5.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"564-570"},"PeriodicalIF":2.0,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135845106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-20DOI: 10.1109/TDMR.2023.3317539
Sharmila B;Priyanka Dwivedi
This paper presents the reliability and process scalability aspects to fabricate efficient broadband photodetectors based on titanium dioxide (TiO2)/porous silicon (P-Si). Here we have compared the performance and photoresponse of the TiO2/P-Si photodetectors with the P-Si photodetectors. The photosensing performance of the fabricated photodetectors were tested in the broadband spectrum (ultraviolet (UV) to near infrared (NIR)) at room temperature (RT). The TiO2/P-Si photodetectors showed more reliable, repeatable and reproducible results at room temperature (RT). The TiO2/P-Si photodetectors showed a photoresponsivity of ~820 mA/W and detectivity of $5.2times 10,,^{mathrm{ 10}}$ Jones. The photoresponsivity value for TiO2/P-Si is ~8 times higher than the P-Si based photodetectors. Moreover, the TiO2/P-Si photodetector offers rise/fall times of 11/14 ms with excellent repeatability and reproducibility. Further, the TiO2/P-Si photodetector’s reliability test was conducted from 293 K to 400 K. The TiO2/P-Si photodetector offered improved, reliable, repeatable, and stable results at 400 K. The aforementioned results proved that the highly efficient TiO2/P-Si photodetector could be useful for real time optical sensing applications.
{"title":"Reliability and Process Scalability of TiO2/Porous Silicon-Based Broadband Photodetectors","authors":"Sharmila B;Priyanka Dwivedi","doi":"10.1109/TDMR.2023.3317539","DOIUrl":"10.1109/TDMR.2023.3317539","url":null,"abstract":"This paper presents the reliability and process scalability aspects to fabricate efficient broadband photodetectors based on titanium dioxide (TiO2)/porous silicon (P-Si). Here we have compared the performance and photoresponse of the TiO2/P-Si photodetectors with the P-Si photodetectors. The photosensing performance of the fabricated photodetectors were tested in the broadband spectrum (ultraviolet (UV) to near infrared (NIR)) at room temperature (RT). The TiO2/P-Si photodetectors showed more reliable, repeatable and reproducible results at room temperature (RT). The TiO2/P-Si photodetectors showed a photoresponsivity of ~820 mA/W and detectivity of \u0000<inline-formula> <tex-math>$5.2times 10,,^{mathrm{ 10}}$ </tex-math></inline-formula>\u0000 Jones. The photoresponsivity value for TiO2/P-Si is ~8 times higher than the P-Si based photodetectors. Moreover, the TiO2/P-Si photodetector offers rise/fall times of 11/14 ms with excellent repeatability and reproducibility. Further, the TiO2/P-Si photodetector’s reliability test was conducted from 293 K to 400 K. The TiO2/P-Si photodetector offered improved, reliable, repeatable, and stable results at 400 K. The aforementioned results proved that the highly efficient TiO2/P-Si photodetector could be useful for real time optical sensing applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"516-520"},"PeriodicalIF":2.0,"publicationDate":"2023-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135557438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-18DOI: 10.1109/TDMR.2023.3316928
Renze Yu;Saeed Jahdi;Olayiwola Alatise;Jose Ortiz-Gonzalez;Sai Priya Munagala;Nick Simpson;Phil Mellor
The reliability of the SiC MOSFET has always been a factor hindering the device application, especially under high voltage and high current conditions, such as in the short circuit events. This paper experimentally reviews the failure mechanisms caused by destructive short circuit impulses, and investigates the degradation patterns of key electrical parameters under repetitive short circuit events. The impact of test parameters on the short circuit reliability of SiC MOSFET has been analyzed. Approaches to characterize the electrical-thermal-mechanical stress during the short circuit period and advanced test methods are highlighted. Finally, the constraints from the standpoint of both manufacturers and users have been presented, including comparison of current SiC MOSFET devices, reliability evaluation of parallel SiC MOSFET devices, reliability improvement of the chip, performance improvement of protection circuits, and reliability assessment of SiC MOSFET devices under application-representative stress.
SiC MOSFET的可靠性一直是阻碍器件应用的一个因素，特别是在高电压和大电流条件下，例如在短路事件中。本文通过实验综述了破坏性短路脉冲的失效机制，并研究了重复短路事件下关键电气参数的退化规律。分析了测试参数对SiC MOSFET短路可靠性的影响。重点介绍了表征短路时电-热-机械应力的方法和先进的测试方法。最后，从制造商和用户的角度提出了限制条件，包括现有SiC MOSFET器件的比较，并行SiC MOSFET器件的可靠性评估，芯片的可靠性改进，保护电路的性能改进以及SiC MOSFET器件在应用代表性应力下的可靠性评估。
{"title":"Measurements and Review of Failure Mechanisms and Reliability Constraints of 4H-SiC Power MOSFETs Under Short Circuit Events","authors":"Renze Yu;Saeed Jahdi;Olayiwola Alatise;Jose Ortiz-Gonzalez;Sai Priya Munagala;Nick Simpson;Phil Mellor","doi":"10.1109/TDMR.2023.3316928","DOIUrl":"10.1109/TDMR.2023.3316928","url":null,"abstract":"The reliability of the SiC MOSFET has always been a factor hindering the device application, especially under high voltage and high current conditions, such as in the short circuit events. This paper experimentally reviews the failure mechanisms caused by destructive short circuit impulses, and investigates the degradation patterns of key electrical parameters under repetitive short circuit events. The impact of test parameters on the short circuit reliability of SiC MOSFET has been analyzed. Approaches to characterize the electrical-thermal-mechanical stress during the short circuit period and advanced test methods are highlighted. Finally, the constraints from the standpoint of both manufacturers and users have been presented, including comparison of current SiC MOSFET devices, reliability evaluation of parallel SiC MOSFET devices, reliability improvement of the chip, performance improvement of protection circuits, and reliability assessment of SiC MOSFET devices under application-representative stress.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"544-563"},"PeriodicalIF":2.0,"publicationDate":"2023-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135501693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-18DOI: 10.1109/TDMR.2023.3316774
Jihee Bae;Hyoungseuk Choi
Fluorine-doped tin oxide (FTO) is a transparent conductive oxide that is used in solar cells and energy devices. In this study, environmental tests and corresponding failure analyses were conducted to identify the failure mechanisms of FTO. An FTO thin film was prepared via spray pyrolysis deposition (SPD). Environmental tests were conducted in high-temperature and high-humidity environments, similar to field conditions. The degradation behavior and failure mechanisms were investigated using Hall-coefficient measurements, X-ray powder diffraction (XRD) analysis, and field-emission scanning electron microscopy (FE-SEM), before and after exposure to the test environments. A decrease in the carrier concentrations and electron mobilities of the FTO samples was observed after the tests. The analysis of the results revealed a decrease in the F concentration after the tests, resulting in a decrease in the carrier concentration. Moreover, the electron mobility decreased owing to the reduction in periodicity of the crystal attributed to F vacancies. Therefore, high-temperature and high-humidity conditions significantly decreased the durability of FTO. Future studies should consider the degradation of F in such environments and determine ways to prevent it.
{"title":"Failure Mechanisms of Fluorine-Doped Tin Oxide Thin Films in Glass and Reliability Tests","authors":"Jihee Bae;Hyoungseuk Choi","doi":"10.1109/TDMR.2023.3316774","DOIUrl":"10.1109/TDMR.2023.3316774","url":null,"abstract":"Fluorine-doped tin oxide (FTO) is a transparent conductive oxide that is used in solar cells and energy devices. In this study, environmental tests and corresponding failure analyses were conducted to identify the failure mechanisms of FTO. An FTO thin film was prepared via spray pyrolysis deposition (SPD). Environmental tests were conducted in high-temperature and high-humidity environments, similar to field conditions. The degradation behavior and failure mechanisms were investigated using Hall-coefficient measurements, X-ray powder diffraction (XRD) analysis, and field-emission scanning electron microscopy (FE-SEM), before and after exposure to the test environments. A decrease in the carrier concentrations and electron mobilities of the FTO samples was observed after the tests. The analysis of the results revealed a decrease in the F concentration after the tests, resulting in a decrease in the carrier concentration. Moreover, the electron mobility decreased owing to the reduction in periodicity of the crystal attributed to F vacancies. Therefore, high-temperature and high-humidity conditions significantly decreased the durability of FTO. Future studies should consider the degradation of F in such environments and determine ways to prevent it.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"461-467"},"PeriodicalIF":2.0,"publicationDate":"2023-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135501697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The radiation sensitivity of the Static Random-Access Memory (SRAM) device depends on the basic memory cell and peripheral circuits, and the influence of peripheral circuits is difficult to measure and classify, especially for the internal low dropout regulator (LDO) modules. In this paper, the LDO with radiation-tolerant bipolar bandgap was designed and fabricated to provide power supply for Fully Depleted Silicon on Insulator (FDSOI) SRAM test chips. The LDO induced Single Event Effects (SEE) for SRAM devices were investigated by pulsed laser and heavy ion irradiation tests. The simulation and irradiation results show that the hardened LDO has high SEE tolerance, while a few upset errors for memory units were induced by the transient turbulence of the internal LDO in test chips. The characterization results of LDOs provide specific insights into radiation sensitivity and impacts on the whole chips, and contribute to the full evaluation of high-reliable circuits and systems for space applications.
{"title":"Characterization of LDO Induced Increment of SEE Sensitivity for 22-nm FDSOI SRAM","authors":"Chang Cai;Yuzhu Liu;Minchi Hu;Gengshen Chen;Jun Yu","doi":"10.1109/TDMR.2023.3316625","DOIUrl":"10.1109/TDMR.2023.3316625","url":null,"abstract":"The radiation sensitivity of the Static Random-Access Memory (SRAM) device depends on the basic memory cell and peripheral circuits, and the influence of peripheral circuits is difficult to measure and classify, especially for the internal low dropout regulator (LDO) modules. In this paper, the LDO with radiation-tolerant bipolar bandgap was designed and fabricated to provide power supply for Fully Depleted Silicon on Insulator (FDSOI) SRAM test chips. The LDO induced Single Event Effects (SEE) for SRAM devices were investigated by pulsed laser and heavy ion irradiation tests. The simulation and irradiation results show that the hardened LDO has high SEE tolerance, while a few upset errors for memory units were induced by the transient turbulence of the internal LDO in test chips. The characterization results of LDOs provide specific insights into radiation sensitivity and impacts on the whole chips, and contribute to the full evaluation of high-reliable circuits and systems for space applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"537-543"},"PeriodicalIF":2.0,"publicationDate":"2023-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135501966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents $({I}_{ {s}}$ and ${I}_{ {d}}$ ), enabling the localization of interface traps $({N}_{ {it}})$ near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.
{"title":"Single Pulse Charge Pumping Technique Improvement for Interface-States Profiling in the Channel of MOSFET Devices","authors":"DhiaElhak Messaoud;Boualem Djezzar;Mohamed Boubaaya;Abdelmadjid Benabdelmoumene;Boumediene Zatout;Amel Chenouf;Abdelkader Zitouni","doi":"10.1109/TDMR.2023.3315931","DOIUrl":"10.1109/TDMR.2023.3315931","url":null,"abstract":"This paper presents the separated single pulse charge pumping (SSPCP) technique, an improvement over conventional single pulse charge pumping (CSPCP) for analyzing metal oxide semiconductor field-effect transistor (MOSFET) degradation. SSPCP separates the measurement of source and drain currents \u0000<inline-formula> <tex-math>$({I}_{ {s}}$ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>${I}_{ {d}}$ </tex-math></inline-formula>\u0000), enabling the localization of interface traps \u0000<inline-formula> <tex-math>$({N}_{ {it}})$ </tex-math></inline-formula>\u0000 near these regions. Experimental validation shows that SSPCP achieves comparable results to CSPCP with a maximum measurement error of 5%. The technique is particularly useful for studying stress-induced localized degradation profiling, allowing for the exploration of non-uniform stress (e.g., hot-carrier injection) and uniform stress (e.g., negative bias temperature instability) in transistors with short channels. SSPCP effectively analyzes localized degradation and identifies differences in stress-induced degradation between the source and drain regions, making it a valuable tool in semiconductor device characterization.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"23 4","pages":"521-529"},"PeriodicalIF":2.0,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135495236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-electron-mobility transistor (HEMT) based on Gallium Nitride (GaN) material is often designed for high-voltage operating conditions because of the high electric critical field of GaN material. However, such devices are often prone to the hot carrier stress (HCS) effect under high drain voltage and on-state conditions. Therefore, the HCS effect is an important consideration for reliable GaN HEMT devices. The Al2O3/Si3N4 bilayer gate dielectric AlGaN/GaN metal–insulator–semiconductor (MIS) HEMT has many advantages such as low gate leakage current and interface defects. However, the degradation phenomena observed in this device under HCS is very different from those of Si3N4 MIS HEMTs discussed in several reported studies. In this work, the HCS degradation results of Si3N4 MIS HEMTs and Al2O3/Si3N4 bilayer MIS HEMTs are both investigated and compared. The HCS degradations in Al2O3/Si3N4 bilayer MIS HEMTs are also examined and illustrated in depth. Finally, different stress voltage conditions of HCS are applied and the C-V measurements are carried out in order to confirm the degradation behaviors of MIS HEMT device.
基于氮化镓(GaN)材料的高电子迁移率晶体管(HEMT)通常被设计用于高压工作条件，因为氮化镓(GaN)材料具有高电临界场。然而，这种器件在高漏极电压和导通状态下往往容易产生热载流子应力(HCS)效应。因此，HCS效应是可靠GaN HEMT器件的重要考虑因素。Al2O3/Si3N4双层栅介质AlGaN/GaN金属绝缘体半导体HEMT具有栅漏电流小、界面缺陷少等优点。然而，该装置在HCS下观察到的降解现象与一些报道中讨论的Si3N4 MIS hemt有很大不同。本文对Si3N4 MIS hemt和Al2O3/Si3N4双层MIS hemt的HCS降解结果进行了研究和比较。HCS在Al2O3/Si3N4双层MIS hemt中的降解也进行了深入的研究和说明。最后，采用不同的HCS应力电压条件，进行了C-V测量，以确定MIS HEMT器件的退化行为。
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