Pub Date : 2024-09-19DOI: 10.1109/TDMR.2024.3463698
Shiwei Liang;Yu Yang;Jiaqi Chen;Lei Shu;Liang Wang;Jun Wang
Heavy ion strike-induced Single-Event Effect (SEE) is an essential reliability issue for SiC MOSFETs in radiation environments. The mass clustering of excess charges in SiC MOSFET is found to be root cause for device failure when heavy ion strikes. Based on the SEE failure mechanism, a planar gate SiC MOSFET with Hole Extraction Channel (HEC-MOS) and current aperture structure to improve its SEE immunity and electrical performance is proposed in this paper. The embedded $P^{+}$ pillar provides an additional path to extract excess holes during heavy ion radiation so that transient currents and SEE response time are greatly reduced. As a result, the maximum lattice temperature (hot spot) decreases by 768K, and a single-event burnout (SEB) threshold voltage of 624V is achieved with linear energy transfer (LET) value of 75MeV $cdot $ cm2/mg for HEC-MOS, which is 1.4 times higher than conventional SiC MOSFET (Conv-MOS). Moreover, the gate oxide electric field also decreases ~10 times owing to much less clustered holes in JFET region, which ensures HEC-MOS superior immunity to single-event gate rupture (SEGR). Apart from improving SEE performance, a better trade-off with its electrical performances is also considered. By adopting optimized parameters in current spreading layers and P+ pillar, the specific ON-resistance of HEC-MOS is reduced by 17.5% while maintain a good forward blocking capability and SEB immunity. Therefore, HEC-MOS is a promising candidate for harsh environmental applications.
{"title":"Improving Single-Event Effect Performance of SiC MOSFET by Excess Hole Extraction","authors":"Shiwei Liang;Yu Yang;Jiaqi Chen;Lei Shu;Liang Wang;Jun Wang","doi":"10.1109/TDMR.2024.3463698","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3463698","url":null,"abstract":"Heavy ion strike-induced Single-Event Effect (SEE) is an essential reliability issue for SiC MOSFETs in radiation environments. The mass clustering of excess charges in SiC MOSFET is found to be root cause for device failure when heavy ion strikes. Based on the SEE failure mechanism, a planar gate SiC MOSFET with Hole Extraction Channel (HEC-MOS) and current aperture structure to improve its SEE immunity and electrical performance is proposed in this paper. The embedded \u0000<inline-formula> <tex-math>$P^{+}$ </tex-math></inline-formula>\u0000 pillar provides an additional path to extract excess holes during heavy ion radiation so that transient currents and SEE response time are greatly reduced. As a result, the maximum lattice temperature (hot spot) decreases by 768K, and a single-event burnout (SEB) threshold voltage of 624V is achieved with linear energy transfer (LET) value of 75MeV\u0000<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>\u0000cm2/mg for HEC-MOS, which is 1.4 times higher than conventional SiC MOSFET (Conv-MOS). Moreover, the gate oxide electric field also decreases ~10 times owing to much less clustered holes in JFET region, which ensures HEC-MOS superior immunity to single-event gate rupture (SEGR). Apart from improving SEE performance, a better trade-off with its electrical performances is also considered. By adopting optimized parameters in current spreading layers and P+ pillar, the specific ON-resistance of HEC-MOS is reduced by 17.5% while maintain a good forward blocking capability and SEB immunity. Therefore, HEC-MOS is a promising candidate for harsh environmental applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"507-513"},"PeriodicalIF":2.5,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the increasing complexity of electromagnetic environments, receivers demand higher reliability from their internal components. To enhance the survivability of receivers, limiter circuits are commonly inserted at the backend of antennas to mitigate the damage caused by high-power interference pulses to subsequent sensitive components. The reliability of limiter circuits determines the stable operation of sensitive components at the backend, which holds significant implications for the overall reliability and robustness of navigation receivers. Given that Ultra-Wideband (UWB) pulse’s temporal characteristics typically last on the order of sub-nanoseconds, they can substantially influence the performance of limiter circuits. This study employs UWB-EMP as the interfering pulse to investigate the failure process and mechanism of the core device, GaAs-PIN diode, within the PIN limiter under UWB pulse exposure. Simulation results indicate that the failure of the diode’s conductivity modulation effect under UWB pulse exposure leads to the incapacity of the PIN limiter to function properly. Furthermore, the generation of multiple oscillatory pulses post-pulse exposure exacerbates the performance degradation of the PIN limiter. Experimental validations conducted via injection corroborate the simulation outcomes, demonstrating the impact of failure mechanisms and varying degrees of failure on normal signals within the PIN limiter.
{"title":"Reliability Analysis of GaAs-PIN Limiter Under Ultra-Wideband Pulse Radiation","authors":"Xuelin Yuan;Shengxian Chen;Yonglong Li;Ming Hu;Teng Zhou","doi":"10.1109/TDMR.2024.3456832","DOIUrl":"10.1109/TDMR.2024.3456832","url":null,"abstract":"With the increasing complexity of electromagnetic environments, receivers demand higher reliability from their internal components. To enhance the survivability of receivers, limiter circuits are commonly inserted at the backend of antennas to mitigate the damage caused by high-power interference pulses to subsequent sensitive components. The reliability of limiter circuits determines the stable operation of sensitive components at the backend, which holds significant implications for the overall reliability and robustness of navigation receivers. Given that Ultra-Wideband (UWB) pulse’s temporal characteristics typically last on the order of sub-nanoseconds, they can substantially influence the performance of limiter circuits. This study employs UWB-EMP as the interfering pulse to investigate the failure process and mechanism of the core device, GaAs-PIN diode, within the PIN limiter under UWB pulse exposure. Simulation results indicate that the failure of the diode’s conductivity modulation effect under UWB pulse exposure leads to the incapacity of the PIN limiter to function properly. Furthermore, the generation of multiple oscillatory pulses post-pulse exposure exacerbates the performance degradation of the PIN limiter. Experimental validations conducted via injection corroborate the simulation outcomes, demonstrating the impact of failure mechanisms and varying degrees of failure on normal signals within the PIN limiter.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"487-497"},"PeriodicalIF":2.5,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/TDMR.2024.3457728
Uttara Chakraborty;Duane S. Boning;Carl V. Thompson
Estimating the reliability of electronic devices involves identification of failure mechanisms and prediction of lifetimes. For parameter estimation and failure mode identification in Weibull competing-risks models, a differential-evolution-based global optimization approach has recently been developed, with the superiority of that approach demonstrated over the best-known local methods for the problem. In an effort to design a method faster than differential evolution for this problem, the present paper develops a new type of expectation maximization (EM) algorithm that is capable of handling bound constraints while optimizing the parameters of the Weibull component distributions. The differential-evolution-based approach guarantees a feasible, but not necessarily high-quality, solution in every run, while the proposed method offers no such guarantee. Despite this lack of guarantee, the proposed method is seen to produce results of a quality highly competitive with differential evolution. Numerical results on ten test cases, based on three real test datasets and two synthetic datasets, show that in terms of solution quality, the proposed method is competitive with differential evolution, while offering an average savings of about 64% in the computation time. Comparative performance analyses with the standard EM algorithm and the best-known local method L-BFGS-B are also provided. The numerical results are statistically validated. A new approach to model improvement via selective failure analysis is demonstrated as an application of the proposed algorithm. The proposed algorithm has the potential to be used for general-purpose likelihood maximization involving latent variables in diverse domains.
{"title":"Bound-Constrained Expectation Maximization for Weibull Competing-Risks Device Reliability","authors":"Uttara Chakraborty;Duane S. Boning;Carl V. Thompson","doi":"10.1109/TDMR.2024.3457728","DOIUrl":"10.1109/TDMR.2024.3457728","url":null,"abstract":"Estimating the reliability of electronic devices involves identification of failure mechanisms and prediction of lifetimes. For parameter estimation and failure mode identification in Weibull competing-risks models, a differential-evolution-based global optimization approach has recently been developed, with the superiority of that approach demonstrated over the best-known local methods for the problem. In an effort to design a method faster than differential evolution for this problem, the present paper develops a new type of expectation maximization (EM) algorithm that is capable of handling bound constraints while optimizing the parameters of the Weibull component distributions. The differential-evolution-based approach guarantees a feasible, but not necessarily high-quality, solution in every run, while the proposed method offers no such guarantee. Despite this lack of guarantee, the proposed method is seen to produce results of a quality highly competitive with differential evolution. Numerical results on ten test cases, based on three real test datasets and two synthetic datasets, show that in terms of solution quality, the proposed method is competitive with differential evolution, while offering an average savings of about 64% in the computation time. Comparative performance analyses with the standard EM algorithm and the best-known local method L-BFGS-B are also provided. The numerical results are statistically validated. A new approach to model improvement via selective failure analysis is demonstrated as an application of the proposed algorithm. The proposed algorithm has the potential to be used for general-purpose likelihood maximization involving latent variables in diverse domains.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"556-570"},"PeriodicalIF":2.5,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-09DOI: 10.1109/TDMR.2024.3456095
Cheng-Hao Yu;Hui Yang;Wen-Sheng Zhao;Da-Wei Wang;Hao-Min Guo;Yue Hu;Xiao-Dong Wu;Xin Tan
This paper presents the 2-D numerical simulation results of the ion-induced single-event burnout (SEB) in the conventional gallium-oxide (Ga2O3) Schottky barrier diode (SBD), conventional Ga2O3 heterojunction diode (HJD), and Ga2O3 HJD with a p-NiO junction termination extension (JTE) and a small-angle beveled field plate (BFP). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics in experiments. The simulation results of SEB failure mechanism and threshold voltage in the conventional Ga2O3 SBD are proved by the chlorine (Cl) ion irradiation tests. The most sensitive position and the ion range influence to induce an SEB are discussed. Then, the SEB failure mechanism and threshold voltage of conventional Ga2O3 HJD are comparatively investigated based on the Cl ion strike. Although, the conventional HJD presents much better SEB performance than conventional SBD in anode position, the anode edge of HJD is proved to be very sensitive to an ion. Therefore, the Ga2O3 HJD with JTE and BFP, which can significantly suppress the peak electric field strength at the anode edge, is investigated that has better SEB performance than the conventional SBD and HJD under different ion species.
{"title":"Research of Single-Event Burnout in P-NiO/n-Ga2O3 Heterojunction Diode","authors":"Cheng-Hao Yu;Hui Yang;Wen-Sheng Zhao;Da-Wei Wang;Hao-Min Guo;Yue Hu;Xiao-Dong Wu;Xin Tan","doi":"10.1109/TDMR.2024.3456095","DOIUrl":"10.1109/TDMR.2024.3456095","url":null,"abstract":"This paper presents the 2-D numerical simulation results of the ion-induced single-event burnout (SEB) in the conventional gallium-oxide (Ga2O3) Schottky barrier diode (SBD), conventional Ga2O3 heterojunction diode (HJD), and Ga2O3 HJD with a p-NiO junction termination extension (JTE) and a small-angle beveled field plate (BFP). The employed simulation physics models and material parameters are validated by the reverse I-V characteristics in experiments. The simulation results of SEB failure mechanism and threshold voltage in the conventional Ga2O3 SBD are proved by the chlorine (Cl) ion irradiation tests. The most sensitive position and the ion range influence to induce an SEB are discussed. Then, the SEB failure mechanism and threshold voltage of conventional Ga2O3 HJD are comparatively investigated based on the Cl ion strike. Although, the conventional HJD presents much better SEB performance than conventional SBD in anode position, the anode edge of HJD is proved to be very sensitive to an ion. Therefore, the Ga2O3 HJD with JTE and BFP, which can significantly suppress the peak electric field strength at the anode edge, is investigated that has better SEB performance than the conventional SBD and HJD under different ion species.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"480-486"},"PeriodicalIF":2.5,"publicationDate":"2024-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142223806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TDMR.2024.3445849
{"title":"Blank Page","authors":"","doi":"10.1109/TDMR.2024.3445849","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3445849","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"C4-C4"},"PeriodicalIF":2.5,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668831","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Correction to “Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130 nm to 28 nm Nodes and Beyond”","authors":"Tidjani Garba-Seybou;Xavier Federspiel;Joycelyn Hai;Cheikh Diouf;Florian Cacho;Alain Bravaix","doi":"10.1109/TDMR.2024.3429780","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3429780","url":null,"abstract":"In \u0000<xref>[1]</xref>\u0000, \u0000<xref>(4)</xref>\u0000 should appear as","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"466-466"},"PeriodicalIF":2.5,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668825","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TDMR.2024.3424970
{"title":"Bridging the Data Gap in Photovoltaics with Synthetic Data Generation","authors":"","doi":"10.1109/TDMR.2024.3424970","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3424970","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"467-468"},"PeriodicalIF":2.5,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668842","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TDMR.2024.3445848
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2024.3445848","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3445848","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"C3-C3"},"PeriodicalIF":2.5,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668821","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TDMR.2024.3445828
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2024.3445828","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3445828","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"C2-C2"},"PeriodicalIF":2.5,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668822","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142143596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the interconnected structure of 3D chip, through-silicon via undertakes the key functions in energy transmission, mechanical support and signal transmission of 3D chip. With the increasing of TSV interconnection density, the reliability of TSV is becoming increasingly prominent, and the slight variation of TSV dimension may exert severe impact on the fatigue life of the TSV array. In this study, a typical double-layer TSV interconnected 3D array is built to carried out the multi-interface fatigue analysis under thermoelectric structure coupling field, the influence of different dimension of the TSV interconnected array on the fatigue life of various interface and whole thermoelectric circuit are deeply investigated. Results shows that: 1) relatively small or large diameter of TSV-Cu or Bump can effectively improve the fatigue life of Bump-RDL interface. 2) The fatigue life of the top interface between TSV-Cu and SiO2 layer is slightly higher than that of the bottom interface. 3) The optimal dimension combination of TSV interconnected array is highly related with external working environment and own working state. Under the condition of this study, the dimension corresponding to Case 0 (TSV-Cu diameter: $5~mu $ m, Bump diameter: $10~mu $ m, Pitch: $100~mu $ m, SiO2 layer thickness: $1~mu $ m) is the optimal solution. 4) TSV-Cu diameter and SiO2 thickness have the greatest influence on the fatigue life of TSV array. Relevant results can provide valuable references for locating the weak points of the TSV interconnected array and the subsequent optimization design.
{"title":"Dimension Influence on the Interface Fatigue Characteristics of Three-Dimensional TSV Array: A Fully Coupled Thermal-Electrical-Structural Analysis","authors":"Kaihong Hou;Zhengwei Fan;Shufeng Zhang;Yashun Wang;Xun Chen","doi":"10.1109/TDMR.2024.3453923","DOIUrl":"10.1109/TDMR.2024.3453923","url":null,"abstract":"As the interconnected structure of 3D chip, through-silicon via undertakes the key functions in energy transmission, mechanical support and signal transmission of 3D chip. With the increasing of TSV interconnection density, the reliability of TSV is becoming increasingly prominent, and the slight variation of TSV dimension may exert severe impact on the fatigue life of the TSV array. In this study, a typical double-layer TSV interconnected 3D array is built to carried out the multi-interface fatigue analysis under thermoelectric structure coupling field, the influence of different dimension of the TSV interconnected array on the fatigue life of various interface and whole thermoelectric circuit are deeply investigated. Results shows that: 1) relatively small or large diameter of TSV-Cu or Bump can effectively improve the fatigue life of Bump-RDL interface. 2) The fatigue life of the top interface between TSV-Cu and SiO2 layer is slightly higher than that of the bottom interface. 3) The optimal dimension combination of TSV interconnected array is highly related with external working environment and own working state. Under the condition of this study, the dimension corresponding to Case 0 (TSV-Cu diameter: \u0000<inline-formula> <tex-math>$5~mu $ </tex-math></inline-formula>\u0000m, Bump diameter: \u0000<inline-formula> <tex-math>$10~mu $ </tex-math></inline-formula>\u0000m, Pitch: \u0000<inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula>\u0000m, SiO2 layer thickness: \u0000<inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>\u0000m) is the optimal solution. 4) TSV-Cu diameter and SiO2 thickness have the greatest influence on the fatigue life of TSV array. Relevant results can provide valuable references for locating the weak points of the TSV interconnected array and the subsequent optimization design.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"571-583"},"PeriodicalIF":2.5,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142181555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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