This study presents YOLOv11n-GhostLite, an innovative lightweight deep learning architecture optimized for real-time localization of photovoltaic (PV) faults in electroluminescence (EL) images, specifically designed for edge deployment. A Deep Convolutional Generative Adversarial Network (DCGAN)-based synthetic augmentation pipeline is presented to address the issues of class imbalance and limited resource availability, generating high-fidelity, class-conditional EL images that include realistic banding artifacts. This method enhances the representation of minority defect categories by more than 150%, elevating the mean Average Precision (mAP@50) by 4% and decreasing false negatives by 5%. The proposed model incorporates GhostConv for efficient early feature extraction, C3k2 residual blocks for deep representation learning, GhostSPPF for multi-scale context aggregation, C2PSA attention for adaptive feature refinement, and an anchor-free detection head, achieving high performance with only 2.34 million parameters and 6.2 GFLOPs. Detailed experiments on two benchmark datasets PVEL-AD and PV Multi-Defect exhibit the model’s efficacy, attaining 97.2% mAP@50 on PVEL-AD, and 96.4% mAP@50 on PV Multi-Defect, outperforming larger models in both accuracy and speed. The model is further deployed on a Google Coral Edge TPU, demonstrating its real-time functionality with minimal power consumption (~2W) and suitable latency for drone-based solar inspections. YOLOv11n-GhostLite’s integration of efficient architecture and data-driven augmentation renders it an effective solution for scalable, real-time photovoltaic fault detection in resource-limited settings.
{"title":"DCGAN-Driven Minority Class Augmentation for Lightweight YOLO-Based Photovoltaic Defect Localization Suitable for Edge Deployment","authors":"Nakka Saampotth Maddileti;Rupesh Namburi;Rayappa David Amar Raj;Rama Muni Reddy Yanamala;Archana Pallakonda","doi":"10.1109/TDMR.2025.3592416","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3592416","url":null,"abstract":"This study presents YOLOv11n-GhostLite, an innovative lightweight deep learning architecture optimized for real-time localization of photovoltaic (PV) faults in electroluminescence (EL) images, specifically designed for edge deployment. A Deep Convolutional Generative Adversarial Network (DCGAN)-based synthetic augmentation pipeline is presented to address the issues of class imbalance and limited resource availability, generating high-fidelity, class-conditional EL images that include realistic banding artifacts. This method enhances the representation of minority defect categories by more than 150%, elevating the mean Average Precision (mAP@50) by 4% and decreasing false negatives by 5%. The proposed model incorporates GhostConv for efficient early feature extraction, C3k2 residual blocks for deep representation learning, GhostSPPF for multi-scale context aggregation, C2PSA attention for adaptive feature refinement, and an anchor-free detection head, achieving high performance with only 2.34 million parameters and 6.2 GFLOPs. Detailed experiments on two benchmark datasets PVEL-AD and PV Multi-Defect exhibit the model’s efficacy, attaining 97.2% mAP@50 on PVEL-AD, and 96.4% mAP@50 on PV Multi-Defect, outperforming larger models in both accuracy and speed. The model is further deployed on a Google Coral Edge TPU, demonstrating its real-time functionality with minimal power consumption (~2W) and suitable latency for drone-based solar inspections. YOLOv11n-GhostLite’s integration of efficient architecture and data-driven augmentation renders it an effective solution for scalable, real-time photovoltaic fault detection in resource-limited settings.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"742-751"},"PeriodicalIF":2.3,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-21DOI: 10.1109/TDMR.2025.3590736
Weidan Li;Mingmin Huang;Min Gong
A trench gate lateral insulated gate bipolar transistor with an extra hole path (HP LIGBT) is proposed to ease the current concentration around the trench gate so as to suppress single-event burnout (SEB) and reduce the maximum electric field at the gate oxide so as to lower the risk of single-event gate rupture (SEGR). The SEB position of the trench gate LIGBT in comparison with the trench gate laterally diffused metal-oxide semiconductor (LDMOS) is studied by TCAD simulations with lattice heating model, where the former fails around the trench gate but the latter fails at the drain contact. The most sensitive position for inducing SEB is found to be both at the n-drift region near the emitter or source side. Simulation results show that the threshold voltage of triggering SEB of the HP LIGBT for ion species with high linear energy transfer (LET) values of 76.56 MeV$cdot $ cm2/mg can be 46% higher than that of the conventional LIGBT. Moreover, the maximum electric field at the gate oxide of HP LIGBT is 55% lower than the conventional LIGBT.
{"title":"A Novel Single Event Irradiation-Hardened SOI Trench Gate LIGBT","authors":"Weidan Li;Mingmin Huang;Min Gong","doi":"10.1109/TDMR.2025.3590736","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590736","url":null,"abstract":"A trench gate lateral insulated gate bipolar transistor with an extra hole path (HP LIGBT) is proposed to ease the current concentration around the trench gate so as to suppress single-event burnout (SEB) and reduce the maximum electric field at the gate oxide so as to lower the risk of single-event gate rupture (SEGR). The SEB position of the trench gate LIGBT in comparison with the trench gate laterally diffused metal-oxide semiconductor (LDMOS) is studied by TCAD simulations with lattice heating model, where the former fails around the trench gate but the latter fails at the drain contact. The most sensitive position for inducing SEB is found to be both at the n-drift region near the emitter or source side. Simulation results show that the threshold voltage of triggering SEB of the HP LIGBT for ion species with high linear energy transfer (LET) values of 76.56 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg can be 46% higher than that of the conventional LIGBT. Moreover, the maximum electric field at the gate oxide of HP LIGBT is 55% lower than the conventional LIGBT.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"692-697"},"PeriodicalIF":2.3,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-18DOI: 10.1109/TDMR.2025.3590371
Zhaohui Qin;Lei Dong;Lan Chen;Renjie Lu;Rong Chen;Yali Wang
With device dimensions shrink, traditional plane-field effect transistors no longer meet the demands of the development. As a novel type of three-dimensional device, 14 nm SOI FinFETs has been widely research attention and application due to the superior performance. However, Hot Carrier Injection (HCI) at different temperatures and its synergistic effect with Self-Heating Effect (SHE) synergistic effects have serious effects on the reliability of 14 nm SOI FinFETs and need to be solved. Therefore, this work uses Technology Computer-Aided Design to explore the electrical performance degradation of the 14 nm SOI FinFETs to reveal the damage mechanism. Simulation results demonstrate the threshold voltage shift and electron mobility decrease of the device. The increase in ambient temperature and the rise in lattice temperature induced by SHE will exacerbate the HCI effect, resulting in more hot charge carriers being injected into the gate oxide layer. Based on results, achieving more efficient thermal management by enhancing the heat dissipation performance of the drain and its extended regions can provide important theoretical support for reliability design.
随着器件尺寸的不断缩小，传统的平面场效应晶体管已不能满足发展的要求。14nm SOI finfet作为一种新型的三维器件，由于其优越的性能得到了广泛的研究和应用。然而，不同温度下的热载流子注入（HCI）及其与自热效应（SHE）的协同效应严重影响了14nm SOI finfet的可靠性，需要解决。因此，本研究利用计算机辅助设计技术来探讨14nm SOI finfet的电性能退化，以揭示其损伤机制。仿真结果表明，该器件的阈值电压偏移和电子迁移率降低。环境温度的升高和SHE引起的晶格温度的升高会加剧HCI效应，导致更多的热荷载流子被注入栅极氧化层。研究结果表明，通过提高排水孔及其延伸区域的散热性能来实现更高效的热管理，可以为可靠性设计提供重要的理论支持。
{"title":"Degradation Analysis of 14 nm SOI FinFETs by Influence of Hot Carrier Injection and Self-Heating Synergistic Effects","authors":"Zhaohui Qin;Lei Dong;Lan Chen;Renjie Lu;Rong Chen;Yali Wang","doi":"10.1109/TDMR.2025.3590371","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590371","url":null,"abstract":"With device dimensions shrink, traditional plane-field effect transistors no longer meet the demands of the development. As a novel type of three-dimensional device, 14 nm SOI FinFETs has been widely research attention and application due to the superior performance. However, Hot Carrier Injection (HCI) at different temperatures and its synergistic effect with Self-Heating Effect (SHE) synergistic effects have serious effects on the reliability of 14 nm SOI FinFETs and need to be solved. Therefore, this work uses Technology Computer-Aided Design to explore the electrical performance degradation of the 14 nm SOI FinFETs to reveal the damage mechanism. Simulation results demonstrate the threshold voltage shift and electron mobility decrease of the device. The increase in ambient temperature and the rise in lattice temperature induced by SHE will exacerbate the HCI effect, resulting in more hot charge carriers being injected into the gate oxide layer. Based on results, achieving more efficient thermal management by enhancing the heat dissipation performance of the drain and its extended regions can provide important theoretical support for reliability design.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"659-667"},"PeriodicalIF":2.3,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145028009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, the effects of 2 MeV-proton irradiation on the electrical characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) are investigated. The device characteristics suddenly degraded for proton fluences exceeding $1times 10{^{{13}}}$ cm−2 and almost functionally failed for proton fluences reaches $1times 10{^{{14}}}$ cm${}^{-}2 $ . The increase in base current is directly responsible for the degradation of current gain. It was demonstrated that the reciprocal gain of irradiated InP/InGaAs DHBTs exhibits an exponential relationship with proton fluence over a broader fluence range below $5times 10{^{{13}}}$ cm${}^{-}2 $ , rather than a linear relationship as described by the Messenger-Spratt equation. The analysis of base current components and micro-Raman spectrums indicates that the electrostatic-potential modulation effect of irradiated defects as charged centers on the BE junction is the main cause of gain degradation. Furthermore, a comparison with irradiation effects of other bipolar transistors enhances our understanding of the varied impact of radiation-induced defects on the gain degradation across different transistor architectures.
本文研究了2mev质子辐照对InP/InGaAs双异质结双极晶体管（dhbt）电特性的影响。当质子影响超过$1乘以10{^{{13}}}$ cm−2时，器件特性突然退化，当质子影响达到$1乘以10{^{{13}}}$ cm ${}^{-}2 $时，器件几乎失效。基极电流的增加直接导致电流增益的降低。结果表明，辐照的InP/InGaAs dhbt的互反增益与质子能量的关系在5乘以10{^{{13}}}$ cm ${}^{-}2 $以下的较宽能量范围内呈指数关系，而不是像messinger - spratt方程所描述的线性关系。基极电流分量和微拉曼光谱分析表明，辐照缺陷作为带电中心在BE结上的静电电位调制效应是导致增益下降的主要原因。此外，与其他双极晶体管的辐照效应的比较增强了我们对辐射诱导缺陷对不同晶体管结构的增益退化的不同影响的理解。
{"title":"Exponential Gain Degradation Behavior on Irradiated InP/InGaAs Double Heterojunction Bipolar Transistors","authors":"Jialin Zhang;Yongbo Su;Bo Mei;Feng Yang;Zhi Jin;Yinghui Zhong","doi":"10.1109/TDMR.2025.3590272","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3590272","url":null,"abstract":"In this paper, the effects of 2 MeV-proton irradiation on the electrical characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) are investigated. The device characteristics suddenly degraded for proton fluences exceeding <inline-formula> <tex-math>$1times 10{^{{13}}}$ </tex-math></inline-formula> cm−2 and almost functionally failed for proton fluences reaches <inline-formula> <tex-math>$1times 10{^{{14}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-}2 $ </tex-math></inline-formula>. The increase in base current is directly responsible for the degradation of current gain. It was demonstrated that the reciprocal gain of irradiated InP/InGaAs DHBTs exhibits an exponential relationship with proton fluence over a broader fluence range below <inline-formula> <tex-math>$5times 10{^{{13}}}$ </tex-math></inline-formula> cm<inline-formula> <tex-math>${}^{-}2 $ </tex-math></inline-formula>, rather than a linear relationship as described by the Messenger-Spratt equation. The analysis of base current components and micro-Raman spectrums indicates that the electrostatic-potential modulation effect of irradiated defects as charged centers on the BE junction is the main cause of gain degradation. Furthermore, a comparison with irradiation effects of other bipolar transistors enhances our understanding of the varied impact of radiation-induced defects on the gain degradation across different transistor architectures.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"452-459"},"PeriodicalIF":2.3,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-16DOI: 10.1109/TDMR.2025.3589784
Wangyong Chen;Zhengxin Zhang;Jianwen Lin;Linlin Cai
With the scaling of integrated circuit technologies, charge-sharing effects induced by single-event transient (SET) have become a critical reliability concern in radiation environments. However, conventional circuit-level SET simulation methodologies fail to account for charge-sharing mechanisms among adjacent devices. This work proposes a physics-aware simulation framework combining technology computer-aided design (TCAD) device simulations and circuit-level modeling to address this limitation. The methodology involves extracting transient current waveform parameters through 3D TCAD simulations under varied ion strike locations. Spatially-dependent behavioral models are then developed via multivariate regression of these parameters, which are subsequently integrated into bias-dependent SET analytical models. To enable circuit-level analysis, built-in current sources characterized by the developed models are inserted at sensitive nodes during layout-aware simulations. The proposed approach is validated through comparative analysis between TCAD mixed-mode simulations and circuit-level predictions in a 12-nm FinFET test structure, demonstrating smaller deviation in critical SET metrics. Compared to existing methods, this co-simulation strategy incorporates both charge-sharing effects and bias voltage dependencies while maintaining computational efficiency. The implemented framework enables early-stage evaluation of radiation-induced soft errors during physical design phases, providing critical insights for radiation-hardened-by-design strategies in advanced process nodes.
{"title":"A Comprehensive Modeling Framework for Charge-Sharing and Bias-Dependent Single Event Transient Prediction in FinFETs","authors":"Wangyong Chen;Zhengxin Zhang;Jianwen Lin;Linlin Cai","doi":"10.1109/TDMR.2025.3589784","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3589784","url":null,"abstract":"With the scaling of integrated circuit technologies, charge-sharing effects induced by single-event transient (SET) have become a critical reliability concern in radiation environments. However, conventional circuit-level SET simulation methodologies fail to account for charge-sharing mechanisms among adjacent devices. This work proposes a physics-aware simulation framework combining technology computer-aided design (TCAD) device simulations and circuit-level modeling to address this limitation. The methodology involves extracting transient current waveform parameters through 3D TCAD simulations under varied ion strike locations. Spatially-dependent behavioral models are then developed via multivariate regression of these parameters, which are subsequently integrated into bias-dependent SET analytical models. To enable circuit-level analysis, built-in current sources characterized by the developed models are inserted at sensitive nodes during layout-aware simulations. The proposed approach is validated through comparative analysis between TCAD mixed-mode simulations and circuit-level predictions in a 12-nm FinFET test structure, demonstrating smaller deviation in critical SET metrics. Compared to existing methods, this co-simulation strategy incorporates both charge-sharing effects and bias voltage dependencies while maintaining computational efficiency. The implemented framework enables early-stage evaluation of radiation-induced soft errors during physical design phases, providing critical insights for radiation-hardened-by-design strategies in advanced process nodes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"520-527"},"PeriodicalIF":2.3,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node. Three primary sources of variability work function variation (WFV), line width roughness (LWR), and gate edge roughness (GER) are systematically analyzed. By extracting and calibrating empirical parameters, the proposed model accurately captures the statistical trends of process-induced fluctuations across a broad range of conditions. The model is integrated into the BSIM-CMG framework for circuit-level variability assessment, enabling comprehensive evaluation of performance deviations. Simulation results indicate that WFV dominates the overall reliability degradation, leading to energy variations from -12% to +24%. This study provides a refined predictive framework for assessing process-induced reliability risks and optimizing circuit design in advanced semiconductor technologies.
{"title":"Compact Modeling of Process Variation and Reliability Predictions for Nanosheet Gate-All-Around FET","authors":"Mengge Jin;Chao Wang;Siyi Xu;Yang Shen;Yuhang Zhang;Bingyi Ye;Shaoqiang Chen;Xinyu Dong;Fei Lu;Ziyu Liu;Xiaojin Li;Yanling Shi;Yabin Sun","doi":"10.1109/TDMR.2025.3589379","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3589379","url":null,"abstract":"In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node. Three primary sources of variability work function variation (WFV), line width roughness (LWR), and gate edge roughness (GER) are systematically analyzed. By extracting and calibrating empirical parameters, the proposed model accurately captures the statistical trends of process-induced fluctuations across a broad range of conditions. The model is integrated into the BSIM-CMG framework for circuit-level variability assessment, enabling comprehensive evaluation of performance deviations. Simulation results indicate that WFV dominates the overall reliability degradation, leading to energy variations from -12% to +24%. This study provides a refined predictive framework for assessing process-induced reliability risks and optimizing circuit design in advanced semiconductor technologies.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"707-713"},"PeriodicalIF":2.3,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-07DOI: 10.1109/TDMR.2025.3586592
Guang-Chao Lyu;Min-Bo Zhou;Xin-Ping Zhang
Cracking at corner points or edges of multi-material interfaces has long been a critical reliability concern for engineered components and structures. In particular, accurate prediction of failure risks due to interface crack and delamination in advanced electronic packages is highly demanded for improvement of the reliability and the integrated circuit (IC) product yield. This study proposes a new approach, which combines the asymptotic stress solution at the singularity with the maximum average tangential stress (MATS) and maximum tangential strain (MTSN) criteria, to predict the crack initiation angle and critical fracture conditions. The proposed approach is first validated against the experimental results for silicon/glass anode bonds subjected to biased three-point bending as reported in the literature, demonstrating its accuracy and reliability. Further, and more importantly, the validated criteria are applied to analyze the cracking behavior of a typical molded underfill flip-chip (MUF FC) package under both heating and cooling loads. The predicted crack initiation angles are close to the analytical results derived from the fracture mechanics parameters obtained by finite element analysis. The present study has moved the reliability assessment forward to establish a practical and reliable framework for predicting the crack initiation at the interface corner of the MUF FC package structure, which is also highly anticipated to be used in other advanced electronic packages.
{"title":"Application of New Criteria for Predicting Crack Initiation From the Interface Corner in the Molded Underfill Flip-Chip Package Under Thermal Load","authors":"Guang-Chao Lyu;Min-Bo Zhou;Xin-Ping Zhang","doi":"10.1109/TDMR.2025.3586592","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3586592","url":null,"abstract":"Cracking at corner points or edges of multi-material interfaces has long been a critical reliability concern for engineered components and structures. In particular, accurate prediction of failure risks due to interface crack and delamination in advanced electronic packages is highly demanded for improvement of the reliability and the integrated circuit (IC) product yield. This study proposes a new approach, which combines the asymptotic stress solution at the singularity with the maximum average tangential stress (MATS) and maximum tangential strain (MTSN) criteria, to predict the crack initiation angle and critical fracture conditions. The proposed approach is first validated against the experimental results for silicon/glass anode bonds subjected to biased three-point bending as reported in the literature, demonstrating its accuracy and reliability. Further, and more importantly, the validated criteria are applied to analyze the cracking behavior of a typical molded underfill flip-chip (MUF FC) package under both heating and cooling loads. The predicted crack initiation angles are close to the analytical results derived from the fracture mechanics parameters obtained by finite element analysis. The present study has moved the reliability assessment forward to establish a practical and reliable framework for predicting the crack initiation at the interface corner of the MUF FC package structure, which is also highly anticipated to be used in other advanced electronic packages.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"723-733"},"PeriodicalIF":2.3,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-30DOI: 10.1109/TDMR.2025.3581148
Shi-Kai Shi;Han-Lin Zhao;Xiao-Lin Wang;Sung-Jin Kim
In this paper, channel layer films of indium oxide (In2O3) solution doped with molybdenum disulfide (MoS2) were prepared at low temperature (250°C). Then the electrical properties of thin-film transistors (TFTs) devices were investigated using ultraviolet/ozone (UV/Ozone) treatment process. The results show that the selection of the appropriate time for the UV/Ozone treatment process can effectively improve the electrical properties of In2O3-MoS2 TFTs devices, leading to the preparation of reliable electronic devices at low temperatures. Specifically, the 40 s UV/Ozone treatment TFTs have relatively high saturation mobility of $2.08~pm ~0.02$ cm2V${}^{-}1 $ s${}^{-}1 $ and on/off current ratio of $3.09times 10{^{{6}}}$ , as well as relatively low threshold voltage and subthreshold swing values of $3.74~pm ~0.03$ V and $0.61~pm ~0.01$ V, and stable electrical properties after 30 days of exposure to ambient air. The UV/Ozone treatment resulted in stable electrical characteristics compared to devices that were not treated with the process, which has potential in electronics applications and is expected to be widely used in semiconductors for a variety of emerging electronic devices.
{"title":"Solution-Processed In₂O₃ Doped 2-D MoS₂ Thin-Film Transistors With Improvement of Electrical Properties by UV/Ozone Treatment","authors":"Shi-Kai Shi;Han-Lin Zhao;Xiao-Lin Wang;Sung-Jin Kim","doi":"10.1109/TDMR.2025.3581148","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3581148","url":null,"abstract":"In this paper, channel layer films of indium oxide (In2O3) solution doped with molybdenum disulfide (MoS2) were prepared at low temperature (250°C). Then the electrical properties of thin-film transistors (TFTs) devices were investigated using ultraviolet/ozone (UV/Ozone) treatment process. The results show that the selection of the appropriate time for the UV/Ozone treatment process can effectively improve the electrical properties of In2O3-MoS2 TFTs devices, leading to the preparation of reliable electronic devices at low temperatures. Specifically, the 40 s UV/Ozone treatment TFTs have relatively high saturation mobility of <inline-formula> <tex-math>$2.08~pm ~0.02$ </tex-math></inline-formula> cm2V<inline-formula> <tex-math>${}^{-}1 $ </tex-math></inline-formula> s<inline-formula> <tex-math>${}^{-}1 $ </tex-math></inline-formula> and on/off current ratio of <inline-formula> <tex-math>$3.09times 10{^{{6}}}$ </tex-math></inline-formula>, as well as relatively low threshold voltage and subthreshold swing values of <inline-formula> <tex-math>$3.74~pm ~0.03$ </tex-math></inline-formula> V and <inline-formula> <tex-math>$0.61~pm ~0.01$ </tex-math></inline-formula> V, and stable electrical properties after 30 days of exposure to ambient air. The UV/Ozone treatment resulted in stable electrical characteristics compared to devices that were not treated with the process, which has potential in electronics applications and is expected to be widely used in semiconductors for a variety of emerging electronic devices.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"594-600"},"PeriodicalIF":2.3,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance of perovskite/silicon tandem solar cells (PTSCs) has achieved remarkable progress in recent years, showing the great potential of commercialization. Nevertheless, the operational stability of PTSC modules under real working conditions remains poorly understood. In this study, we investigated the module stability by connecting individual PTSCs. Evident hot spot effect caused by partial light occlusion was firstly observed in PTSCs. Moreover, the module exhibited a rapid output power degradation under maximum power point tracking (MPPT) condition, but it spontaneously recovers to initial output power within one minute in dark environment. Impressively, the module stability improves significantly after several MPPT cycles. These findings provide critical insights into the stability mechanisms of PTSC modules and offer practical guidelines for improving the performance in future applications.
{"title":"Metastable Operating Stability of Perovskite/Silicon Tandem Solar Cell Modules","authors":"Zhenzhu Zhao;Fei Wang;Pengxu Chen;Mulin Sun;Yuhui Ji;Yutao Wang;Shuangbiao Xia;Na Wang;Fan Xu;Hanlin Hu;Kexin Yao;Liping Zhang;Jian Yu;Honghai Xiao;Chen Yang;Zhengxin Liu;Jiakai Liu;Qin Hu;Wenzhu Liu","doi":"10.1109/TDMR.2025.3583339","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3583339","url":null,"abstract":"The performance of perovskite/silicon tandem solar cells (PTSCs) has achieved remarkable progress in recent years, showing the great potential of commercialization. Nevertheless, the operational stability of PTSC modules under real working conditions remains poorly understood. In this study, we investigated the module stability by connecting individual PTSCs. Evident hot spot effect caused by partial light occlusion was firstly observed in PTSCs. Moreover, the module exhibited a rapid output power degradation under maximum power point tracking (MPPT) condition, but it spontaneously recovers to initial output power within one minute in dark environment. Impressively, the module stability improves significantly after several MPPT cycles. These findings provide critical insights into the stability mechanisms of PTSC modules and offer practical guidelines for improving the performance in future applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"654-658"},"PeriodicalIF":2.3,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-20DOI: 10.1109/TDMR.2025.3581604
Nitish Kumar;Ankur Gupta;Pushpapraj Singh
The uniaxial tensile mechanical stress (MS) is induced up to 1.4 GPa on the channel of the twin junctionless nanowire (JL-NW) gate-all-around (GAA) field-effect transistors (FETs) using a four-point bending technique. The variation of the electrical parameters is measured before and during induced MS to analyze the performance. The ON-state current, carrier mobility, threshold voltage, and subthreshold swing are directly proportional to the induced MS due to the reduced energy band gap and intervalley scattering effect. The reduced subthreshold swing indicates low power consumption and better switching ability, whereas the higher OFF-state current leads to slightly increased standby power consumption, representing a trade-off for low-power logic applications. In addition, the change of drain current shows highly piezoresistive sensing ability in nanoelectromechanical sensor applications. Thus, this study demonstrates the importance of mechanical stress engineering for performance improvement in non-planar nanowire devices, piezoresistive sensing applications, and device reliability.
{"title":"Impact of Externally Induced Uniaxial Stress on the Electrical Performance of the Junctionless Nanowire Field-Effect Transistors","authors":"Nitish Kumar;Ankur Gupta;Pushpapraj Singh","doi":"10.1109/TDMR.2025.3581604","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3581604","url":null,"abstract":"The uniaxial tensile mechanical stress (MS) is induced up to 1.4 GPa on the channel of the twin junctionless nanowire (JL-NW) gate-all-around (GAA) field-effect transistors (FETs) using a four-point bending technique. The variation of the electrical parameters is measured before and during induced MS to analyze the performance. The ON-state current, carrier mobility, threshold voltage, and subthreshold swing are directly proportional to the induced MS due to the reduced energy band gap and intervalley scattering effect. The reduced subthreshold swing indicates low power consumption and better switching ability, whereas the higher OFF-state current leads to slightly increased standby power consumption, representing a trade-off for low-power logic applications. In addition, the change of drain current shows highly piezoresistive sensing ability in nanoelectromechanical sensor applications. Thus, this study demonstrates the importance of mechanical stress engineering for performance improvement in non-planar nanowire devices, piezoresistive sensing applications, and device reliability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"677-683"},"PeriodicalIF":2.3,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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