Pub Date : 2024-06-28DOI: 10.1109/tdmr.2024.3420759
G.C. Lyu, X.P. Zhang, M.B. Zhou, C.B. Ke, Y.W. Mai
{"title":"Prediction of Crack Initiation at Die Corner of Molded Underfill Flip-Chip Packages Under Thermal Load by New Criteria—Part I: Accurate Formulation of Singular Stress Fields","authors":"G.C. Lyu, X.P. Zhang, M.B. Zhou, C.B. Ke, Y.W. Mai","doi":"10.1109/tdmr.2024.3420759","DOIUrl":"https://doi.org/10.1109/tdmr.2024.3420759","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"172 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-28DOI: 10.1109/TDMR.2024.3420391
Chonghao Chen;Jiang Xu;Zhuojun Chen
Lateral diffused metal-oxide-semiconductor (LDMOS) devices are vulnerable to single-event burnout (SEB) in radiation environments, potentially leading to catastrophic failure in high-voltage integrated circuits (HVICs). Pulsed-laser experiments have demonstrated that the SEB triggering voltage of n-type LDMOS (nLDMOS) is significantly lower than that of p-type LDMOS (pLDMOS), which limits the applications of complementary LDMOS devices in aerospace electronic systems. This work investigates the SEB mechanism in both nLDMOS and pLDMOS through technology computer-aided design (TCAD) simulations. The analysis reveals that differences in the current gain of parasitic bipolar transistors and well resistance between pLDMOS and nLDMOS result in varying SEB triggering voltages. Additionally, a radiation-hardening technique is employed to improve the SEB triggering voltage of nLDMOS, aligning it closely with that of pLDMOS. This research provides insight into the design of radiation-hardened high-voltage integrated circuits, such as DC-DC converters and motor drivers, using a standard Bipolar-CMOS-DMOS (BCD) fabrication process.
{"title":"Single-Event Burnout Effects of Complementary LDMOS Devices in High-Voltage Integrated Circuits","authors":"Chonghao Chen;Jiang Xu;Zhuojun Chen","doi":"10.1109/TDMR.2024.3420391","DOIUrl":"10.1109/TDMR.2024.3420391","url":null,"abstract":"Lateral diffused metal-oxide-semiconductor (LDMOS) devices are vulnerable to single-event burnout (SEB) in radiation environments, potentially leading to catastrophic failure in high-voltage integrated circuits (HVICs). Pulsed-laser experiments have demonstrated that the SEB triggering voltage of n-type LDMOS (nLDMOS) is significantly lower than that of p-type LDMOS (pLDMOS), which limits the applications of complementary LDMOS devices in aerospace electronic systems. This work investigates the SEB mechanism in both nLDMOS and pLDMOS through technology computer-aided design (TCAD) simulations. The analysis reveals that differences in the current gain of parasitic bipolar transistors and well resistance between pLDMOS and nLDMOS result in varying SEB triggering voltages. Additionally, a radiation-hardening technique is employed to improve the SEB triggering voltage of nLDMOS, aligning it closely with that of pLDMOS. This research provides insight into the design of radiation-hardened high-voltage integrated circuits, such as DC-DC converters and motor drivers, using a standard Bipolar-CMOS-DMOS (BCD) fabrication process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"401-406"},"PeriodicalIF":2.5,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively $1.78times $ / $1.78times $ / $1.83times $ / $1.78times $ / $1.78times $ / $1.99times $ larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.
{"title":"Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique","authors":"Feng Wei;Xiaole Cui;Qixue Zhang;Sunrui Zhang;Xiaoxin Cui;Xing Zhang","doi":"10.1109/TDMR.2024.3417961","DOIUrl":"10.1109/TDMR.2024.3417961","url":null,"abstract":"The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively \u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.83times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.78times $ </tex-math></inline-formula>\u0000/\u0000<inline-formula> <tex-math>$1.99times $ </tex-math></inline-formula>\u0000 larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"390-400"},"PeriodicalIF":2.5,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141506380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3405612
{"title":"Special Issue on Intelligent Sensor Systems for the IEEE Journal of Electron Devices","authors":"","doi":"10.1109/TDMR.2024.3405612","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3405612","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"354-355"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566484","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3405820
{"title":"Blank Page","authors":"","doi":"10.1109/TDMR.2024.3405820","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3405820","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"C4-C4"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566497","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3405819
{"title":"IEEE Transactions on Device and Materials Reliability Information for Authors","authors":"","doi":"10.1109/TDMR.2024.3405819","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3405819","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"C3-C3"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566483","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3407548
Charles LaRow
The IEEE International Integrated Reliability Workshop (IIRW) is a distinctive event which brings together reliability researchers, professionals, and students from around the globe to a common forum for lively discussions, wonderful technical presentations, and beautiful scenery for 4 days and nights. The event takes place every year at Fallen Leaf Lake in South Lake Tahoe, CA, USA, where attendees are housed within a secluded camp with informal meeting spaces and access to boats, trails, and many other outdoor activities. The scope of content centers around hot topics in, novel techniques for, and general knowledge on semiconductor reliability research and industry challenges. Talks on transistor and front-end-of-the-line (FEOL) reliability, bias temperature instability (BTI), hot carrier (HC), gate dielectric time-dependent dielectric breakdown (TDDB), back-end-of-the-line (BEOL) reliability, Interconnect TDDB, electro-migration (EM), circuit reliability, packaging reliability, conventional and emerging memory reliability, failure analysis (FA), wafer-level reliability (WLR), among other topic are presented. The key focus areas at IIRW 2023 were Advanced node scaling solutions (FEOL/MOL/BEOL), circuit reliability (device-circuit degradation and aging).
{"title":"Guest Editorial TDMR IIRW Special Section","authors":"Charles LaRow","doi":"10.1109/TDMR.2024.3407548","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3407548","url":null,"abstract":"The IEEE International Integrated Reliability Workshop (IIRW) is a distinctive event which brings together reliability researchers, professionals, and students from around the globe to a common forum for lively discussions, wonderful technical presentations, and beautiful scenery for 4 days and nights. The event takes place every year at Fallen Leaf Lake in South Lake Tahoe, CA, USA, where attendees are housed within a secluded camp with informal meeting spaces and access to boats, trails, and many other outdoor activities. The scope of content centers around hot topics in, novel techniques for, and general knowledge on semiconductor reliability research and industry challenges. Talks on transistor and front-end-of-the-line (FEOL) reliability, bias temperature instability (BTI), hot carrier (HC), gate dielectric time-dependent dielectric breakdown (TDDB), back-end-of-the-line (BEOL) reliability, Interconnect TDDB, electro-migration (EM), circuit reliability, packaging reliability, conventional and emerging memory reliability, failure analysis (FA), wafer-level reliability (WLR), among other topic are presented. The key focus areas at IIRW 2023 were Advanced node scaling solutions (FEOL/MOL/BEOL), circuit reliability (device-circuit degradation and aging).","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"159-160"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3405818
{"title":"IEEE Transactions on Device and Materials Reliability Publication Information","authors":"","doi":"10.1109/TDMR.2024.3405818","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3405818","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"C2-C2"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566480","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/TDMR.2024.3412348
{"title":"Special Issue on Semiconductor Design for Manufacturing (DFM)Joint Call for Papers","authors":"","doi":"10.1109/TDMR.2024.3412348","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3412348","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"356-356"},"PeriodicalIF":2.5,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10566482","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141435413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-17DOI: 10.1109/TDMR.2024.3415049
Tae Yeob Kang;Haebom Lee;Sungho Suh
In the field of optoelectronics, indium tin oxide (ITO) electrodes play a crucial role in various applications, such as displays, sensors, and solar cells. Effective fault diagnosis and root cause analysis of the ITO electrodes are essential to ensure the performance and reliability of the devices. However, traditional visual inspection is challenging with transparent ITO electrodes, and existing fault diagnosis methods have limitations in determining the root causes of the defects, often requiring destructive evaluations and secondary material characterization techniques. In this study, a fault diagnosis method with root cause analysis is proposed using scattering parameter (S-parameter) patterns, offering early detection, high diagnostic accuracy, and noise robustness. A comprehensive S-parameter pattern database is obtained according to various defect states of the ITO electrodes. Deep learning (DL) approaches, including multilayer perceptron (MLP), convolutional neural network (CNN), and transformer, are then used to simultaneously analyze the cause and severity of defects. Notably, it is demonstrated that the diagnostic performance under additive noise levels can be significantly enhanced by combining different channels of the S-parameters as input to the learning algorithms, as confirmed through the t-distributed stochastic neighbor embedding (t-SNE) dimension reduction visualization of the S-parameter patterns.
在光电子领域，铟锡氧化物（ITO）电极在显示器、传感器和太阳能电池等各种应用中发挥着至关重要的作用。要确保设备的性能和可靠性，就必须对 ITO 电极进行有效的故障诊断和根本原因分析。然而，对于透明的 ITO 电极来说，传统的目视检测具有挑战性，而且现有的故障诊断方法在确定缺陷的根本原因方面存在局限性，通常需要进行破坏性评估和二次材料表征技术。本研究提出了一种利用散射参数（S 参数）模式进行根本原因分析的故障诊断方法，具有早期检测、诊断准确性高和噪声稳健性好的特点。根据 ITO 电极的各种缺陷状态，获得了一个全面的 S 参数模式数据库。然后使用深度学习（DL）方法，包括多层感知器（MLP）、卷积神经网络（CNN）和变压器，同时分析缺陷的原因和严重程度。值得注意的是，通过对 S 参数模式进行 t 分布随机邻域嵌入（t-SNE）降维可视化，证明了将不同通道的 S 参数组合作为学习算法的输入，可显著提高加性噪声水平下的诊断性能。
{"title":"An Empirical Study on Fault Detection and Root Cause Analysis of Indium Tin Oxide Electrodes by Processing S-Parameter Patterns","authors":"Tae Yeob Kang;Haebom Lee;Sungho Suh","doi":"10.1109/TDMR.2024.3415049","DOIUrl":"10.1109/TDMR.2024.3415049","url":null,"abstract":"In the field of optoelectronics, indium tin oxide (ITO) electrodes play a crucial role in various applications, such as displays, sensors, and solar cells. Effective fault diagnosis and root cause analysis of the ITO electrodes are essential to ensure the performance and reliability of the devices. However, traditional visual inspection is challenging with transparent ITO electrodes, and existing fault diagnosis methods have limitations in determining the root causes of the defects, often requiring destructive evaluations and secondary material characterization techniques. In this study, a fault diagnosis method with root cause analysis is proposed using scattering parameter (S-parameter) patterns, offering early detection, high diagnostic accuracy, and noise robustness. A comprehensive S-parameter pattern database is obtained according to various defect states of the ITO electrodes. Deep learning (DL) approaches, including multilayer perceptron (MLP), convolutional neural network (CNN), and transformer, are then used to simultaneously analyze the cause and severity of defects. Notably, it is demonstrated that the diagnostic performance under additive noise levels can be significantly enhanced by combining different channels of the S-parameters as input to the learning algorithms, as confirmed through the t-distributed stochastic neighbor embedding (t-SNE) dimension reduction visualization of the S-parameter patterns.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"380-389"},"PeriodicalIF":2.5,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141935389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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