This study explores optimization strategies for the attenuation performance and modulation depth of Graphene-based Microstrip Line Attenuators (GMSLAs). Existing GMSLAs mainly rely on rectangular attenuation units, such as single-layer graphene sheets and graphene composite sandwich structures, which have limitations in meeting diverse performance requirements. To address this, this study systematically investigates which configuration within the same class of structures yields the most optimal and reliable attenuation performance. Using finite element simulations, this study systematically examines the attenuation performance and modulation characteristics of graphene ring-shaped attenuation units with five distinct geometric configurations (circle, regular triangle, square, regular pentagon, and regular hexagon) in the 40-70 GHz V-band. The results indicate that among individual units, the hexagonal unit exhibits the highest average reflection transmission loss and modulation depth. The triangular unit demonstrates a relatively stable and high average reflection transmission loss as well as the most stable modulation depth, whereas the square unit possesses the most stable average reflection transmission loss. Furthermore, by adjusting the rotation angle of the hexagonal units, significant polarization-dependent attenuation was observed. When combining multiple hexagonal units, their performance exceeded the simple sum of individual unit performances, showing superlinear growth. This study overcomes the limitations of traditional graphene attenuation unit designs by introducing a range of geometric configurations, offering new insights into the development of highly efficient, tunable attenuators with superior performance in high-frequency bands.
{"title":"Exploring the Optimal Solution for Graphene-Based Microstrip Line Attenuators","authors":"Yuhan Li;Cheng Chen;Jingfeng Liu;Jiaxuan Xue;Jixin Wang;Wu Zhao;Zhiyong Zhang;Johan Stiens","doi":"10.1109/TDMR.2025.3578061","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3578061","url":null,"abstract":"This study explores optimization strategies for the attenuation performance and modulation depth of Graphene-based Microstrip Line Attenuators (GMSLAs). Existing GMSLAs mainly rely on rectangular attenuation units, such as single-layer graphene sheets and graphene composite sandwich structures, which have limitations in meeting diverse performance requirements. To address this, this study systematically investigates which configuration within the same class of structures yields the most optimal and reliable attenuation performance. Using finite element simulations, this study systematically examines the attenuation performance and modulation characteristics of graphene ring-shaped attenuation units with five distinct geometric configurations (circle, regular triangle, square, regular pentagon, and regular hexagon) in the 40-70 GHz V-band. The results indicate that among individual units, the hexagonal unit exhibits the highest average reflection transmission loss and modulation depth. The triangular unit demonstrates a relatively stable and high average reflection transmission loss as well as the most stable modulation depth, whereas the square unit possesses the most stable average reflection transmission loss. Furthermore, by adjusting the rotation angle of the hexagonal units, significant polarization-dependent attenuation was observed. When combining multiple hexagonal units, their performance exceeded the simple sum of individual unit performances, showing superlinear growth. This study overcomes the limitations of traditional graphene attenuation unit designs by introducing a range of geometric configurations, offering new insights into the development of highly efficient, tunable attenuators with superior performance in high-frequency bands.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"617-628"},"PeriodicalIF":2.3,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-09DOI: 10.1109/TDMR.2025.3577612
J. Tang;Y. Duan;P. Liu
The rapid advancement of power electronics applications has propelled the development of SiC MOSFETs while simultaneously posing challenges to their long-term reliability. To address this, the reliability issues associated with long-term stress are comprehensively explored through Accelerated Life Tests’ (ALTs’) verification protocols, aiming to optimize devices and enhance experimental methodologies. 16 sets of ALT experiments were conducted under maximum Tj conditions for HTGB, HTRB, and H3TRB tests, divided into groups around rated voltage conditions. The correlation between stress and degradation is examined by comparing offline data at both 25°C and 175°C. In HTRB tests, precursors of failures are confirmed with further investigation into failure modes. For HTGB experiments, the degradation in the gate oxide under gate bias is characterized using the Tj-Vth and C-V methods. Additionally, the device failures due to HV-H3TRB are analyzed by electrical measurement and acoustic scanning. The experimental findings provide insights that inform the design of subsequent ALT experiments.
{"title":"Investigation of Degradation and Failure Mechanism in 1200-V Planar SiC MOSFET Under Statical Accelerated Lifetime Test","authors":"J. Tang;Y. Duan;P. Liu","doi":"10.1109/TDMR.2025.3577612","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3577612","url":null,"abstract":"The rapid advancement of power electronics applications has propelled the development of SiC MOSFETs while simultaneously posing challenges to their long-term reliability. To address this, the reliability issues associated with long-term stress are comprehensively explored through Accelerated Life Tests’ (ALTs’) verification protocols, aiming to optimize devices and enhance experimental methodologies. 16 sets of ALT experiments were conducted under maximum Tj conditions for HTGB, HTRB, and H3TRB tests, divided into groups around rated voltage conditions. The correlation between stress and degradation is examined by comparing offline data at both 25°C and 175°C. In HTRB tests, precursors of failures are confirmed with further investigation into failure modes. For HTGB experiments, the degradation in the gate oxide under gate bias is characterized using the Tj-Vth and C-V methods. Additionally, the device failures due to HV-H3TRB are analyzed by electrical measurement and acoustic scanning. The experimental findings provide insights that inform the design of subsequent ALT experiments.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"441-451"},"PeriodicalIF":2.3,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145043858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-09DOI: 10.1109/TDMR.2025.3575820
{"title":"Wide Band Gap Semiconductors for Automotive Applications","authors":"","doi":"10.1109/TDMR.2025.3575820","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3575820","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"357-358"},"PeriodicalIF":2.5,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11028127","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/TDMR.2025.3575598
Anran Hua;Yanbo Che;Peiyi Li;Mengxiang Zheng
The Insulated Gate Bipolar Transistor (IGBT) is a critical component of power electronic devices, and its reliability significantly impacts the overall system performance. To enhance IGBT reliability assessment in the context of modular multilevel converters (MMCs), this study proposes a remaining useful life (RUL) prediction method based on a phased nonlinear Wiener process. By analyzing the failure mechanisms of IGBTs, the turn-off peak voltage and the collector-emitter saturation voltage are identified as key degradation indicators. A piecewise nonlinear Wiener degradation model is employed for RUL prediction, with gradient change detection method used to dynamically determine segmentation points. The proposed model accounts for the stochastic effects of the drift coefficient and measurement errors, with Kalman filtering algorithm applied to update random parameters in real time. Based on accelerated aging test data, the proposed method is compared with the standard Wiener model, the Wiener model considering only drift coefficient randomness, and other recent RUL prediction methods that do not rely on the Wiener process. The results demonstrate that the proposed approach achieves higher prediction accuracy and computational efficiency, particularly in scenarios with significant fluctuations in degradation indicators, making it highly promising for engineering applications.
{"title":"A Lifetime Prediction Method of IGBT Based on Phased Nonlinear Wiener Process","authors":"Anran Hua;Yanbo Che;Peiyi Li;Mengxiang Zheng","doi":"10.1109/TDMR.2025.3575598","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3575598","url":null,"abstract":"The Insulated Gate Bipolar Transistor (IGBT) is a critical component of power electronic devices, and its reliability significantly impacts the overall system performance. To enhance IGBT reliability assessment in the context of modular multilevel converters (MMCs), this study proposes a remaining useful life (RUL) prediction method based on a phased nonlinear Wiener process. By analyzing the failure mechanisms of IGBTs, the turn-off peak voltage and the collector-emitter saturation voltage are identified as key degradation indicators. A piecewise nonlinear Wiener degradation model is employed for RUL prediction, with gradient change detection method used to dynamically determine segmentation points. The proposed model accounts for the stochastic effects of the drift coefficient and measurement errors, with Kalman filtering algorithm applied to update random parameters in real time. Based on accelerated aging test data, the proposed method is compared with the standard Wiener model, the Wiener model considering only drift coefficient randomness, and other recent RUL prediction methods that do not rely on the Wiener process. The results demonstrate that the proposed approach achieves higher prediction accuracy and computational efficiency, particularly in scenarios with significant fluctuations in degradation indicators, making it highly promising for engineering applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"545-556"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the “First Switch Effect”. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.
{"title":"The First Switch Effect in Ferroelectric Field-Effect Transistors","authors":"Priyankka Ravikumar;Prasanna Venkatesan;Chinsung Park;Nashrah Afroze;Mengkun Tian;Winston Chern;Suman Datta;Shimeng Yu;Souvik Mahapatra;Asif Khan","doi":"10.1109/TDMR.2025.3576042","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3576042","url":null,"abstract":"In this work, a ferroelectric field-effect transistor (FEFET) is systematically characterized and compared with an equivalent standard MOSFET with an equivalent oxide thickness. We show that these two devices, with a silicon channel, exhibit similar pristine state transfer characteristics but starkly different endurance characteristics. In contrast to the MOSFET, the FEFET shows a significant increase in sub-threshold swing in the first write pulse. Based on this, we reveal that this first write pulse (cycle 1) generates more than half of the total traps generated during the fatigue cycling in FEFETs. We call this the “First Switch Effect”. Further, by polarizing a pristine FEFET step by step, we demonstrate a direct correlation between the switched polarization and interface trap density during the first switch. Through charge pumping measurements, we also observe that continued cycling generates traps more towards the bulk of the stack, away from the Si/SiO2 interface in FEFETs. We establish that: (1) the first switch effect leads to approximately 50% of the total trap density (Nit) near the Si/SiO2 interface until memory window closure; and (2) further bipolar cycling leads to trap generation both at and away from Si/SiO2 interface in FEFETs.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 3","pages":"365-370"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-current pulse thyristor-based switches operate under high-current pulse conditions and are subjected to coupled electromagnetic-thermomechanical stresses, resulting in the progressive development of thermal fatigue-induced failure mechanisms. The study revealed that localized overheating triggers electrical erosion of the aluminum layer, which further accelerates the thermal fatigue failure of high-current switches. To investigate this phenomenon, a microscopic model of the silicon-aluminum interface incorporating surface roughness effects was developed to quantify the transient temperature rise and electrical erosion threshold under varying pulsed current conditions, with experimental validation demonstrating strong agreement. Furthermore, using a thermal network model, we established a correlation between the electrical erosion threshold and the average junction temperature for different high-current pulses and clamping stresses, thereby defining the operational range for electrical erosion in high-current pulse thyristor-based switches. This provides theoretical guidance for the reliable operation of these switches.
{"title":"Research on the Mechanism of Electrical Erosion Accelerating Failure in High-Current Pulse Thyristor-Based Switches","authors":"Shiyun Xiao;Yi Liu;Liuxia Li;Fuchang Lin;Yunxin Miao","doi":"10.1109/TDMR.2025.3565618","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3565618","url":null,"abstract":"High-current pulse thyristor-based switches operate under high-current pulse conditions and are subjected to coupled electromagnetic-thermomechanical stresses, resulting in the progressive development of thermal fatigue-induced failure mechanisms. The study revealed that localized overheating triggers electrical erosion of the aluminum layer, which further accelerates the thermal fatigue failure of high-current switches. To investigate this phenomenon, a microscopic model of the silicon-aluminum interface incorporating surface roughness effects was developed to quantify the transient temperature rise and electrical erosion threshold under varying pulsed current conditions, with experimental validation demonstrating strong agreement. Furthermore, using a thermal network model, we established a correlation between the electrical erosion threshold and the average junction temperature for different high-current pulses and clamping stresses, thereby defining the operational range for electrical erosion in high-current pulse thyristor-based switches. This provides theoretical guidance for the reliable operation of these switches.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"263-273"},"PeriodicalIF":2.5,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-24DOI: 10.1109/TDMR.2025.3563885
B Sharmila;Kr. Sarkar Achintya;Priyanka Dwivedi
This paper presents the fabrication, testing device reliability and impact of temperature variation on the MoO3 decorated PSi heterostructure. The memristor devices are fabricated using standard microfabrication processes. The MoO3 decorated PSi heterostructure memristor has shown the current switching ratio, resistance switching ratio of 67 and $7times 10{^{{3}}}$ respectively at room temperature (RT). The reliability test of the MoO3 decorated PSi heterostructure based memristor device is tested using the thermal stimuli ranging from RT to 100°C. The developed device has shown the current switching ratio of 200 at 90°C, which is close to three times higher than the measurements at RT. Further, stability/reproducibility of the fabricated device was verified using the modulated frequency test at 90°C.
{"title":"Memristive Switching Behavior of MoO3 Decorated PSi Heterostructure and Impact of Temperature on Device Reliability","authors":"B Sharmila;Kr. Sarkar Achintya;Priyanka Dwivedi","doi":"10.1109/TDMR.2025.3563885","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3563885","url":null,"abstract":"This paper presents the fabrication, testing device reliability and impact of temperature variation on the MoO3 decorated PSi heterostructure. The memristor devices are fabricated using standard microfabrication processes. The MoO3 decorated PSi heterostructure memristor has shown the current switching ratio, resistance switching ratio of 67 and <inline-formula> <tex-math>$7times 10{^{{3}}}$ </tex-math></inline-formula> respectively at room temperature (RT). The reliability test of the MoO3 decorated PSi heterostructure based memristor device is tested using the thermal stimuli ranging from RT to 100°C. The developed device has shown the current switching ratio of 200 at 90°C, which is close to three times higher than the measurements at RT. Further, stability/reproducibility of the fabricated device was verified using the modulated frequency test at 90°C.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"335-340"},"PeriodicalIF":2.5,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-16DOI: 10.1109/TDMR.2025.3561519
Na Bai;Pengshuai Zhang;Yaohua Xu;Yunhui Guo;Hang Li;Yi Wang;Xiaoqing Wen
Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.
{"title":"A Low Cost Triple-Node-Upset Self-Recoverable Latch Design for Nanoscale CMOS","authors":"Na Bai;Pengshuai Zhang;Yaohua Xu;Yunhui Guo;Hang Li;Yi Wang;Xiaoqing Wen","doi":"10.1109/TDMR.2025.3561519","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3561519","url":null,"abstract":"Due to the constant reduction of semiconductor feature sizes, the charge sharing effect is getting worse. The occurrence probability of triple-node upset (TNU), which has a significant impact on the circuit’s reliability, is rising in nanoscale digital circuits. This paper proposes a low overhead and TNU self-recovery latch (TNU-SR) based on the 28 nm CMOS technology to efficiently tolerate TNU and reduce the power dissipation and latency of the latch. The latch design proposed in this article adopts stacked transistors to reduce sensitive nodes and area overhead. The TNU-SR latch uses clock gating and high-speed transfer path technology, resulting in low power dissipation and low delay. For simulation results, compared with existing latches, it can be known that the TNU-SR latch performs well in terms of delay, power consumption, and area, so it is a good choice for radiation-hardened design for space applications. In addition, compared with the latest TNU self-recovery latch (HLTNURL), the TNU-SR latch proposed in this paper reduces the Power-Area-Delay Product (PADP) metric by 111.13%.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"296-307"},"PeriodicalIF":2.5,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-14DOI: 10.1109/TDMR.2025.3560489
Yong Hyeon Yi;Robert Bloom;Armen Kteyan;Alexander Volkov;Jun-Ho Choy;Stephane Moreau;Valeriy Sukharev;Chris H. Kim
This work presents silicon data from 28 nm test chips specifically designed to study electromigration (EM) induced lifetime effects. The power grids were generated by an automatic place-and-route tool to create realistic device-under-tests (DUT) to capture power grid EM aging behaviors and lifetimes. Poly-silicon quasi-load cells mimicking the circuit current were employed to withstand high temperature stress. 1,024 local voltages throughout the power grid were tapped out to monitor the voiding locations and IR drop trends with stress. Four power grid architectures with different metal configurations were tested under different temperatures and currents. EM effects under different temperatures and current cycling conditions were also studied.
{"title":"A Power Grid Electromigration Test Chip for Lifetime Characterization and Model Calibration","authors":"Yong Hyeon Yi;Robert Bloom;Armen Kteyan;Alexander Volkov;Jun-Ho Choy;Stephane Moreau;Valeriy Sukharev;Chris H. Kim","doi":"10.1109/TDMR.2025.3560489","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3560489","url":null,"abstract":"This work presents silicon data from 28 nm test chips specifically designed to study electromigration (EM) induced lifetime effects. The power grids were generated by an automatic place-and-route tool to create realistic device-under-tests (DUT) to capture power grid EM aging behaviors and lifetimes. Poly-silicon quasi-load cells mimicking the circuit current were employed to withstand high temperature stress. 1,024 local voltages throughout the power grid were tapped out to monitor the voiding locations and IR drop trends with stress. Four power grid architectures with different metal configurations were tested under different temperatures and currents. EM effects under different temperatures and current cycling conditions were also studied.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"253-262"},"PeriodicalIF":2.5,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TDMR.2025.3559531
Anand Pandey;Ankush Bag
The operational thermal stability of perovskite solar cells (PSCs) is a critical issue hindering their commercialization. Therefore, besides achieving high power conversion efficiency (PCE), understanding and quantifying the device degradation kinetics of PSCs is necessary for their reliability and to prevent failure under thermal stress. In this work, exponential and linear degradation models have been adopted to comprehend and quantify the degradation kinetics of FAPbI3 and multifunctional fluorinated molecule 3-fluoro-4-methoxy-4’,4”-bis((4-vinyl benzyl ether) methyl)) triphenylamine (FTPA)-modified FAPbI3 PSCs. Further, various figures of merit, such as acceleration factor, degradation factor, mean lifetime, transformational fraction, and activation energy, have been deduced by fitting the PCE degradation data into the Arrhenius equation and onto the Johnson– Mehl-Avrami (JMA) kinetic models. These figures of merit have been correlated with other defect-determining factors such as micro-strain and Urbach’s energy. The degradation factor and PbI2 residuals are reduced for controlled PSCs to FTPA-modified PSCs. Furthermore, the activation energy and operational thermal stability of FTPA-modified PSCs have increased due to the forming of a hydrogen-bonding polymer network, which enhances PSCs’ thermal stability and acceleration factor. Our findings reveal that the studied devices’ intrinsic stability, thermal stability, and mean lifetime strongly correlate with micro-structural and optoelectronic defects, which helps to improve the performance of photovoltaics.
{"title":"Modeling Degradation Kinetics of FAPbI₃ Perovskite Solar Cells: Impact of Microstructural and Optoelectronic Defects","authors":"Anand Pandey;Ankush Bag","doi":"10.1109/TDMR.2025.3559531","DOIUrl":"https://doi.org/10.1109/TDMR.2025.3559531","url":null,"abstract":"The operational thermal stability of perovskite solar cells (PSCs) is a critical issue hindering their commercialization. Therefore, besides achieving high power conversion efficiency (PCE), understanding and quantifying the device degradation kinetics of PSCs is necessary for their reliability and to prevent failure under thermal stress. In this work, exponential and linear degradation models have been adopted to comprehend and quantify the degradation kinetics of FAPbI3 and multifunctional fluorinated molecule 3-fluoro-4-methoxy-4’,4”-bis((4-vinyl benzyl ether) methyl)) triphenylamine (FTPA)-modified FAPbI3 PSCs. Further, various figures of merit, such as acceleration factor, degradation factor, mean lifetime, transformational fraction, and activation energy, have been deduced by fitting the PCE degradation data into the Arrhenius equation and onto the Johnson– Mehl-Avrami (JMA) kinetic models. These figures of merit have been correlated with other defect-determining factors such as micro-strain and Urbach’s energy. The degradation factor and PbI2 residuals are reduced for controlled PSCs to FTPA-modified PSCs. Furthermore, the activation energy and operational thermal stability of FTPA-modified PSCs have increased due to the forming of a hydrogen-bonding polymer network, which enhances PSCs’ thermal stability and acceleration factor. Our findings reveal that the studied devices’ intrinsic stability, thermal stability, and mean lifetime strongly correlate with micro-structural and optoelectronic defects, which helps to improve the performance of photovoltaics.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"25 2","pages":"288-295"},"PeriodicalIF":2.5,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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