Pub Date : 2024-04-10DOI: 10.1109/TDMR.2024.3387305
Daniel Beckmeier;Charles LaRow;Andreas Kerber
Plasma Induced Damage (PID) testing methodology is applied to a Vertical Floating-Gate 3D NAND Memory Technology with CMOS under Array (CuA) and detected lifetime effects are reported for the first time. Revealing Constant Current Stresses (CCS) at elevated temperature of 95°C are performed to identify process charging risks. The effect on transistor dielectric breakdown lifetimes from PID induced defects are quantified by a Constant Voltage Stress (CVS) test methodology and modeled by combining intrinsic and extrinsic failure distributions scaled by antenna size. To determine the voltage dependence of the early fails, a larger sample size is stressed at varying gate stress voltages. The tests show the same intrinsic power law voltage acceleration while for larger antennas the extrinsic branches increase with reduced gate stress voltage. The empirical bimodal TDDB model with added intrinsic/extrinsic power law terms for the gate stress voltage can describe the behavior with high accuracy. A physical model using the gate current voltage characteristics and the antenna area ratios as inputs is developed, which describes the behavior also with good agreement. Probing pad charging damage effects are further analyzed by TDDB tests on capacitor structures of varying gate dielectric areas for n- and pMOS devices of different dielectric thicknesses.
{"title":"TDDB Lifetime Reduction From Charging Damage in a 3D Vertical NAND Memory Technology","authors":"Daniel Beckmeier;Charles LaRow;Andreas Kerber","doi":"10.1109/TDMR.2024.3387305","DOIUrl":"10.1109/TDMR.2024.3387305","url":null,"abstract":"Plasma Induced Damage (PID) testing methodology is applied to a Vertical Floating-Gate 3D NAND Memory Technology with CMOS under Array (CuA) and detected lifetime effects are reported for the first time. Revealing Constant Current Stresses (CCS) at elevated temperature of 95°C are performed to identify process charging risks. The effect on transistor dielectric breakdown lifetimes from PID induced defects are quantified by a Constant Voltage Stress (CVS) test methodology and modeled by combining intrinsic and extrinsic failure distributions scaled by antenna size. To determine the voltage dependence of the early fails, a larger sample size is stressed at varying gate stress voltages. The tests show the same intrinsic power law voltage acceleration while for larger antennas the extrinsic branches increase with reduced gate stress voltage. The empirical bimodal TDDB model with added intrinsic/extrinsic power law terms for the gate stress voltage can describe the behavior with high accuracy. A physical model using the gate current voltage characteristics and the antenna area ratios as inputs is developed, which describes the behavior also with good agreement. Probing pad charging damage effects are further analyzed by TDDB tests on capacitor structures of varying gate dielectric areas for n- and pMOS devices of different dielectric thicknesses.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"203-210"},"PeriodicalIF":2.5,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.
{"title":"A Low-Area Overhead and Low-Delay Triple-Node-Upset Self-Recoverable Design Based on Stacked Transistors","authors":"Hui Xu;Jiuqi Li;Ruijun Ma;Huaguo Liang;Chaoming Liu;Senling Wang;Xiaoqing Wen","doi":"10.1109/TDMR.2024.3386954","DOIUrl":"10.1109/TDMR.2024.3386954","url":null,"abstract":"With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"302-312"},"PeriodicalIF":2.5,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study investigates the characteristics on different channel lengths for a sequence of Si3N4 and SiO2 deposition as PV of LTPS TFTs. After analyzing the subthreshold swing (SS) of the initial condition and change in the $Delta text{V}_{text{TH}}$ after NBTI and PBTI operations, a degradation mechanism is identified. When Si3N4 is deposited as the first layer of passivation (PV), hydrogen diffuses into the channel owing to activation or thermal annealing. As the channel length decreases, the hydrogen concentration increases at the center of the channel for devices with Si3N4 as the first layer of PV. Elevated hydrogen concentrations in the center of short channel devices lead to a debased SS. Moreover, the more positive fixed oxide charges create a more pronounced degradation after NBTI operation. On the other hand, PBTI performance shows a milder degradation with decreasing channel length due to fewer trapping charges. Finally, the hydrogen concentration is verified using SIMS. In summary, the heightened degradation of NBTI with device scaling is attributed to excess hydrogen on channel center during Si3N4 film deposition. The uneven hydrogen distribution also contributes the different SS and the different degradation after PBTI operation with different channel length.
{"title":"The Characteristics and Reliability With Channel Length Dependent on the Deposited Sequence of SiO₂ and Si₃N₄ as PV in LTPS TFTs","authors":"Chuan-Wei Kuo;Tsung-Ming Tsai;Ting-Chang Chang;Hong-Yi Tu;Yu-Hsiang Tsai;Jian-Jie Chen;I-Yu Huang","doi":"10.1109/TDMR.2024.3379743","DOIUrl":"10.1109/TDMR.2024.3379743","url":null,"abstract":"This study investigates the characteristics on different channel lengths for a sequence of Si3N4 and SiO2 deposition as PV of LTPS TFTs. After analyzing the subthreshold swing (SS) of the initial condition and change in the \u0000<inline-formula> <tex-math>$Delta text{V}_{text{TH}}$ </tex-math></inline-formula>\u0000 after NBTI and PBTI operations, a degradation mechanism is identified. When Si3N4 is deposited as the first layer of passivation (PV), hydrogen diffuses into the channel owing to activation or thermal annealing. As the channel length decreases, the hydrogen concentration increases at the center of the channel for devices with Si3N4 as the first layer of PV. Elevated hydrogen concentrations in the center of short channel devices lead to a debased SS. Moreover, the more positive fixed oxide charges create a more pronounced degradation after NBTI operation. On the other hand, PBTI performance shows a milder degradation with decreasing channel length due to fewer trapping charges. Finally, the hydrogen concentration is verified using SIMS. In summary, the heightened degradation of NBTI with device scaling is attributed to excess hydrogen on channel center during Si3N4 film deposition. The uneven hydrogen distribution also contributes the different SS and the different degradation after PBTI operation with different channel length.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"268-274"},"PeriodicalIF":2.5,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-01DOI: 10.1109/TDMR.2024.3384056
Sara Vecchi;Andrea Padovani;Paolo Pavan;Francesco Maria Puglisi
Despite the various well-established theories such as the thermochemical (E-model), $surd $ E-model, power law $(V^{N}$ -model), and 1/E-model, accurately replicate dielectric breakdown (BD) experimental trends in accelerated conditions, they diverge significantly in lifetime estimations when projecting to operating conditions. The recently introduced Carrier Injection (CI) model successfully reconciles the discrepancies observed in the aforementioned theories within a unified framework, revealing that the time-dependent dielectric breakdown (TDDB) E-field dependence can change from thermochemical to power-law, and even to 1/E trend, depending on the microscopic properties of key atomic species (precursors). Notably, these findings were based on the assumption that the electric field in the dielectric is solely influenced by the applied bias, disregarding the impact of trapped charge at defects and precursors. Nevertheless, it is recognized that trapped charge significantly contributes to the local electric field within the oxide at low applied voltages, leading to a substantial difference between accelerated and operating conditions. With that in mind, this paper incorporates the influence of trapped charges into the CI model, offering a more complete explanation of the BD phenomenon in SiO2 and HfO2 stacks. The research demonstrates that, depending on the material system and the nature of defect precursors in the oxide, the presence of trapped charge can result in significant deviations from TDDB lifetime predictions derived from conventional models. Furthermore, the study explores the combined impact of trapped charge and the microscopic properties of defect precursor sites on TDDB and leakage current through the oxide.
{"title":"From Accelerated to Operating Conditions: How Trapped Charge Impacts on TDDB in SiO₂ and HfO₂ Stacks","authors":"Sara Vecchi;Andrea Padovani;Paolo Pavan;Francesco Maria Puglisi","doi":"10.1109/TDMR.2024.3384056","DOIUrl":"10.1109/TDMR.2024.3384056","url":null,"abstract":"Despite the various well-established theories such as the thermochemical (E-model), \u0000<inline-formula> <tex-math>$surd $ </tex-math></inline-formula>\u0000 E-model, power law \u0000<inline-formula> <tex-math>$(V^{N}$ </tex-math></inline-formula>\u0000-model), and 1/E-model, accurately replicate dielectric breakdown (BD) experimental trends in accelerated conditions, they diverge significantly in lifetime estimations when projecting to operating conditions. The recently introduced Carrier Injection (CI) model successfully reconciles the discrepancies observed in the aforementioned theories within a unified framework, revealing that the time-dependent dielectric breakdown (TDDB) E-field dependence can change from thermochemical to power-law, and even to 1/E trend, depending on the microscopic properties of key atomic species (precursors). Notably, these findings were based on the assumption that the electric field in the dielectric is solely influenced by the applied bias, disregarding the impact of trapped charge at defects and precursors. Nevertheless, it is recognized that trapped charge significantly contributes to the local electric field within the oxide at low applied voltages, leading to a substantial difference between accelerated and operating conditions. With that in mind, this paper incorporates the influence of trapped charges into the CI model, offering a more complete explanation of the BD phenomenon in SiO2 and HfO2 stacks. The research demonstrates that, depending on the material system and the nature of defect precursors in the oxide, the presence of trapped charge can result in significant deviations from TDDB lifetime predictions derived from conventional models. Furthermore, the study explores the combined impact of trapped charge and the microscopic properties of defect precursor sites on TDDB and leakage current through the oxide.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"194-202"},"PeriodicalIF":2.5,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-01DOI: 10.1109/TDMR.2024.3384065
Roshaun C. Titus;Miriam R. Rath;Rosario A. Gerhardt;J. Elliott Fowler
The use of electronics substrates, such as printed circuit boards (PCBs) in modern technology has become nearly ubiquitous. As PCBs become smaller, denser and mass produced, printed, interdigitated circuit (IDC) sensors are increasingly utilized to qualify the geometric, material and process decisions for manufacturing electronics assemblies. Despite this, the accuracy in determining reproducibility and reliability of printed circuit designs for these applications is not well studied. In this article we report on the usage of small signal ac impedance spectroscopy to determine measurement repeatability and manufactured board reproducibility as a function of frequency, humidity and solder mask coverage for a single IDC design. These measurements allowed detection of systematic changes in the electrical response as the frequency (10MHz-0.1Hz) and humidity were varied (96%-10%RH). Our ac impedance results indicate that the measurement repeatability error is better than 0.6% while circuit or board reproducibility ranges from 2.5%-5.2%. Detailed surface analysis of the circuit structures indicated that differences observed were primarily due to porosity in the solder mask as well as differences in solder coating thickness and coverage between the interdigitated combs. Results are explained by a model that considers water surface adsorption, then infusion into the pore space and finally diffusion through the solder mask as the humidity of the ambient increased. These effects were most easily detected using imaginary electric modulus M” vs log frequency plots. It is anticipated that this methodology will have application to other circuit designs, solder mask or contamination variability.
印刷电路板（PCB）等电子基板在现代技术中的应用几乎无处不在。随着印刷电路板变得更小、更密集和大规模生产，越来越多的印刷电路板插接（IDC）传感器被用来验证制造电子组件的几何、材料和工艺决策。尽管如此，在确定这些应用中印刷电路设计的可重复性和可靠性方面的准确性还没有得到很好的研究。在本文中，我们报告了使用小信号交流阻抗光谱来确定测量可重复性和单个 IDC 设计的制造电路板可重复性与频率、湿度和焊接掩模覆盖率的函数关系。通过这些测量，可以检测到频率（10MHz-0.1Hz）和湿度（96%-10%RH）变化时电气响应的系统性变化。我们的交流阻抗测量结果表明，测量的重复性误差优于 0.6%，而电路或电路板的再现性则在 2.5%-5.2% 之间。对电路结构进行的详细表面分析表明，观察到的差异主要是由于阻焊层的多孔性以及阻焊梳之间的焊料涂层厚度和覆盖率的差异造成的。结果可以用一个模型来解释，该模型考虑了水的表面吸附，然后渗入孔隙，最后随着环境湿度的增加通过阻焊层扩散。使用虚电模量 M "与对数频率图最容易检测到这些影响。预计这种方法可应用于其他电路设计、阻焊层或污染变化。
{"title":"Effects of Solder Mask Variability on the Electrical Response of Commercially Manufactured Interdigitated Circuits","authors":"Roshaun C. Titus;Miriam R. Rath;Rosario A. Gerhardt;J. Elliott Fowler","doi":"10.1109/TDMR.2024.3384065","DOIUrl":"10.1109/TDMR.2024.3384065","url":null,"abstract":"The use of electronics substrates, such as printed circuit boards (PCBs) in modern technology has become nearly ubiquitous. As PCBs become smaller, denser and mass produced, printed, interdigitated circuit (IDC) sensors are increasingly utilized to qualify the geometric, material and process decisions for manufacturing electronics assemblies. Despite this, the accuracy in determining reproducibility and reliability of printed circuit designs for these applications is not well studied. In this article we report on the usage of small signal ac impedance spectroscopy to determine measurement repeatability and manufactured board reproducibility as a function of frequency, humidity and solder mask coverage for a single IDC design. These measurements allowed detection of systematic changes in the electrical response as the frequency (10MHz-0.1Hz) and humidity were varied (96%-10%RH). Our ac impedance results indicate that the measurement repeatability error is better than 0.6% while circuit or board reproducibility ranges from 2.5%-5.2%. Detailed surface analysis of the circuit structures indicated that differences observed were primarily due to porosity in the solder mask as well as differences in solder coating thickness and coverage between the interdigitated combs. Results are explained by a model that considers water surface adsorption, then infusion into the pore space and finally diffusion through the solder mask as the humidity of the ambient increased. These effects were most easily detected using imaginary electric modulus M” vs log frequency plots. It is anticipated that this methodology will have application to other circuit designs, solder mask or contamination variability.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"287-301"},"PeriodicalIF":2.5,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140588066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-31DOI: 10.1109/TDMR.2024.3407855
Kaining Kuang;Xinhua Guo;Chunzhen Li;Xiuwan Li
Film capacitors are widely used in electric vehicles (EVs) controllers to reduce the adverse effects of ripple current on batteries and converters. But the upper limit of the working temperature for film capacitors is relatively low. High ambient temperatures in EVs can lead to premature failure of film capacitors, thereby impacting the reliability of the controllers. Therefore, proposing a corresponding capacitor lifetime prediction method is a burning issue. This paper analyzes the accumulation of damage and degradation processes in film capacitors and proposes a method to predict their lifetime, which accounts for changes in ESR, thermal conductivity, and internal losses. An analysis on a $440mu $ F film capacitor bank is performed using this method as an example. In addition, the effectiveness of optimizing the capacitor structure to extend capacitor lifetime is analyzed based on finite element modeling (FEM), and the Monte Carlo method is employed to consider the influence of manufacturing tolerances on the reliability of film capacitors. The analysis results indicate that, compared to the original capacitor, the B10 life of the optimized capacitor can be extended by 54.11%.
薄膜电容器被广泛应用于电动汽车（EV）控制器中，以减少纹波电流对电池和转换器的不利影响。但薄膜电容器的工作温度上限相对较低。电动汽车中的环境温度过高会导致薄膜电容器过早失效，从而影响控制器的可靠性。因此，提出相应的电容器寿命预测方法是一个紧迫的问题。本文分析了薄膜电容器的累积损伤和退化过程，并提出了一种预测其使用寿命的方法，该方法考虑了 ESR、热传导率和内部损耗的变化。本文以一个价值 440 美元的 F 薄膜电容器组为例进行了分析。此外，还基于有限元建模（FEM）分析了优化电容器结构以延长电容器寿命的有效性，并采用蒙特卡罗方法考虑了制造公差对薄膜电容器可靠性的影响。分析结果表明，与原始电容器相比，优化电容器的 B10 寿命可延长 54.11%。
{"title":"A Novel Lifetime Estimation Method and Structural Optimization Design for Film Capacitors in EVs Considering Material Aging and Power Losses","authors":"Kaining Kuang;Xinhua Guo;Chunzhen Li;Xiuwan Li","doi":"10.1109/TDMR.2024.3407855","DOIUrl":"10.1109/TDMR.2024.3407855","url":null,"abstract":"Film capacitors are widely used in electric vehicles (EVs) controllers to reduce the adverse effects of ripple current on batteries and converters. But the upper limit of the working temperature for film capacitors is relatively low. High ambient temperatures in EVs can lead to premature failure of film capacitors, thereby impacting the reliability of the controllers. Therefore, proposing a corresponding capacitor lifetime prediction method is a burning issue. This paper analyzes the accumulation of damage and degradation processes in film capacitors and proposes a method to predict their lifetime, which accounts for changes in ESR, thermal conductivity, and internal losses. An analysis on a \u0000<inline-formula> <tex-math>$440mu $ </tex-math></inline-formula>\u0000F film capacitor bank is performed using this method as an example. In addition, the effectiveness of optimizing the capacitor structure to extend capacitor lifetime is analyzed based on finite element modeling (FEM), and the Monte Carlo method is employed to consider the influence of manufacturing tolerances on the reliability of film capacitors. The analysis results indicate that, compared to the original capacitor, the B10 life of the optimized capacitor can be extended by 54.11%.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 3","pages":"365-379"},"PeriodicalIF":2.5,"publicationDate":"2024-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141192456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1109/TDMR.2024.3382396
Paul Stampfer;Frederic Roger;Lukas Cvitkovich;Tibor Grasser;Michael Waltl
We present a Deep Level Transient Spectroscopy (DLTS) study on dedicated test samples to investigate the defect landscape of deep trench (DT) sidewalls. The DT is commonly used to prevent crosstalk between two neighboring optoelectronic devices or as a separator between different functional blocks on a monolithic semiconductor chip. However, in minority carrier-based optoelectronic devices, such as photodiodes, carriers might recombine at trap states located at the DT to silicon interface causing performance degradation. The extracted parameters of the DLTS study are further utilized to investigate this recombination in terms of TCAD simulations. The results suggest that carrier recombination at the DT sidewalls of DT-terminated photodiodes may lead to non-linear responsivities with respect to the optical radiant flux. Furthermore, on the example of silicon dangling bonds, we investigate the influence of structural relaxations at the defect sites which are incorporated in the nonradiative multiphonon (NMP) model. By a comparison between the NMP model to the conventional Shockley-Read-Hall (SRH) model we show, that a difference in the emission barrier of approx. 50 meV will arise, resulting in a strong shift of the corresponding DLTS transients.
{"title":"A DLTS Study on Deep Trench Processing-Induced Trap States in Silicon Photodiodes","authors":"Paul Stampfer;Frederic Roger;Lukas Cvitkovich;Tibor Grasser;Michael Waltl","doi":"10.1109/TDMR.2024.3382396","DOIUrl":"10.1109/TDMR.2024.3382396","url":null,"abstract":"We present a Deep Level Transient Spectroscopy (DLTS) study on dedicated test samples to investigate the defect landscape of deep trench (DT) sidewalls. The DT is commonly used to prevent crosstalk between two neighboring optoelectronic devices or as a separator between different functional blocks on a monolithic semiconductor chip. However, in minority carrier-based optoelectronic devices, such as photodiodes, carriers might recombine at trap states located at the DT to silicon interface causing performance degradation. The extracted parameters of the DLTS study are further utilized to investigate this recombination in terms of TCAD simulations. The results suggest that carrier recombination at the DT sidewalls of DT-terminated photodiodes may lead to non-linear responsivities with respect to the optical radiant flux. Furthermore, on the example of silicon dangling bonds, we investigate the influence of structural relaxations at the defect sites which are incorporated in the nonradiative multiphonon (NMP) model. By a comparison between the NMP model to the conventional Shockley-Read-Hall (SRH) model we show, that a difference in the emission barrier of approx. 50 meV will arise, resulting in a strong shift of the corresponding DLTS transients.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"161-167"},"PeriodicalIF":2.5,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10480619","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140316144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/TDMR.2024.3379745
Osman Çiçek;Yosef Badali
Gallium Nitride (GaN) based High Electron Mobility Transistors (HEMTs) are regarded as fundamental semiconductor devices for future power electronic applications. Consequently, researchers have directed their efforts toward enhancing critical parameters such as the breakdown voltage $(V_{br})$ , cut-off frequency, and operating temperature. Therefore, this review article explores research endeavors concerning the enhancement of $V_{br}$ in GaN-based HEMTs. The objective is to gain insights into the key factors influencing $V_{br}$ values and to identify the constraints that govern the optimal performance of HEMTs in power devices. Additionally, this review provides an in-depth examination of select studies that introduce novel techniques for improving $V_{br}$ values.
{"title":"A Review: Breakdown Voltage Enhancement of GaN Semiconductors-Based High Electron Mobility Transistors","authors":"Osman Çiçek;Yosef Badali","doi":"10.1109/TDMR.2024.3379745","DOIUrl":"10.1109/TDMR.2024.3379745","url":null,"abstract":"Gallium Nitride (GaN) based High Electron Mobility Transistors (HEMTs) are regarded as fundamental semiconductor devices for future power electronic applications. Consequently, researchers have directed their efforts toward enhancing critical parameters such as the breakdown voltage \u0000<inline-formula> <tex-math>$(V_{br})$ </tex-math></inline-formula>\u0000, cut-off frequency, and operating temperature. Therefore, this review article explores research endeavors concerning the enhancement of \u0000<inline-formula> <tex-math>$V_{br}$ </tex-math></inline-formula>\u0000 in GaN-based HEMTs. The objective is to gain insights into the key factors influencing \u0000<inline-formula> <tex-math>$V_{br}$ </tex-math></inline-formula>\u0000 values and to identify the constraints that govern the optimal performance of HEMTs in power devices. Additionally, this review provides an in-depth examination of select studies that introduce novel techniques for improving \u0000<inline-formula> <tex-math>$V_{br}$ </tex-math></inline-formula>\u0000 values.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"275-286"},"PeriodicalIF":2.5,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/TDMR.2024.3379498
Jie Chen;Shuang Zhou;Zhen-Guo Yang
The SiC die has broad application prospects in new energy vehicles due to its excellent performances. In recent years, with the continuous development, the safety and reliability of SiC power modules have become particularly important and highly valued. In this paper, a case about the abnormal failure of SiC power modules during the High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) tests was addressed. According to the failure phenomena, a systematical investigation was conducted to explore the root cause by a series of methods such as failure point localization, synchrotron radiation infrared spectrum (SR-IR), time of flight-secondary ion mass spectrometry (TOF-SIMS), the ion beam method, scanning electron microscope (SEM) equipped with the energy dispersive spectrometer (EDS). Finally, the root cause of the failure was determined through comprehensive analysis, and based on the conclusions, some corresponding countermeasures were also proposed. Hopefully, the achievements obtained in this paper would be of great significance for improving the reliability of SiC power modules and avoiding similar failure in future manufacturing process.
SiC 芯片因其优异的性能，在新能源汽车领域有着广阔的应用前景。近年来，随着SiC电源模块的不断发展，其安全性和可靠性变得尤为重要和备受重视。本文针对 SiC 功率模块在高电压-高湿度-高温反向偏置（HV-H3TRB）试验中出现的异常失效案例进行了分析。根据故障现象，通过故障点定位、同步辐射红外光谱（SR-IR）、飞行时间-二次离子质谱（TOF-SIMS）、离子束法、配备能量色散光谱仪（EDS）的扫描电子显微镜（SEM）等一系列方法进行了系统调查，以探究故障的根本原因。最后，通过综合分析确定了失效的根本原因，并在此基础上提出了一些相应的对策。希望本文所取得的成果对提高碳化硅功率模块的可靠性，避免在今后的制造过程中出现类似故障具有重要意义。
{"title":"Cause Analysis on the Abnormal Failure of SiC Power Modules During the HV-H3TRB Tests","authors":"Jie Chen;Shuang Zhou;Zhen-Guo Yang","doi":"10.1109/TDMR.2024.3379498","DOIUrl":"10.1109/TDMR.2024.3379498","url":null,"abstract":"The SiC die has broad application prospects in new energy vehicles due to its excellent performances. In recent years, with the continuous development, the safety and reliability of SiC power modules have become particularly important and highly valued. In this paper, a case about the abnormal failure of SiC power modules during the High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) tests was addressed. According to the failure phenomena, a systematical investigation was conducted to explore the root cause by a series of methods such as failure point localization, synchrotron radiation infrared spectrum (SR-IR), time of flight-secondary ion mass spectrometry (TOF-SIMS), the ion beam method, scanning electron microscope (SEM) equipped with the energy dispersive spectrometer (EDS). Finally, the root cause of the failure was determined through comprehensive analysis, and based on the conclusions, some corresponding countermeasures were also proposed. Hopefully, the achievements obtained in this paper would be of great significance for improving the reliability of SiC power modules and avoiding similar failure in future manufacturing process.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 2","pages":"260-267"},"PeriodicalIF":2.5,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140202930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-08DOI: 10.1109/TDMR.2024.3369791
{"title":"Call for Nominations Editor-in-Chief IEEE Transactions on Device and Materials Reliability","authors":"","doi":"10.1109/TDMR.2024.3369791","DOIUrl":"https://doi.org/10.1109/TDMR.2024.3369791","url":null,"abstract":"","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"154-154"},"PeriodicalIF":2.0,"publicationDate":"2024-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10463657","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140067242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：