Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940628
Saptarshi Das, J. Appenzeller
In this paper, we propose and quantitatively evaluate an “All-Graphene nano-ribbon (GNR) circuit” for high frequency low noise amplifier (LNA) applications, which shows considerable advantage over state-of-the-art technologies. In particular, we discuss how to satisfy the requirements for temperature stability, gain, power dissipation, noise and speed for a high performance LNA circuit by adjusting only the width of the nano ribbons. Our calculations predict a nano-ribbon width in the range of 8–12 nm to be ideal for these types of applications - different from logic applications that are expected to require much smaller ribbon widths.
{"title":"An all-graphene radio frequency low noise amplifier","authors":"Saptarshi Das, J. Appenzeller","doi":"10.1109/RFIC.2011.5940628","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940628","url":null,"abstract":"In this paper, we propose and quantitatively evaluate an “All-Graphene nano-ribbon (GNR) circuit” for high frequency low noise amplifier (LNA) applications, which shows considerable advantage over state-of-the-art technologies. In particular, we discuss how to satisfy the requirements for temperature stability, gain, power dissipation, noise and speed for a high performance LNA circuit by adjusting only the width of the nano ribbons. Our calculations predict a nano-ribbon width in the range of 8–12 nm to be ideal for these types of applications - different from logic applications that are expected to require much smaller ribbon widths.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940642
Wouter Volkaerts, M. Steyaert, P. Reynaert
This paper presents a 118GHz fundamental voltage controlled oscillator in a 65nm low power CMOS technology. Using accumulation mode varactors, the oscillator covers a frequency range from 113.4GHz to 122.6GHz, which corresponds to a 7.8% tuning range. This is the widest tuning range in a D-band VCO reported to date. Combined with a variable supply voltage, the tuning range is extended to 11GHz (9.3%). The VCO draws 5.6mA from a 1V supply and the output is higher than −28.5 dBm. The measured phase noise at 118.3GHz is −83.9dBc/Hz at 1MHz offset. The FOMT is −175.7dB, which is the highest reported for a D-band VCO.
{"title":"118GHz fundamental VCO with 7.8% tuning range in 65nm CMOS","authors":"Wouter Volkaerts, M. Steyaert, P. Reynaert","doi":"10.1109/RFIC.2011.5940642","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940642","url":null,"abstract":"This paper presents a 118GHz fundamental voltage controlled oscillator in a 65nm low power CMOS technology. Using accumulation mode varactors, the oscillator covers a frequency range from 113.4GHz to 122.6GHz, which corresponds to a 7.8% tuning range. This is the widest tuning range in a D-band VCO reported to date. Combined with a variable supply voltage, the tuning range is extended to 11GHz (9.3%). The VCO draws 5.6mA from a 1V supply and the output is higher than −28.5 dBm. The measured phase noise at 118.3GHz is −83.9dBc/Hz at 1MHz offset. The FOMT is −175.7dB, which is the highest reported for a D-band VCO.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123753486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940643
O. Yildirim, Dongwan Ha, D. Ham
We report a mode-locked electrical oscillator fully integrated in GaAs. It self generates a periodic train of pulses with a 16-ps pulse width and a 18.7-GHz frequency. This is the fastest electrical mode-locked oscillator to date, and the first integration of reflective mode-locked electrical oscillator. It works by sending a pulse back and forth on a coplanar waveguide with reflections at both ends. The reflection occurs with level-dependent gain that enables pulse formation and stabilization.
{"title":"Fully monolithic 18.7GHz 16Ps GaAs mode-locked oscillators","authors":"O. Yildirim, Dongwan Ha, D. Ham","doi":"10.1109/RFIC.2011.5940643","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940643","url":null,"abstract":"We report a mode-locked electrical oscillator fully integrated in GaAs. It self generates a periodic train of pulses with a 16-ps pulse width and a 18.7-GHz frequency. This is the fastest electrical mode-locked oscillator to date, and the first integration of reflective mode-locked electrical oscillator. It works by sending a pulse back and forth on a coplanar waveguide with reflections at both ends. The reflection occurs with level-dependent gain that enables pulse formation and stabilization.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129696811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940615
C. Schultz, H. Doppke, M. Hammes, R. Kreienkamp, L. Lemke, S. van Waasen
A GPS receiver front-end achieves high dynamic input range by using Q-enhancement circuitry. In mobile phone environments the Q of the LNA is automatically increased, improving blocker performance by 11.3dB. The area is 1.9mm2 fabricated in a 65nm CMOS process without RF options and requires 25mA from a 1.3V supply with a system NF of 1.5dB.
{"title":"An L-band receiver-front-end-architecture using adaptive Q-enhancement techniques in 65nm CMOS as enabler for single-SAW GPS receivers","authors":"C. Schultz, H. Doppke, M. Hammes, R. Kreienkamp, L. Lemke, S. van Waasen","doi":"10.1109/RFIC.2011.5940615","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940615","url":null,"abstract":"A GPS receiver front-end achieves high dynamic input range by using Q-enhancement circuitry. In mobile phone environments the Q of the LNA is automatically increased, improving blocker performance by 11.3dB. The area is 1.9mm2 fabricated in a 65nm CMOS process without RF options and requires 25mA from a 1.3V supply with a system NF of 1.5dB.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122692463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940718
Wei-Tsung Li, Jeng‐Han Tsai, Min Huang, Tian-Wei Huang
An ultra-compact reflection-type phase shifter (RTPS) with full 360° continuous phase shift and low insertion loss using standard 0.18-µm CMOS technology is demonstrated in this paper. Dual active reflection load using active inductor is utilized in the proposed reflection-type load to cover 360 ° phase tuning through only one quadrature hybrid, which has the advantages of compact chip size, low insertion loss, and low loss variation. Measurements show better than 15 dB input/output return loss, signal losses of 6.4dB±1.5dB, less than 2.4dB±0.6 dB loss variation, and a 360 ° continuously tunable range across 3.5∼4.5 GHz with 3.4mW dc power consumption. To the best of our knowledge, the proposed phase shifter has the smallest die size, 0.25 mm2, among all reported 360° C-band CMOS RTPS, which is important for a large phase array system.
{"title":"A 3.5–4.5-GHz ultra-compact 0.25mm2 reflection-type 360° phase shifter","authors":"Wei-Tsung Li, Jeng‐Han Tsai, Min Huang, Tian-Wei Huang","doi":"10.1109/RFIC.2011.5940718","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940718","url":null,"abstract":"An ultra-compact reflection-type phase shifter (RTPS) with full 360° continuous phase shift and low insertion loss using standard 0.18-µm CMOS technology is demonstrated in this paper. Dual active reflection load using active inductor is utilized in the proposed reflection-type load to cover 360 ° phase tuning through only one quadrature hybrid, which has the advantages of compact chip size, low insertion loss, and low loss variation. Measurements show better than 15 dB input/output return loss, signal losses of 6.4dB±1.5dB, less than 2.4dB±0.6 dB loss variation, and a 360 ° continuously tunable range across 3.5∼4.5 GHz with 3.4mW dc power consumption. To the best of our knowledge, the proposed phase shifter has the smallest die size, 0.25 mm2, among all reported 360° C-band CMOS RTPS, which is important for a large phase array system.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122288756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940700
Bum-Kyum Kim, D. Im, Jaeyoung Choi, Kwyro Lee
A CMOS complementary capacitive loaded LNA with inductively source degeneration is implemented for 900MHz application using a 0.18-µm CMOS process. In order to achieve simultaneous input impedance and minimum noise matching, the capacitive loading technique is proposed. Owing to the capacitive loading technique, the noise figure (NF) of the proposed LNA can be perfectly close to NFmin while maintaining the source impedance matching by reducing the source degeneration inductor and gate inductor contrast to conventional cascode LNA with inductively source degeneration. The measurements demonstrate that the LNA has a power gain of 12 dB, a NF of 1 dB, an IIP3 of +7.7 dBm, and an input P1-dB of −5 dBm at 900 MHz while drawing 9 mA from a 1.8 V supply voltage.
{"title":"A low noise amplifier simultaneously achieving input impedance and minimum noise matching","authors":"Bum-Kyum Kim, D. Im, Jaeyoung Choi, Kwyro Lee","doi":"10.1109/RFIC.2011.5940700","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940700","url":null,"abstract":"A CMOS complementary capacitive loaded LNA with inductively source degeneration is implemented for 900MHz application using a 0.18-µm CMOS process. In order to achieve simultaneous input impedance and minimum noise matching, the capacitive loading technique is proposed. Owing to the capacitive loading technique, the noise figure (NF) of the proposed LNA can be perfectly close to NFmin while maintaining the source impedance matching by reducing the source degeneration inductor and gate inductor contrast to conventional cascode LNA with inductively source degeneration. The measurements demonstrate that the LNA has a power gain of 12 dB, a NF of 1 dB, an IIP3 of +7.7 dBm, and an input P1-dB of −5 dBm at 900 MHz while drawing 9 mA from a 1.8 V supply voltage.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134234376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940633
T. Taris, J. Bégueret, Y. Deval
This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are −12 dBm and −19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio.
{"title":"A 60µW LNA for 2.4 GHz wireless sensors network applications","authors":"T. Taris, J. Bégueret, Y. Deval","doi":"10.1109/RFIC.2011.5940633","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940633","url":null,"abstract":"This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are −12 dBm and −19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940618
Muhammad Hassan, M. Kwak, V. Leung, C. Hsia, Jonmei J. Yan, D. Kimball, L. Larson, P. Asbeck
A high efficiency wideband envelope tracking power amplifier with low quiescent power is presented. The CMOS envelope amplifier has a combined linear amplifier and switching amplifier to achieve high efficiency and wider bandwidth. Quiescent power of the envelope amplifier is reduced using a source cross-coupled linear amplifier with inherently low DC power dissipation. Measurements show a power added efficiency of 45% for the envelope tracking power amplifier for 20 MHz LTE signal with 6.0 dB PAPR at 2.5 GHz at 1W output power.
提出了一种低静态功率的高效宽带包络跟踪功率放大器。CMOS包络放大器采用线性放大器和开关放大器相结合的方式，实现了高效率和更宽的带宽。采用具有低直流功耗的源交叉耦合线性放大器来降低包络放大器的静态功率。测量结果表明，在输出功率为1W、2.5 GHz、6.0 dB PAPR的20 MHz LTE信号下，包络跟踪功率放大器的功率增加效率为45%。
{"title":"High efficiency envelope tracking power amplifier with very low quiescent power for 20 MHz LTE","authors":"Muhammad Hassan, M. Kwak, V. Leung, C. Hsia, Jonmei J. Yan, D. Kimball, L. Larson, P. Asbeck","doi":"10.1109/RFIC.2011.5940618","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940618","url":null,"abstract":"A high efficiency wideband envelope tracking power amplifier with low quiescent power is presented. The CMOS envelope amplifier has a combined linear amplifier and switching amplifier to achieve high efficiency and wider bandwidth. Quiescent power of the envelope amplifier is reduced using a source cross-coupled linear amplifier with inherently low DC power dissipation. Measurements show a power added efficiency of 45% for the envelope tracking power amplifier for 20 MHz LTE signal with 6.0 dB PAPR at 2.5 GHz at 1W output power.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114260586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940614
Haolu Xie, P. Rakers, R. Fernandez, Terrie McCain, J. Xiang, J. Parkes, J. Riches, R. Verellen, Mahib Rahman, Elie Shimoni, V. Bhan, D. Schwartz
A single-chip multi-mode multi-band saw-less 90nm CMOS receiver is designed and implemented for 4G mobile platform. It supports LTE/WCDMA/EGPRS standards and supports 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900), WCDMA (Bands I, II, III, IV, V, VI, VIII, IX, X and XI) and LTE (FDD Bands 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 17 and TDD bands 38 or 40). The receiver achieves a typical 3dB and maximum 4dB noise figure (NF) in all standards and bands. By using inductive source degeneration LNA architecture with 24dB passive matching voltage gain, the receiver radio frequency (RF)/analog front-end meets noise and linearity requirements for all modes and all bands with small power consumption. For example, the whole main receiver RF and analog blocks in band1 LTE 20MHz mode operate at 1.8V supply and draw total only 24mA current at maximum TX output power condition. It also automatically calibrates baseband low-pass filter cut-off frequency, mixer image rejection and IIP2 performance.
{"title":"Single-chip multi-band SAW-less LTE WCDMA and EGPRS CMOS receiver with diversity","authors":"Haolu Xie, P. Rakers, R. Fernandez, Terrie McCain, J. Xiang, J. Parkes, J. Riches, R. Verellen, Mahib Rahman, Elie Shimoni, V. Bhan, D. Schwartz","doi":"10.1109/RFIC.2011.5940614","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940614","url":null,"abstract":"A single-chip multi-mode multi-band saw-less 90nm CMOS receiver is designed and implemented for 4G mobile platform. It supports LTE/WCDMA/EGPRS standards and supports 4 GSM bands (GSM850, EGSM900, DCS1800, PCS1900), WCDMA (Bands I, II, III, IV, V, VI, VIII, IX, X and XI) and LTE (FDD Bands 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 17 and TDD bands 38 or 40). The receiver achieves a typical 3dB and maximum 4dB noise figure (NF) in all standards and bands. By using inductive source degeneration LNA architecture with 24dB passive matching voltage gain, the receiver radio frequency (RF)/analog front-end meets noise and linearity requirements for all modes and all bands with small power consumption. For example, the whole main receiver RF and analog blocks in band1 LTE 20MHz mode operate at 1.8V supply and draw total only 24mA current at maximum TX output power condition. It also automatically calibrates baseband low-pass filter cut-off frequency, mixer image rejection and IIP2 performance.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114314266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940691
D. Sandstrom, B. Martineau, M. Varonen, M. Karkkainen, A. Cathelin, K. Halonen
A power combining power amplifier utilizing cascode topology and transformer-based matching elements is presented in this paper. The amplifier achieves +13 dBm saturated output power at 94 GHz with a standard 1.2 V supply and occupies an active area of only 0.069 mm2. Amplifier is implemented in an industrial 65nm CMOS process taking into account reliability issues at high output power level. The amplifier is also ESD-protected at the input and at the output.
{"title":"94GHz power-combining power amplifier with +13dBm saturated output power in 65nm CMOS","authors":"D. Sandstrom, B. Martineau, M. Varonen, M. Karkkainen, A. Cathelin, K. Halonen","doi":"10.1109/RFIC.2011.5940691","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940691","url":null,"abstract":"A power combining power amplifier utilizing cascode topology and transformer-based matching elements is presented in this paper. The amplifier achieves +13 dBm saturated output power at 94 GHz with a standard 1.2 V supply and occupies an active area of only 0.069 mm2. Amplifier is implemented in an industrial 65nm CMOS process taking into account reliability issues at high output power level. The amplifier is also ESD-protected at the input and at the output.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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