Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940644
V. Trivedi, K. To, W. Huang
We demonstrate, using a foundry-based 65nm bulk technology, mmWave CMOS VCOs in the range of 38GHz and 77GHz with highest reported continuous tuning range (14%–25%), competitive phase noise (−88dBc/Hz at 1MHz offset at 77GHz), and high Pout (6dBm at 77GHz) needed to readily integrate with CMOS PA and to tolerate PVT variations. The DC power consumption of the 77GHz VCO is ∼190mW and that of the 38GHz VCOs is ∼60mW (∼16mW without buffer) from 1V supply (VDD). Device and design optimizations responsible for the high performance are presented. The impact of temperature and VDD variation (e.g., ∼2.6GHz shift in frequency and >5.3dB variation in Pout at 77GHz) is reported for the first time.
{"title":"A 77GHz CMOS VCO with 11.3GHz tuning range, 6dBm output power, and competitive phase noise in 65nm bulk CMOS","authors":"V. Trivedi, K. To, W. Huang","doi":"10.1109/RFIC.2011.5940644","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940644","url":null,"abstract":"We demonstrate, using a foundry-based 65nm bulk technology, mmWave CMOS VCOs in the range of 38GHz and 77GHz with highest reported continuous tuning range (14%–25%), competitive phase noise (−88dBc/Hz at 1MHz offset at 77GHz), and high Pout (6dBm at 77GHz) needed to readily integrate with CMOS PA and to tolerate PVT variations. The DC power consumption of the 77GHz VCO is ∼190mW and that of the 38GHz VCOs is ∼60mW (∼16mW without buffer) from 1V supply (VDD). Device and design optimizations responsible for the high performance are presented. The impact of temperature and VDD variation (e.g., ∼2.6GHz shift in frequency and >5.3dB variation in Pout at 77GHz) is reported for the first time.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133310852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940699
Mengdi Cao, B. Chi, Chun Zhang, Zhihua Wang
A 1.2V 0.1–3GHz software-defined radio (SDR) receiver front-end in 130nm CMOS is presented. The current-driven passive mixer with 25% duty-cycle LO and reconfigurable inverter-based RF transconductor array (TCA) is utilized to satisfy the low 1/f noise and high linearity requirements. The current buffer is implemented as a like Tow-Thomas transimpedance biquad amplifier (TIA) with built-in 2nd-order filtering and reconfigurable gain/bandwidth. The scaling power consumption along with the gain and bandwidth is achieved by utilizing the switchable amplifier approach during TCA and TIA design. The measured results show that the front-end could provide reconfigurable conversion gain from 35dB to 55dB and signal bandwidth from 3MHz to 65MHz with scaling current consumption from 14.5mA to 48.5mA, from a power supply of 1.2V. The measured noise figure (NF) and output third-order intercept point (OIP3) with the maximum gain is 3.5∼6dB and higher than 10dBm, respectively, across 0.1∼3GHz frequency range, and the die area is 2.0×1.2 mm2.
{"title":"A 1.2V 0.1–3GHz software-defined radio receiver front-end in 130nm CMOS","authors":"Mengdi Cao, B. Chi, Chun Zhang, Zhihua Wang","doi":"10.1109/RFIC.2011.5940699","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940699","url":null,"abstract":"A 1.2V 0.1–3GHz software-defined radio (SDR) receiver front-end in 130nm CMOS is presented. The current-driven passive mixer with 25% duty-cycle LO and reconfigurable inverter-based RF transconductor array (TCA) is utilized to satisfy the low 1/f noise and high linearity requirements. The current buffer is implemented as a like Tow-Thomas transimpedance biquad amplifier (TIA) with built-in 2nd-order filtering and reconfigurable gain/bandwidth. The scaling power consumption along with the gain and bandwidth is achieved by utilizing the switchable amplifier approach during TCA and TIA design. The measured results show that the front-end could provide reconfigurable conversion gain from 35dB to 55dB and signal bandwidth from 3MHz to 65MHz with scaling current consumption from 14.5mA to 48.5mA, from a power supply of 1.2V. The measured noise figure (NF) and output third-order intercept point (OIP3) with the maximum gain is 3.5∼6dB and higher than 10dBm, respectively, across 0.1∼3GHz frequency range, and the die area is 2.0×1.2 mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132173061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940635
Chenglin Cui, Tae-Sung Kim, Seong-Kyun Kim, Jun-Kyung Cho, Su-Tae Kim, Byung-sung Kim
This work presents the effects of the common-gate (CG) stage nonlinearity on the linearity of the cascode amplifier. Conventionally, the CG stage is assumed as an ideal current buffer in the CMOS cascode low noise amplifier (LNA) design, but the analysis shows that the CG stage limits the linearity of the cascode LNA as the gain increases, due to the finite output resistance of the CG stage and the parasitic capacitance at the interstage node. Therefore, the simple linearization of the CS stage has difficulties to enhance the gain of LNA as the operating frequency increases. To confirm the analysis, a 2 GHz CMOS LNA was designed and the gain and the nonlinearity were measured. The measurement results show that there exists optimum load impedance to achieve the maximum OIP3 of the LNA as expected by the analysis.
{"title":"Effects of the nonlinearity of the common-gate stage on the linearity of CMOS cascode low noise amplifier","authors":"Chenglin Cui, Tae-Sung Kim, Seong-Kyun Kim, Jun-Kyung Cho, Su-Tae Kim, Byung-sung Kim","doi":"10.1109/RFIC.2011.5940635","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940635","url":null,"abstract":"This work presents the effects of the common-gate (CG) stage nonlinearity on the linearity of the cascode amplifier. Conventionally, the CG stage is assumed as an ideal current buffer in the CMOS cascode low noise amplifier (LNA) design, but the analysis shows that the CG stage limits the linearity of the cascode LNA as the gain increases, due to the finite output resistance of the CG stage and the parasitic capacitance at the interstage node. Therefore, the simple linearization of the CS stage has difficulties to enhance the gain of LNA as the operating frequency increases. To confirm the analysis, a 2 GHz CMOS LNA was designed and the gain and the nonlinearity were measured. The measurement results show that there exists optimum load impedance to achieve the maximum OIP3 of the LNA as expected by the analysis.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130852061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940715
Sunyoung Lee, Tzung-yin Lee
This paper presents the large-signal model requirements and generation as well as the 1- and 2-tone large-signal characterization for CMOS PA applications. The sensitivity of important parameters to the large-signal prediction for a transistor is discussed. It is demonstrated that an accurate modeling of Gm as a function of bias, as well as other important extrinsic transistor parameters, enables proper prediction of the 1-tone distortion behavior for a transistor, which in turn determines the quality of prediction for the 2-tone inter-modulation product up to the 5th order.
{"title":"Large-signal characterization and modeling of MOSFET for PA applications","authors":"Sunyoung Lee, Tzung-yin Lee","doi":"10.1109/RFIC.2011.5940715","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940715","url":null,"abstract":"This paper presents the large-signal model requirements and generation as well as the 1- and 2-tone large-signal characterization for CMOS PA applications. The sensitivity of important parameters to the large-signal prediction for a transistor is discussed. It is demonstrated that an accurate modeling of Gm as a function of bias, as well as other important extrinsic transistor parameters, enables proper prediction of the 1-tone distortion behavior for a transistor, which in turn determines the quality of prediction for the 2-tone inter-modulation product up to the 5th order.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121812753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940696
Alfredo Perez-Carrillo, S. Taylor, J. Silva-Martínez, A. Karsilayan
A baseband transimpedance amplifier for coexisting radio receivers is presented. It exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers. A fully-differential prototype of the proposed solution has been designed and implemented in 45nm CMOS. Experimental results show that it can handle linearly single tones of ±10mA, withstanding blocking currents of ±9mA at 50MHz and beyond before reaching P1dB in a 10MHz bandwidth. The fabricated device occupies 0.25mm2, largely MOM finger capacitors, and draws 17mA from a 2.5V supply.
{"title":"A large-signal blocker robust transimpedance amplifier for coexisting radio receivers in 45nm CMOS","authors":"Alfredo Perez-Carrillo, S. Taylor, J. Silva-Martínez, A. Karsilayan","doi":"10.1109/RFIC.2011.5940696","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940696","url":null,"abstract":"A baseband transimpedance amplifier for coexisting radio receivers is presented. It exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers. A fully-differential prototype of the proposed solution has been designed and implemented in 45nm CMOS. Experimental results show that it can handle linearly single tones of ±10mA, withstanding blocking currents of ±9mA at 50MHz and beyond before reaching P1dB in a 10MHz bandwidth. The fabricated device occupies 0.25mm2, largely MOM finger capacitors, and draws 17mA from a 2.5V supply.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940645
L. Negre, D. Roy, F. Cacho, P. Scheer, S. Boret, A. Zaka, D. Gloria, G. Ghibaudo
In the framework of MOSFET reliability for mixed-analog application, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stress with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.
{"title":"Aging of 40nm MOSFET RF parameters under RF conditions from characterization to compact modeling for RF design","authors":"L. Negre, D. Roy, F. Cacho, P. Scheer, S. Boret, A. Zaka, D. Gloria, G. Ghibaudo","doi":"10.1109/RFIC.2011.5940645","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940645","url":null,"abstract":"In the framework of MOSFET reliability for mixed-analog application, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stress with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121096762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940639
S. Wane, R. van Heijster, S. Bardy
This paper presents design solutions for signal detectors and Antenna on-Chip (AoC) using a state-of-the-art (SiGe) BiCMOS technology. Both CML (Current-Mode-Logic) and CMOS detectors are designed, fabricated and compared in terms of their performances such as conversion gain and robustness against process variations. Wide-band Antenna-on-Chip working in the range 60GHz to 94 GHz are designed, fabricated and characterized. Several Antenna-on-Chip structures are proposed to evaluate bandwidth and radiation efficiency performances. Near-field antenna couplings are experimentally evaluated using different technology variants with different silicon substrate thickness values. Schottky diodes are designed and characterized for feasibility analysis of THz detection, mixing and down-conversion.
{"title":"Integration of Antenna-on-Chip and signal detectors for applications from RF to THz frequency range in SiGe technology","authors":"S. Wane, R. van Heijster, S. Bardy","doi":"10.1109/RFIC.2011.5940639","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940639","url":null,"abstract":"This paper presents design solutions for signal detectors and Antenna on-Chip (AoC) using a state-of-the-art (SiGe) BiCMOS technology. Both CML (Current-Mode-Logic) and CMOS detectors are designed, fabricated and compared in terms of their performances such as conversion gain and robustness against process variations. Wide-band Antenna-on-Chip working in the range 60GHz to 94 GHz are designed, fabricated and characterized. Several Antenna-on-Chip structures are proposed to evaluate bandwidth and radiation efficiency performances. Near-field antenna couplings are experimentally evaluated using different technology variants with different silicon substrate thickness values. Schottky diodes are designed and characterized for feasibility analysis of THz detection, mixing and down-conversion.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115914332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940714
N. Singhal, N. Nidhi, Abhishek Ghosh, S. Pamarti
This paper implements a digital Zero Voltage Switching (ZVS) Contour based power amplifier previously proposed by the authors in [1]. The proposed PA implemented in 0.13µm digital CMOS technology, achieves a peak power of 19dBm at a peak drain efficiency of 23% and peak power added efficiency (PAE) of 18% at a center frequency of 800MHz from a 1.2V supply. The PA can maintain its peak efficiency over a 6dB dynamic range of output power by a simultaneous load and duty cycle modulation of a parallel class E PA. The PA achieves an average drain efficiency of 20% and an average PAE of 15% while generating 6dB peak to minimum ratio (PMR) OQPSK signal with bandwidths up to 20Mbps.
{"title":"A 19 dBm 0.13µm CMOS parallel class-E switching PA with minimal efficiency degradation under 6 dB back-off","authors":"N. Singhal, N. Nidhi, Abhishek Ghosh, S. Pamarti","doi":"10.1109/RFIC.2011.5940714","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940714","url":null,"abstract":"This paper implements a digital Zero Voltage Switching (ZVS) Contour based power amplifier previously proposed by the authors in [1]. The proposed PA implemented in 0.13µm digital CMOS technology, achieves a peak power of 19dBm at a peak drain efficiency of 23% and peak power added efficiency (PAE) of 18% at a center frequency of 800MHz from a 1.2V supply. The PA can maintain its peak efficiency over a 6dB dynamic range of output power by a simultaneous load and duty cycle modulation of a parallel class E PA. The PA achieves an average drain efficiency of 20% and an average PAE of 15% while generating 6dB peak to minimum ratio (PMR) OQPSK signal with bandwidths up to 20Mbps.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"58 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940687
Yi Zhao, J. Long, M. Spirito
A three-stage, 60GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-BiCMOS. Common-base differential pair stages extend BVCEO, while neutralization increases isolation, promoting stability. Self-shielded transformers, a parasitic-compensated 4∶1 output combiner and 2∶4 input splitter are designed for low insertion loss and compact dimensions on-chip. Measured small-signal gain is >20dB with over 10GHz −3dB bandwidth. Reverse isolation is better than 51dB across 50–65GHz. Maximum output power and peak-PAE are 20.5dBm and 20%, respectively, at 61.5GHz. The PA consumes 353mW from a 1.8V supply and 0.25mm2 active area.
{"title":"A 60GHz-band 20dBm power amplifier with 20% peak PAE","authors":"Yi Zhao, J. Long, M. Spirito","doi":"10.1109/RFIC.2011.5940687","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940687","url":null,"abstract":"A three-stage, 60GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-BiCMOS. Common-base differential pair stages extend BVCEO, while neutralization increases isolation, promoting stability. Self-shielded transformers, a parasitic-compensated 4∶1 output combiner and 2∶4 input splitter are designed for low insertion loss and compact dimensions on-chip. Measured small-signal gain is >20dB with over 10GHz −3dB bandwidth. Reverse isolation is better than 51dB across 50–65GHz. Maximum output power and peak-PAE are 20.5dBm and 20%, respectively, at 61.5GHz. The PA consumes 353mW from a 1.8V supply and 0.25mm2 active area.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116629129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940668
Chun-Cheng Wang, Zhiming Chen, Hsin-Cheng Yao, P. Heydari
A fully integrated 96GHz 2×2 focal-plane array (FPA) direct conversion imager in 0.18µm SiGe BiCMOS (fT/ƒmax=200/180GHz) employing four integrated antennas with Dicke switches and LO generation/distribution is presented. The PLL plus tripler achieves a locking range of 92.67–98.2GHz and phase noise of −93dBc/Hz at 96GHz measured at 1MHz offset. The 3.5×3mm2 chip achieves an average responsivity and NEP of 285MV/W and 8.1fW/√Hz, respectively, across 86–106GHz band and an NETD of 0.48K. The chip consumes 695mW from 1.8V/2.5V supplies.
{"title":"A fully integrated 96GHz 2×2 focal-plane array with On-Chip antenna","authors":"Chun-Cheng Wang, Zhiming Chen, Hsin-Cheng Yao, P. Heydari","doi":"10.1109/RFIC.2011.5940668","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940668","url":null,"abstract":"A fully integrated 96GHz 2×2 focal-plane array (FPA) direct conversion imager in 0.18µm SiGe BiCMOS (f<inf>T</inf>/ƒ<inf>max</inf>=200/180GHz) employing four integrated antennas with Dicke switches and LO generation/distribution is presented. The PLL plus tripler achieves a locking range of 92.67–98.2GHz and phase noise of −93dBc/Hz at 96GHz measured at 1MHz offset. The 3.5×3mm<sup>2</sup> chip achieves an average responsivity and NEP of 285MV/W and 8.1fW/√Hz, respectively, across 86–106GHz band and an NETD of 0.48K. The chip consumes 695mW from 1.8V/2.5V supplies.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129775749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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