Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940716
S. Wane, M. Ranaivoniarivo, B. Elkassir, C. Kelma, P. Gamand
This paper introduces the concept of cognitive wireless BIST system for reconfigurability of on-chip function blocks, towards contactless measurement and characterization of high frequency integrated systems. Proposed feasibility studies of cognitive BIST cover characterization of chip-to-chip noise interferences as function of wireless coupling-path attributes (wireless separation distance between emitter and receiver chips, injected power levels, Charge-Pump-Current). Study of BIST for reconfigurability of on-chip functions is conducted based on design of programmable automatic amplitude control (ALC) of PLL reference oscillators. Impacts of BIST circuits on system performances are evaluated based on simulation analysis and experimental verifications.
{"title":"Towards cognitive built-in-self-test (BIST) for reconfigurable on-chip applications, and contact-less measurement","authors":"S. Wane, M. Ranaivoniarivo, B. Elkassir, C. Kelma, P. Gamand","doi":"10.1109/RFIC.2011.5940716","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940716","url":null,"abstract":"This paper introduces the concept of cognitive wireless BIST system for reconfigurability of on-chip function blocks, towards contactless measurement and characterization of high frequency integrated systems. Proposed feasibility studies of cognitive BIST cover characterization of chip-to-chip noise interferences as function of wireless coupling-path attributes (wireless separation distance between emitter and receiver chips, injected power levels, Charge-Pump-Current). Study of BIST for reconfigurability of on-chip functions is conducted based on design of programmable automatic amplitude control (ALC) of PLL reference oscillators. Impacts of BIST circuits on system performances are evaluated based on simulation analysis and experimental verifications.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940711
Fan Zhang, Matthew A. Stoneback, B. Otis
We propose a new tag architecture that employs an active transmitter to decouple the frequencies used for power and data telemetry. Receiving power at 918 MHz and transmitting data at 306 MHz eliminates the “self-jamming” problem presented to RFID readers, reducing the complexity of reader design. This scheme allows remote placement of the data receiver and extends the data transmission range. Our transmitter uses subharmonic injection-locking to avoid power hungry LO generation circuitry while eliminating the need for quartz crystals. The tag prototype was fabricated using a 0.13 µm CMOS process, occupying 0.3 mm2 active area. With an on-off keying (OOK) data rate of 4 Mbps, the 23 µA transmitter with an output power of −33 dBm achieves an energy efficiency of 10 pJ/bit, the best reported to date for such systems.
{"title":"A 23 µA RF-powered transmitter for biomedical applications","authors":"Fan Zhang, Matthew A. Stoneback, B. Otis","doi":"10.1109/RFIC.2011.5940711","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940711","url":null,"abstract":"We propose a new tag architecture that employs an active transmitter to decouple the frequencies used for power and data telemetry. Receiving power at 918 MHz and transmitting data at 306 MHz eliminates the “self-jamming” problem presented to RFID readers, reducing the complexity of reader design. This scheme allows remote placement of the data receiver and extends the data transmission range. Our transmitter uses subharmonic injection-locking to avoid power hungry LO generation circuitry while eliminating the need for quartz crystals. The tag prototype was fabricated using a 0.13 µm CMOS process, occupying 0.3 mm2 active area. With an on-off keying (OOK) data rate of 4 Mbps, the 23 µA transmitter with an output power of −33 dBm achieves an energy efficiency of 10 pJ/bit, the best reported to date for such systems.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114966216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940659
Edward P. Coleman, S. Chakraborty, Walter A. Budziak, Theodore R. Blank, P. T. Røine
This paper illustrates the design of a process compensated bias for asynchronous CML dividers for a low power, high performance LO divide chain operating at 4Ghz of input RF frequency. The divider chain provides division by 4,8,12,16,20, and 24. It provides a differential CML level signal for the in-loop modulated transmitter, and 25% duty cycle non-overlapping rail to rail waveforms for I/Q receiver for driving passive mixer. Asynchronous dividers have been used to realize divide by 3 and 5 with 50% duty cycle, quadrature outputs. All the CML dividers use a process compensated bias to compensate for load resistor variation and tail current variation using dual analog feedback loops. Frabricated in 180nm CMOS technology, the divider chain operate over industrial temperature range (−40 to 90°C), and provide outputs in 138–960Mhz range, consuming 2.2mA from 1.8V regulated supply at the highest output frequency.
{"title":"Process compensated low power LO divider chain with asynchronous odd integer 50% duty cycle CML dividers","authors":"Edward P. Coleman, S. Chakraborty, Walter A. Budziak, Theodore R. Blank, P. T. Røine","doi":"10.1109/RFIC.2011.5940659","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940659","url":null,"abstract":"This paper illustrates the design of a process compensated bias for asynchronous CML dividers for a low power, high performance LO divide chain operating at 4Ghz of input RF frequency. The divider chain provides division by 4,8,12,16,20, and 24. It provides a differential CML level signal for the in-loop modulated transmitter, and 25% duty cycle non-overlapping rail to rail waveforms for I/Q receiver for driving passive mixer. Asynchronous dividers have been used to realize divide by 3 and 5 with 50% duty cycle, quadrature outputs. All the CML dividers use a process compensated bias to compensate for load resistor variation and tail current variation using dual analog feedback loops. Frabricated in 180nm CMOS technology, the divider chain operate over industrial temperature range (−40 to 90°C), and provide outputs in 138–960Mhz range, consuming 2.2mA from 1.8V regulated supply at the highest output frequency.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115054748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940663
Hongrui Wang, Dajie Zeng, Dongxu Yang, Li Zhang, Lei Zhang, Yan Wang, H. Qian, Zhiping Yu
Coplanar waveguides (CPW) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R, and G parameters. Started from a standard CPW structure, influences of different kinds of ground shields have been analyzed and included into the general model. The accuracy of the model is confirmed by experimental results.
{"title":"A unified model for on-chip CPWs with various types of ground shields","authors":"Hongrui Wang, Dajie Zeng, Dongxu Yang, Li Zhang, Lei Zhang, Yan Wang, H. Qian, Zhiping Yu","doi":"10.1109/RFIC.2011.5940663","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940663","url":null,"abstract":"Coplanar waveguides (CPW) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R, and G parameters. Started from a standard CPW structure, influences of different kinds of ground shields have been analyzed and included into the general model. The accuracy of the model is confirmed by experimental results.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122677672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940619
Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang
We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.
{"title":"A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS","authors":"Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2011.5940619","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940619","url":null,"abstract":"We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"23 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125085077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940651
Iliana Fujimori-Chen, B. Walker, Roxann Broughton-Blanchard, E. Balboni
This paper presents a broadband, high-dynamic range, active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-n/fractional-n PLL to generate an LO signal with an in-band phase noise FOM of −223 dBc/Hz/Hz. The 100–3000MHz active mixer can be configured for up or down conversion. The mixer's linearity can be boosted from +25dBm to +29dBm by increasing the bias current, and optimized for a wide range of input frequencies through a variable capacitor setting. Designed in Si-Ge 0.25µm BiCMOS, the entire chip occupies 5.84mm2 and consumes 250mA from a 5V supply.
{"title":"A 100-3000MHz, up/ down-convert, +29dBm IIP3, 13dB NF, active mixer with integrated fractional-N PLL and VCO","authors":"Iliana Fujimori-Chen, B. Walker, Roxann Broughton-Blanchard, E. Balboni","doi":"10.1109/RFIC.2011.5940651","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940651","url":null,"abstract":"This paper presents a broadband, high-dynamic range, active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-n/fractional-n PLL to generate an LO signal with an in-band phase noise FOM of −223 dBc/Hz/Hz. The 100–3000MHz active mixer can be configured for up or down conversion. The mixer's linearity can be boosted from +25dBm to +29dBm by increasing the bias current, and optimized for a wide range of input frequencies through a variable capacitor setting. Designed in Si-Ge 0.25µm BiCMOS, the entire chip occupies 5.84mm2 and consumes 250mA from a 5V supply.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123342887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940630
Jonathan K. Brown, D. Wentzloff
A 0.13µm CMOS clock-harvesting receiver is presented which extracts a 21Hz clock embedded within the GSM standard for the wake-up of a wireless sensor network. In active mode, the receiver achieves −87dBm sensitivity with 57µs of jitter at the output while consuming 126µW. The receiver is optimized for heavy duty-cycling with a sleep-mode power consumption of only 81pW.
提出了一种0.13 μ m CMOS时钟采集接收器，该接收器提取嵌入GSM标准的21Hz时钟，用于无线传感器网络的唤醒。在主动模式下，接收器达到−87dBm灵敏度，输出抖动为57µs，功耗为126µW。该接收器针对重占空比进行了优化，睡眠模式功耗仅为81pW。
{"title":"A 1900MHz-band GSM-based clock-harvesting receiver with −87dBm sensitivity","authors":"Jonathan K. Brown, D. Wentzloff","doi":"10.1109/RFIC.2011.5940630","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940630","url":null,"abstract":"A 0.13µm CMOS clock-harvesting receiver is presented which extracts a 21Hz clock embedded within the GSM standard for the wake-up of a wireless sensor network. In active mode, the receiver achieves −87dBm sensitivity with 57µs of jitter at the output while consuming 126µW. The receiver is optimized for heavy duty-cycling with a sleep-mode power consumption of only 81pW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123390596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940662
B. Dormieu, C. Charbuillet, F. Danneville, N. Kauffmann, P. Scheer
This paper presents a novel methodology for the extraction of the substrate network components in n-MOS isolated devices, based on original “Gate-Bulk” structures. Since the main model acceptance criteria is here the frequency dependency, a large part is devoted to accurately model distributed effects in the p-well and the deep n-well layers up to 80 GHz. The main structures are completed with intermediate structures which give a better understanding of the substrate distribution effects.
{"title":"Millimeter-wave modeling of isolated MOS substrate network through gate-bulk measurements","authors":"B. Dormieu, C. Charbuillet, F. Danneville, N. Kauffmann, P. Scheer","doi":"10.1109/RFIC.2011.5940662","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940662","url":null,"abstract":"This paper presents a novel methodology for the extraction of the substrate network components in n-MOS isolated devices, based on original “Gate-Bulk” structures. Since the main model acceptance criteria is here the frequency dependency, a large part is devoted to accurately model distributed effects in the p-well and the deep n-well layers up to 80 GHz. The main structures are completed with intermediate structures which give a better understanding of the substrate distribution effects.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127687857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940681
W. Deng, K. Okada, A. Matsuzawa
This paper proposes a wide tuning range VCO for multi-band frequency generation. The wide band oscillator consists of a dual-mode LC-VCO using a 5-port inductor, and a divider chain. The proposed 5-port inductor provides two different inductances, which could support two resonances in a compact chip area. Thus, for LC-VCO, two operation modes are obtained to increase the tuning range. The experimental results achieve 25MHz-to-6.44GHz of continuous tuning range with a FoMT of −209 dBc/Hz.
{"title":"A 25MHz–6.44GHz LC-VCO using a 5-port inductor for multi-band frequency generation","authors":"W. Deng, K. Okada, A. Matsuzawa","doi":"10.1109/RFIC.2011.5940681","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940681","url":null,"abstract":"This paper proposes a wide tuning range VCO for multi-band frequency generation. The wide band oscillator consists of a dual-mode LC-VCO using a 5-port inductor, and a divider chain. The proposed 5-port inductor provides two different inductances, which could support two resonances in a compact chip area. Thus, for LC-VCO, two operation modes are obtained to increase the tuning range. The experimental results achieve 25MHz-to-6.44GHz of continuous tuning range with a FoMT of −209 dBc/Hz.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127891807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940672
A. Arbabian, Shinwon Kang, Steven Callender, B. Afshar, Jun-Chau Chien, A. Niknejad
A reflective, dual-loop, switching antenna utilizing near-field/far-field energy cancellation is integrated in a 90 GHz pulsed transmitter (TX). The TX features high ON/OFF ratio, good antenna efficiency and PRF up to 3.45GHz. It achieves TX power of 10dBm with 18dB of power tuning. The pulse width is tunable between 46ps to 310ps and initial bistatic measurements distinguish 4 reflectors across a 6cm region signifying progress towards the development of a diagnostic medical imager in silicon.
{"title":"A 90GHz pulsed-transmitter with near-field/far-field energy cancellation using a dual-loop antenna","authors":"A. Arbabian, Shinwon Kang, Steven Callender, B. Afshar, Jun-Chau Chien, A. Niknejad","doi":"10.1109/RFIC.2011.5940672","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940672","url":null,"abstract":"A reflective, dual-loop, switching antenna utilizing near-field/far-field energy cancellation is integrated in a 90 GHz pulsed transmitter (TX). The TX features high ON/OFF ratio, good antenna efficiency and PRF up to 3.45GHz. It achieves TX power of 10dBm with 18dB of power tuning. The pulse width is tunable between 46ps to 310ps and initial bistatic measurements distinguish 4 reflectors across a 6cm region signifying progress towards the development of a diagnostic medical imager in silicon.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126543980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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