Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940638
Chi-Shin Kuo, Hsin-Chih Kuo, H. Chuang, Chu‐Yu Chen, Tzuen-Hsi Huang
This paper presents a 60GHz high-isolation CMOS single-pole double-throw (SPDT) transmitter/receiver (T/R) switch fabricated with TSMC standard 90-nm 1P9M CMOS technology. A low insertion loss and high linearity are achieved by using the body-floating technique. The leakage cancellation technique is used to increase the isolation between the transmitter and receiver ports. The top metal (M9) is mainly adopted for designing signal paths and the microstrip-line matching elements. In order to minimize the substrate loss, the first metal (M1) as the ground plane is used in this design. The measured results show the insertion loss from the transmitter port to the antenna port is less than 3.5 dB, and the isolation between the transmitter and receiver ports is higher than 28 dB from 57 to 64GHz. At the center frequency of 60GHz, the port isolation is higher than 34 dB and the input 1-dB compression point (IP1dB) is +6.9 dBm.
{"title":"A high-isolation 60GHz CMOS transmit/receive switch","authors":"Chi-Shin Kuo, Hsin-Chih Kuo, H. Chuang, Chu‐Yu Chen, Tzuen-Hsi Huang","doi":"10.1109/RFIC.2011.5940638","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940638","url":null,"abstract":"This paper presents a 60GHz high-isolation CMOS single-pole double-throw (SPDT) transmitter/receiver (T/R) switch fabricated with TSMC standard 90-nm 1P9M CMOS technology. A low insertion loss and high linearity are achieved by using the body-floating technique. The leakage cancellation technique is used to increase the isolation between the transmitter and receiver ports. The top metal (M9) is mainly adopted for designing signal paths and the microstrip-line matching elements. In order to minimize the substrate loss, the first metal (M1) as the ground plane is used in this design. The measured results show the insertion loss from the transmitter port to the antenna port is less than 3.5 dB, and the isolation between the transmitter and receiver ports is higher than 28 dB from 57 to 64GHz. At the center frequency of 60GHz, the port isolation is higher than 34 dB and the input 1-dB compression point (IP1dB) is +6.9 dBm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124675170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940594
Subhanshu Gupta, Daibashish Gangopadhyay, H. Lakdawala, J. Rudell, D. Allstot
A direct-RF sampled band-pass ΣΔ modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete sampling receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 µm CMOS, it consumes 41 mW and achieves maximum SNDR values of 50 dB, 46 dB and 40 dB over a 1 MHz bandwidth with 796.5 MHz, 1.001 GHz and 1.924 GHz input carrier frequencies. The measured PLL phase noise is −113 dBc/Hz at an offset frequency of 1 MHz with a −74.5 dBc carrier-reference spur; the RMS period jitter is 1.38 ps at 3.2 GHz.
{"title":"A QPLL-timed direct-RF sampling band-pass ΣΔ ADC with a 1.2 GHz tuning range in 0.13 µm CMOS","authors":"Subhanshu Gupta, Daibashish Gangopadhyay, H. Lakdawala, J. Rudell, D. Allstot","doi":"10.1109/RFIC.2011.5940594","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940594","url":null,"abstract":"A direct-RF sampled band-pass ΣΔ modulator enables reconfigurable RF A/D conversion. It features a programmable narrow-band Q-enhanced low-noise amplifier and a phase-locked loop implemented using a low-phase-noise injection-locked harmonic-filtering quadrature voltage-controlled oscillator. The quadrature outputs of the PLL provide phase synchronization between a raised-cosine DAC and the quantizer. The three-tap raised-cosine finite-impulse response filter is embedded in the RF DAC. A complete sampling receiver demonstrates progress towards Software-Defined Radio (SDR) applications. Implemented in 0.13 µm CMOS, it consumes 41 mW and achieves maximum SNDR values of 50 dB, 46 dB and 40 dB over a 1 MHz bandwidth with 796.5 MHz, 1.001 GHz and 1.924 GHz input carrier frequencies. The measured PLL phase noise is −113 dBc/Hz at an offset frequency of 1 MHz with a −74.5 dBc carrier-reference spur; the RMS period jitter is 1.38 ps at 3.2 GHz.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124760182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940603
N. Wang, Hao Wu, J. Liu, Jianhua Lu, H. Hsieh, Po-Yi Wu, C. Jou, Mau-Chung Frank Chang
A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive gm-enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.
{"title":"A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive Gm-enhancement","authors":"N. Wang, Hao Wu, J. Liu, Jianhua Lu, H. Hsieh, Po-Yi Wu, C. Jou, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2011.5940603","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940603","url":null,"abstract":"A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive gm-enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130563504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940641
A. Jooyaie, M. F. Chang
A technique to achieve an extended continuous tuning range for Voltage Controlled Oscillators (VCO) is presented. The technique is scalable and the theory could be applied to achieve wide tuning range VCOs operating at arbitrary center frequency; however, it is more desirable at mm-wave regime (V-Band in this case) as it alleviates the need for switches and big varactor banks. The technique incorporated here relies on separate E and H mode excitation of the resonator, while avoiding the Q-degrading switches. The standing-wave V-band VCO reported here is implemented in 65-nm CMOS technology and achieves a continuous tuning range from 58 GHz to 76.2 GHz, with an average phase noise of −89.5 dBc/Hz at 1 MHz offset across the entire band, consumes an average of 5.8 mW (excluding the output buffers), and thus achieves a record FoM.
{"title":"A V-band Voltage Controlled Oscillator with greater than 18GHz of continuous tuning-range based on orthogonal E mode and H mode control","authors":"A. Jooyaie, M. F. Chang","doi":"10.1109/RFIC.2011.5940641","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940641","url":null,"abstract":"A technique to achieve an extended continuous tuning range for Voltage Controlled Oscillators (VCO) is presented. The technique is scalable and the theory could be applied to achieve wide tuning range VCOs operating at arbitrary center frequency; however, it is more desirable at mm-wave regime (V-Band in this case) as it alleviates the need for switches and big varactor banks. The technique incorporated here relies on separate E and H mode excitation of the resonator, while avoiding the Q-degrading switches. The standing-wave V-band VCO reported here is implemented in 65-nm CMOS technology and achieves a continuous tuning range from 58 GHz to 76.2 GHz, with an average phase noise of −89.5 dBc/Hz at 1 MHz offset across the entire band, consumes an average of 5.8 mW (excluding the output buffers), and thus achieves a record FoM.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"11 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114223715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940708
A. Nelson, Julie R. Hu, J. Kaitila, R. Ruby, B. Otis
We present a 22µW, 2.0GHz FBAR oscillator - the lowest power reported to date for a GHz-range oscillator of this type. Low power consumption is achieved through co-design with a high Rp FBAR resonator and a weakly-forward biased bulk connection. An oscillator with a standard bulk connection was fabricated for comparison. The chip was fabricated in a 0.18µm CMOS process. The weakly-forward biased bulk led to a 41% reduction in power dissipation. The measured phase noise is −121dBc/Hz at a 100kHz offset.
我们提出了一个22µW, 2.0GHz的FBAR振荡器，这是迄今为止报道的该类型ghz范围振荡器的最低功率。通过与高Rp FBAR谐振器和弱正向偏置体连接的共同设计，实现了低功耗。为了进行比较，制作了一个具有标准本体连接的振荡器。该芯片采用0.18 μ m CMOS工艺制造。弱正向偏置体导致功耗降低41%。在100kHz偏移时，测量到的相位噪声为- 121dBc/Hz。
{"title":"A 22µW, 2.0GHz FBAR oscillator","authors":"A. Nelson, Julie R. Hu, J. Kaitila, R. Ruby, B. Otis","doi":"10.1109/RFIC.2011.5940708","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940708","url":null,"abstract":"We present a 22µW, 2.0GHz FBAR oscillator - the lowest power reported to date for a GHz-range oscillator of this type. Low power consumption is achieved through co-design with a high Rp FBAR resonator and a weakly-forward biased bulk connection. An oscillator with a standard bulk connection was fabricated for comparison. The chip was fabricated in a 0.18µm CMOS process. The weakly-forward biased bulk led to a 41% reduction in power dissipation. The measured phase noise is −121dBc/Hz at a 100kHz offset.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125464376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940634
Chang-Jin Jeong, W. Qu, Yang Sun, Dae-Young Yoon, Sok-Kyun Han, S. Lee
This paper presents design guidelines for ultra-low power Low Noise Amplifier (LNA) design by comparing input matching, gain, and noise figure (NF) characteristics of common-source (CS) and common-gate (CG) topologies. A current-reused ultra-low power 2.2 GHz CG LNA is proposed and implemented based on 0.18 um CMOS technology. Measurement results show 13.9 dB power gain, 5.14 dB NF, and −9.3 dBm IIP3, respectively, while dissipating 140 uA from a 1.5 V supply, which shows best figure of merit (FOM) among all published ultra-low power LNAs.
{"title":"A 1.5V, 140µA CMOS ultra-low power common-gate LNA","authors":"Chang-Jin Jeong, W. Qu, Yang Sun, Dae-Young Yoon, Sok-Kyun Han, S. Lee","doi":"10.1109/RFIC.2011.5940634","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940634","url":null,"abstract":"This paper presents design guidelines for ultra-low power Low Noise Amplifier (LNA) design by comparing input matching, gain, and noise figure (NF) characteristics of common-source (CS) and common-gate (CG) topologies. A current-reused ultra-low power 2.2 GHz CG LNA is proposed and implemented based on 0.18 um CMOS technology. Measurement results show 13.9 dB power gain, 5.14 dB NF, and −9.3 dBm IIP3, respectively, while dissipating 140 uA from a 1.5 V supply, which shows best figure of merit (FOM) among all published ultra-low power LNAs.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122211211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940670
H. Sherry, R. Al Hadi, J. Grzyb, E. Ojefors, A. Cathelin, A. Kaiser, U. Pfeiffer
THz CMOS imagers integrated with hyperhemispherical Si-lenses are presented and characterized. FPAs are implemented in 65nm CMOS bulk and SOI technologies. Lens-integrated detectors at 0.65 THz show an increase of 15dB and 20dB in SNR compared to front-side illumination for SOI and bulk respectively. The responsivities Rv are increased and a minimum noise-equivalent power NEP of 17pW/√Hz is measured for SOI detectors with the lens. THz Images are presented.
{"title":"Lens-integrated THz imaging arrays in 65nm CMOS technologies","authors":"H. Sherry, R. Al Hadi, J. Grzyb, E. Ojefors, A. Cathelin, A. Kaiser, U. Pfeiffer","doi":"10.1109/RFIC.2011.5940670","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940670","url":null,"abstract":"THz CMOS imagers integrated with hyperhemispherical Si-lenses are presented and characterized. FPAs are implemented in 65nm CMOS bulk and SOI technologies. Lens-integrated detectors at 0.65 THz show an increase of 15dB and 20dB in SNR compared to front-side illumination for SOI and bulk respectively. The responsivities Rv are increased and a minimum noise-equivalent power NEP of 17pW/√Hz is measured for SOI detectors with the lens. THz Images are presented.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128162836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940613
Xiao Y. Wang, R. Dokania, Yi Zhuang, W. Godycki, Carlos I. Dorta-Quiñones, Michael Lyons, A. Apsel
An 86µW, 150Kbps, self synchronizing 3.5–4.5GHz UWB IR transceiver is presented. Synchronous receiver duty cycling of 0.5% is enabled without a crystal through a pulse coupled oscillator (PCO) network that establishes timing and allows multi-node multi-hop communication. The synchronization scheme is supported by implementation of low power oscillator and timing circuits to control duty-cycling. Our FCC compliant transceiver uses OOK modulation and has a receiver sensitivity of −86dBm.
{"title":"A self-synchronized, crystal-less, 86µW, dual-band impulse radio for ad-hoc wireless networks","authors":"Xiao Y. Wang, R. Dokania, Yi Zhuang, W. Godycki, Carlos I. Dorta-Quiñones, Michael Lyons, A. Apsel","doi":"10.1109/RFIC.2011.5940613","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940613","url":null,"abstract":"An 86µW, 150Kbps, self synchronizing 3.5–4.5GHz UWB IR transceiver is presented. Synchronous receiver duty cycling of 0.5% is enabled without a crystal through a pulse coupled oscillator (PCO) network that establishes timing and allows multi-node multi-hop communication. The synchronization scheme is supported by implementation of low power oscillator and timing circuits to control duty-cycling. Our FCC compliant transceiver uses OOK modulation and has a receiver sensitivity of −86dBm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"537 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133356163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940616
C. Izquierdo, A. Kaiser, F. Montaudon, P. Cathelin
A wide-band receiver for multi-band multi-standard cellular applications with a positive feed-back translational loop is presented in this paper. This technique allows tunable RF filtering right on the input node of the LNA with the base-band filter selectivity. The architecture is highly reconfigurable both regarding the RF channel center frequency and the channel bandwidth. The 65nm CMOS prototype circuit achieves, when in WCDMA mode, attenuation of out-of-band interferers of 12dB at 20MHz frequency offset, improving the out-of-band IIP3 by 17dB. The packaged test-chip provides good performance over a very wide frequency range from 1.3GHz to 2.85GHz.
{"title":"Reconfigurable wide-band receiver with positive feed-back translational loop","authors":"C. Izquierdo, A. Kaiser, F. Montaudon, P. Cathelin","doi":"10.1109/RFIC.2011.5940616","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940616","url":null,"abstract":"A wide-band receiver for multi-band multi-standard cellular applications with a positive feed-back translational loop is presented in this paper. This technique allows tunable RF filtering right on the input node of the LNA with the base-band filter selectivity. The architecture is highly reconfigurable both regarding the RF channel center frequency and the channel bandwidth. The 65nm CMOS prototype circuit achieves, when in WCDMA mode, attenuation of out-of-band interferers of 12dB at 20MHz frequency offset, improving the out-of-band IIP3 by 17dB. The packaged test-chip provides good performance over a very wide frequency range from 1.3GHz to 2.85GHz.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940632
Z. Safarian, H. Hashemi
A scheme for a wirelessly-powered passive sensor is presented in which the extra received power beyond the sensitivity level is stored and later used to enhance the sensitivity of the wireless sensor. A prototype chip has been designed and fabricated in a 0.13µm CMOS technology. The measurement results show that the aforementioned energy storage mechanism improves the sensitivity of the wireless sensor from −19.5dBm to −29dBm at 900MHz and from −15.4dBm to −26.5dBm at 2.4GHz.
提出了一种无线供电无源传感器的方案，该方案将接收到的超出灵敏度水平的额外功率存储起来，然后用于提高无线传感器的灵敏度。采用0.13 μ m CMOS技术设计并制作了原型芯片。测量结果表明，上述储能机制将无线传感器的灵敏度从900MHz时的- 19.5dBm提高到- 29dBm，在2.4GHz时的- 15.4dBm提高到- 26.5dBm。
{"title":"A wirelessly-powered passive RF CMOS transponder with dynamic energy storage and sensitivity enhancement","authors":"Z. Safarian, H. Hashemi","doi":"10.1109/RFIC.2011.5940632","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940632","url":null,"abstract":"A scheme for a wirelessly-powered passive sensor is presented in which the extra received power beyond the sensitivity level is stored and later used to enhance the sensitivity of the wireless sensor. A prototype chip has been designed and fabricated in a 0.13µm CMOS technology. The measurement results show that the aforementioned energy storage mechanism improves the sensitivity of the wireless sensor from −19.5dBm to −29dBm at 900MHz and from −15.4dBm to −26.5dBm at 2.4GHz.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134619465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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