Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940695
Wooram Lee, E. Afshari
A LNA using noise squeezing is designed in a 65 nm CMOS. The noise squeezing occurs through phase sensitive gain implemented by parametric process. This process is carried out inside a nonlinear resonator where energy transfers from a pump to the signal. When the pump frequency is twice that of the signal, the amplifier suppresses one of two quadrature components of the input noise. This concept is exploited to realize an 8 GHz LNA with 0.45 dB NF for non-suppressed quadrature.
设计了一种基于噪声压缩的65纳米CMOS LNA。噪声压缩是通过参数化过程实现的相敏增益实现的。这个过程在一个非线性谐振腔内进行，其中能量从泵传递到信号。当泵浦频率是信号频率的两倍时，放大器抑制输入噪声的两个正交分量中的一个。利用这一概念实现了具有0.45 dB NF的8 GHz LNA，用于非抑制正交。
{"title":"An 8GHz, 0.45dB NF CMOS LNA employing noise squeezing","authors":"Wooram Lee, E. Afshari","doi":"10.1109/RFIC.2011.5940695","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940695","url":null,"abstract":"A LNA using noise squeezing is designed in a 65 nm CMOS. The noise squeezing occurs through phase sensitive gain implemented by parametric process. This process is carried out inside a nonlinear resonator where energy transfers from a pump to the signal. When the pump frequency is twice that of the signal, the amplifier suppresses one of two quadrature components of the input noise. This concept is exploited to realize an 8 GHz LNA with 0.45 dB NF for non-suppressed quadrature.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134621405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940705
N. Buadana, E. Socher
A compact, triple output travelling wave oscillator with combined analog and digital control is presented. The oscillator is based on an eight phase rotary travelling wave oscillator employing shielded digitally controlled transmission lines. The oscillator drives an output buffer, a push-push buffer and a quad-push to generate X, K and Q band outputs simultaneously. Fabricated in standard 0.18µm CMOS it occupies 0.48 mm2 and consumes a DC power of 64mW, including pads and buffers. The circuit exhibits 5.5% tuning range in each band with potential 1MHz digital step resolution. With a phase noise of −108 dBc/Hz at 1MHz offset and −1dBm of output power measured at the fundamental frequency, the circuit is a promising candidate for mm-wave software defined radios and digitals PLLs.
{"title":"A triple band travelling wave VCO using digitally controlled artificial dielectric transmission lines","authors":"N. Buadana, E. Socher","doi":"10.1109/RFIC.2011.5940705","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940705","url":null,"abstract":"A compact, triple output travelling wave oscillator with combined analog and digital control is presented. The oscillator is based on an eight phase rotary travelling wave oscillator employing shielded digitally controlled transmission lines. The oscillator drives an output buffer, a push-push buffer and a quad-push to generate X, K and Q band outputs simultaneously. Fabricated in standard 0.18µm CMOS it occupies 0.48 mm2 and consumes a DC power of 64mW, including pads and buffers. The circuit exhibits 5.5% tuning range in each band with potential 1MHz digital step resolution. With a phase noise of −108 dBc/Hz at 1MHz offset and −1dBm of output power measured at the fundamental frequency, the circuit is a promising candidate for mm-wave software defined radios and digitals PLLs.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940622
Sang-Min Yoo, J. Walling, E. Woo, D. Allstot
A digitally-controlled switched-capacitor RF power amplifier (SCPA) is implemented with a transformer-based power-combiner in 90nm CMOS. The individual SCPA cores can be controlled to provide high average output power and linearity in an “all-switching” mode or increased dynamic range in a “sequential-switching” mode. The SCPA delivers a peak (average) output power of 27.0 (20.3) dBm with a peak (average) PAE of 26% (15.1%) for a 64 QAM OFDM modulated signal with a measured EVM of 3.8% in the 2.4 GHz band.
{"title":"A power-combined switched-capacitor power amplifier in 90nm CMOS","authors":"Sang-Min Yoo, J. Walling, E. Woo, D. Allstot","doi":"10.1109/RFIC.2011.5940622","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940622","url":null,"abstract":"A digitally-controlled switched-capacitor RF power amplifier (SCPA) is implemented with a transformer-based power-combiner in 90nm CMOS. The individual SCPA cores can be controlled to provide high average output power and linearity in an “all-switching” mode or increased dynamic range in a “sequential-switching” mode. The SCPA delivers a peak (average) output power of 27.0 (20.3) dBm with a peak (average) PAE of 26% (15.1%) for a 64 QAM OFDM modulated signal with a measured EVM of 3.8% in the 2.4 GHz band.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115742338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940652
M. Kaltiokallio, Jussi Ryynnen
This paper focuses on the design of a highly tunable active polyphase filter with IRR better than 40dB. The active polyphase filter is implemented as a part of a simple RF receiver to demonstrate its feasibility for wide variety of wireless systems. The design consists of a high frequency adjustable gm-element that is optimized for active PPF. The filter achieves a tuning range of 1 to 5GHz while consuming supply current of 0.7 to 4.4mA. The silicon area of the filter is 64×85µm.
{"title":"A 1 to 5GHz adjustable active polyphase filter for LO quadrature generation","authors":"M. Kaltiokallio, Jussi Ryynnen","doi":"10.1109/RFIC.2011.5940652","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940652","url":null,"abstract":"This paper focuses on the design of a highly tunable active polyphase filter with IRR better than 40dB. The active polyphase filter is implemented as a part of a simple RF receiver to demonstrate its feasibility for wide variety of wireless systems. The design consists of a high frequency adjustable gm-element that is optimized for active PPF. The filter achieves a tuning range of 1 to 5GHz while consuming supply current of 0.7 to 4.4mA. The silicon area of the filter is 64×85µm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124541972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940627
Jian Liu, Lijie Zhang, Xin Wang, Lin Lin, Zitao Shi, Albert Z. H. Wang, Ru Huang, Gary Zhang, Shi-Jie Wen, R. Wong
We report design and analysis of new nano crossbar based nano phase switching electrostatic discharge (ESD) protection structures. Measurements confirm ESD protection featuring fast response of 100pS, ultra low leakage Ileak∼0.11pA, varying trigger voltage (Vt1) and good ESD protection voltage ratio (ESDV)>230V/µm2. This non-traditional nano-crossbar ESD protection can be a potential solution for RF and mixed-signal ICs.
{"title":"Nano crossbar electrostatic discharge protection design","authors":"Jian Liu, Lijie Zhang, Xin Wang, Lin Lin, Zitao Shi, Albert Z. H. Wang, Ru Huang, Gary Zhang, Shi-Jie Wen, R. Wong","doi":"10.1109/RFIC.2011.5940627","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940627","url":null,"abstract":"We report design and analysis of new nano crossbar based nano phase switching electrostatic discharge (ESD) protection structures. Measurements confirm ESD protection featuring fast response of 100pS, ultra low leakage I<inf>leak</inf>∼0.11pA, varying trigger voltage (V<inf>t1</inf>) and good ESD protection voltage ratio (ESDV)>230V/µm<sup>2</sup>. This non-traditional nano-crossbar ESD protection can be a potential solution for RF and mixed-signal ICs.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940692
N. Mallavarpu, D. Dawn, J. Laskar
As the gate length of CMOS processes has become smaller and the device fT has increased, applications such as CMOS power amplifiers in the millimeter-wave region have become feasible and practical. This paper describes the development of an empirical large-signal model for sub-100 nm CMOS transistors and demonstrates its successful use in the design of a 4-stage 60 GHz CMOS power amplifier with measured performance of 20dB gain, +10.3dBm P1dB, 13.5dBm Psat and 13% PAE. A novel drain-source current formulation is used, accurately modeling both strong-inversion and sub- threshold characteristics of short-channel, 90nm CMOS transistors. Further model enhancement is obtained through optimization for millimeter-wave applications using an optimized parasitic extraction process as well as the incorporation of size scalability and temperature dependency, making this modeling approach highly robust.
{"title":"Temperature-dependent scalable large signal CMOS device model developed for millimeter-wave power amplifier design","authors":"N. Mallavarpu, D. Dawn, J. Laskar","doi":"10.1109/RFIC.2011.5940692","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940692","url":null,"abstract":"As the gate length of CMOS processes has become smaller and the device fT has increased, applications such as CMOS power amplifiers in the millimeter-wave region have become feasible and practical. This paper describes the development of an empirical large-signal model for sub-100 nm CMOS transistors and demonstrates its successful use in the design of a 4-stage 60 GHz CMOS power amplifier with measured performance of 20dB gain, +10.3dBm P1dB, 13.5dBm Psat and 13% PAE. A novel drain-source current formulation is used, accurately modeling both strong-inversion and sub- threshold characteristics of short-channel, 90nm CMOS transistors. Further model enhancement is obtained through optimization for millimeter-wave applications using an optimized parasitic extraction process as well as the incorporation of size scalability and temperature dependency, making this modeling approach highly robust.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"22 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125780085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940665
H. Hsieh, Po-Yi Wu, C. Jou, F. Hsueh, G. Huang
In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.
{"title":"60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS","authors":"H. Hsieh, Po-Yi Wu, C. Jou, F. Hsueh, G. Huang","doi":"10.1109/RFIC.2011.5940665","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940665","url":null,"abstract":"In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125915432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940698
M. Abdelghany, R. Pokharel, H. Kanaya, K. Yoshida
This paper describes the design and implementation of a low-voltage low-power low noise amplifier (LNA) merged with a fully differential double-balanced single-gate mixer for 5GHz wireless systems. The LNA and mixer had been designed to operate in sub-threshold region for low-power dissipation. The proposed design has been fabricated using TSMC 0.18µm 1P6M CMOS process. At 1mW power consumption from 1V supply voltage, the proposed LNA-mixer design achieves a conversion gain of 27dB and a single side band noise figure (SSB-NF) of 19dB. Measured IIP3 is −3dBm with LO input power of −5dBm.
{"title":"Low-voltage low-power combined LNA-single gate mixer for 5GHz wireless systems","authors":"M. Abdelghany, R. Pokharel, H. Kanaya, K. Yoshida","doi":"10.1109/RFIC.2011.5940698","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940698","url":null,"abstract":"This paper describes the design and implementation of a low-voltage low-power low noise amplifier (LNA) merged with a fully differential double-balanced single-gate mixer for 5GHz wireless systems. The LNA and mixer had been designed to operate in sub-threshold region for low-power dissipation. The proposed design has been fabricated using TSMC 0.18µm 1P6M CMOS process. At 1mW power consumption from 1V supply voltage, the proposed LNA-mixer design achieves a conversion gain of 27dB and a single side band noise figure (SSB-NF) of 19dB. Measured IIP3 is −3dBm with LO input power of −5dBm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128664644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940653
Ronghui Zhang, M. Acar, M. van der Heijden, M. Apostolidou, L. D. de Vreede, D. Leenaerts
A 65nm CMOS broadband two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To reduce the peak drain-source voltage and improve reliable operation, sub-optimum class-E operation is applied. The PA is followed by a broadband output matching network implemented as an off-chip two-stage LC ladder. The measurements with a 5.0V supply voltage for the power stage and 2.4V for the driver stage show a drain efficiency > 67% and a power-added efficiency (PAE) > 52% with a Pout > 30dBm within 550MHz–1050MHz. The output power variation is within 1.0dB and efficiency variation is less than 13%. The highest efficiency is observed at 700MHz with peak drain efficiency of 77% and peak PAE of 65% at a Pout of 31dBm and 17dB power gain. By using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off from 30dBm.
{"title":"A 550–1050MHz +30dBm class-E power amplifier in 65nm CMOS","authors":"Ronghui Zhang, M. Acar, M. van der Heijden, M. Apostolidou, L. D. de Vreede, D. Leenaerts","doi":"10.1109/RFIC.2011.5940653","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940653","url":null,"abstract":"A 65nm CMOS broadband two-stage class-E power amplifier (PA) using high voltage extended-drain devices is presented. To reduce the peak drain-source voltage and improve reliable operation, sub-optimum class-E operation is applied. The PA is followed by a broadband output matching network implemented as an off-chip two-stage LC ladder. The measurements with a 5.0V supply voltage for the power stage and 2.4V for the driver stage show a drain efficiency > 67% and a power-added efficiency (PAE) > 52% with a Pout > 30dBm within 550MHz–1050MHz. The output power variation is within 1.0dB and efficiency variation is less than 13%. The highest efficiency is observed at 700MHz with peak drain efficiency of 77% and peak PAE of 65% at a Pout of 31dBm and 17dB power gain. By using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off from 30dBm.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128247155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940646
L. Poulain, N. Waldhoff, D. Gloria, F. Danneville, G. Dambrine
The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS Technology. For this purpose, S parameters were measured up to 67 GHz, a high frequency (HF) noise model was extracted in 6–40 GHz frequency range, and its accuracy verified through a comparison with the noise figure measured in W band with a 50 Ω impedance set at the transistor. The technology offers fT, fMAX respectively of 200 and 300 GHz in line with up-to-date published results for a 45 nm CMOS Technology. At the meantime, a minimum noise figure of 4.5 dB at 94 GHz is demonstrated (verified through W band noise measurements).
{"title":"Small signal and HF noise performance of 45 nm CMOS technology in mmW range","authors":"L. Poulain, N. Waldhoff, D. Gloria, F. Danneville, G. Dambrine","doi":"10.1109/RFIC.2011.5940646","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940646","url":null,"abstract":"The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS Technology. For this purpose, S parameters were measured up to 67 GHz, a high frequency (HF) noise model was extracted in 6–40 GHz frequency range, and its accuracy verified through a comparison with the noise figure measured in W band with a 50 Ω impedance set at the transistor. The technology offers fT, fMAX respectively of 200 and 300 GHz in line with up-to-date published results for a 45 nm CMOS Technology. At the meantime, a minimum noise figure of 4.5 dB at 94 GHz is demonstrated (verified through W band noise measurements).","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"45 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129545001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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