Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940667
R. Ye, T. Horng, Jian-Ming Wu
This work designs and implements a wideband common-gate (CG) low-noise amplifier (LNA) with dual-feedback using 0.18 µm CMOS technology. The design is based on a mechanism of dual-feedback, which is composed of a transformer and a gm-boosting feedback, to overcome the trade-off between noise and input matching in common-gate topology without consuming additional dc power. Simultaneously, the noise figure and power gain are improved. The implemented wideband CG LNA achieves an S11 of below −10 dB, a NF of 1.9 – 2.65 dB, a power gain of 13.5 – 16.5 dB, and an IIP3 of −2 – 3 dBm, with a 3 dB gain bandwidth of 1 – 8 GHz; the chip consumes 10.8 mW.
{"title":"Wideband common-gate low-noise amplifier with dual-feedback for simultaneous input and noise matching","authors":"R. Ye, T. Horng, Jian-Ming Wu","doi":"10.1109/RFIC.2011.5940667","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940667","url":null,"abstract":"This work designs and implements a wideband common-gate (CG) low-noise amplifier (LNA) with dual-feedback using 0.18 µm CMOS technology. The design is based on a mechanism of dual-feedback, which is composed of a transformer and a gm-boosting feedback, to overcome the trade-off between noise and input matching in common-gate topology without consuming additional dc power. Simultaneously, the noise figure and power gain are improved. The implemented wideband CG LNA achieves an S11 of below −10 dB, a NF of 1.9 – 2.65 dB, a power gain of 13.5 – 16.5 dB, and an IIP3 of −2 – 3 dBm, with a 3 dB gain bandwidth of 1 – 8 GHz; the chip consumes 10.8 mW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"592 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940679
Mohammed M. Abdul-Latif, E. Sánchez-Sinencio
A topology for realizing wideband ring oscillators is introduced. Five three-stage ring oscillators operating over a frequency range of 1-2.56GHz are coupled using uni-lateral cyclic coupling. This provides phase shifted outputs which are combined twice in an N-Push or M-Push operation (N=3 and M=5) resulting in an output signal of 3.16-12.8GHz. This coupled structure improves phase noise by 10log10M=7dB producing -103.4 and -101.6 dBc/Hz at 1MHz offset for 3.16GHz and 12.8GHz, respectively. A prototype fabricated in 90nm CMOS consumes 13-200mW across the tuning range.
{"title":"A 3.16 – 12.8GHz low phase noise N-Push/M-push cyclic coupled ring oscillator","authors":"Mohammed M. Abdul-Latif, E. Sánchez-Sinencio","doi":"10.1109/RFIC.2011.5940679","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940679","url":null,"abstract":"A topology for realizing wideband ring oscillators is introduced. Five three-stage ring oscillators operating over a frequency range of 1-2.56GHz are coupled using uni-lateral cyclic coupling. This provides phase shifted outputs which are combined twice in an N-Push or M-Push operation (N=3 and M=5) resulting in an output signal of 3.16-12.8GHz. This coupled structure improves phase noise by 10log10M=7dB producing -103.4 and -101.6 dBc/Hz at 1MHz offset for 3.16GHz and 12.8GHz, respectively. A prototype fabricated in 90nm CMOS consumes 13-200mW across the tuning range.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131681481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940680
Shadi Saberi, J. Paramesh
A wide-tuning CMOS quadrature VCO (QVCO) is presented that uses a transformer-coupled resonator that enables quadrature coupling and facilitates alternative tuning methods including mutual inductance switching, magnetic tuning, and dual resonance mode switching besides the conventional capacitor tuning. The QVCO, fabricated in 130nm CMOS, can generate quadrature signals in the frequency range of 11.56–18.1 GHz and 18.9–22 GHz. The phase noise was measured −107dBc/Hz at 1MHz offset from 13.3GHz. The QVCO consumes 20–29mW and the output buffers consume 21mW from a 1.2V supply.
{"title":"A 11.5–22GHz dual-resonance transformer-coupled quadrature VCO","authors":"Shadi Saberi, J. Paramesh","doi":"10.1109/RFIC.2011.5940680","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940680","url":null,"abstract":"A wide-tuning CMOS quadrature VCO (QVCO) is presented that uses a transformer-coupled resonator that enables quadrature coupling and facilitates alternative tuning methods including mutual inductance switching, magnetic tuning, and dual resonance mode switching besides the conventional capacitor tuning. The QVCO, fabricated in 130nm CMOS, can generate quadrature signals in the frequency range of 11.56–18.1 GHz and 18.9–22 GHz. The phase noise was measured −107dBc/Hz at 1MHz offset from 13.3GHz. The QVCO consumes 20–29mW and the output buffers consume 21mW from a 1.2V supply.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":" 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120831847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940590
M. Ghahramani, M. Ferriss, M. Flynn
A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers −2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm2.
{"title":"A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS","authors":"M. Ghahramani, M. Ferriss, M. Flynn","doi":"10.1109/RFIC.2011.5940590","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940590","url":null,"abstract":"A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers −2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131066714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5946225
ChuanKang Liang, B. Razavi
The distributed interconnect parasitics within large transistors markedly degrade the output power and efficiency at millimeter-wave frequencies. This paper develops a model for such structures and proposes a layout technique to reduce the effect of source terminal parasitics. The technique is applied to a 60-GHz prototype in 65-nm CMOS technology, raising the output power from 5 to 10 dBm and the drain efficiency from 3.7% to 10.7%.
{"title":"A layout technique for millimeter-wave PA transistors","authors":"ChuanKang Liang, B. Razavi","doi":"10.1109/RFIC.2011.5946225","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5946225","url":null,"abstract":"The distributed interconnect parasitics within large transistors markedly degrade the output power and efficiency at millimeter-wave frequencies. This paper develops a model for such structures and proposes a layout technique to reduce the effect of source terminal parasitics. The technique is applied to a 60-GHz prototype in 65-nm CMOS technology, raising the output power from 5 to 10 dBm and the drain efficiency from 3.7% to 10.7%.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133683054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940600
A. Matsuzawa, K. Okada
This paper gives an overview of the Millimeter Wave Project to realize the indoor and the outdoor systems over Gbps by developing CMOS RF and Baseband SoCs. A 60 GHz direct conversion transceiver was developed using 65 nm CMOS and demonstrates 7 Gbps using 16 QAM. A quadrature VCO attained very low phase noise of −94 dBc/Hz @1 MHz. For the outdoor system (1 km), a baseband mixed signal SoC using 90 nm CMOS was developed and demonstrates 600 Mbps with 16 QAM in 3 8GHz (BW: 260 MHz) band.
{"title":"Indoor and outdoor millimeter wave systems and RF/BB SoCs","authors":"A. Matsuzawa, K. Okada","doi":"10.1109/RFIC.2011.5940600","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940600","url":null,"abstract":"This paper gives an overview of the Millimeter Wave Project to realize the indoor and the outdoor systems over Gbps by developing CMOS RF and Baseband SoCs. A 60 GHz direct conversion transceiver was developed using 65 nm CMOS and demonstrates 7 Gbps using 16 QAM. A quadrature VCO attained very low phase noise of −94 dBc/Hz @1 MHz. For the outdoor system (1 km), a baseband mixed signal SoC using 90 nm CMOS was developed and demonstrates 600 Mbps with 16 QAM in 3 8GHz (BW: 260 MHz) band.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116197206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940617
Ping-Ying Wang, Ching-Hsing Wang, Wei-Chi Lee, T. Yu
This paper presents a GSM/GPRS transmitter which performance is enhanced by the proposed all digital self-calibration technique. Also, the non-ideal effects for realizing the technique including current mismatch, static phase error and VCO gain non-linearity in a conventional charge pump PLL can be self-diagnosed by the self-calibration. The measurement results shows 0.5 degree phase error and −68dBc ORFS for GMSK modulation, which prove that the accuracy of the loop gain calibration and VCO gain linearity is within 1%, and two times reduction compared to all digital and analog transmitters. The silicon prototype is implemented in 65nm process and with a 1.2V supply. The area overhead for the full custom design to enable the technique is only 0.005mm2.
{"title":"A digital calibration enhanced GSM/GPRS transmitter","authors":"Ping-Ying Wang, Ching-Hsing Wang, Wei-Chi Lee, T. Yu","doi":"10.1109/RFIC.2011.5940617","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940617","url":null,"abstract":"This paper presents a GSM/GPRS transmitter which performance is enhanced by the proposed all digital self-calibration technique. Also, the non-ideal effects for realizing the technique including current mismatch, static phase error and VCO gain non-linearity in a conventional charge pump PLL can be self-diagnosed by the self-calibration. The measurement results shows 0.5 degree phase error and −68dBc ORFS for GMSK modulation, which prove that the accuracy of the loop gain calibration and VCO gain linearity is within 1%, and two times reduction compared to all digital and analog transmitters. The silicon prototype is implemented in 65nm process and with a 1.2V supply. The area overhead for the full custom design to enable the technique is only 0.005mm2.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125626409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940608
Ming-Wei Li, Hsin-Chih Kuo, Tzuen-Hsi Huang, H. Chuang
A new injector topology is adopted for the design of a 60-GHz CMOS divide-by-5 injection-locked frequency divider (ILFD). The topology is based on a distributed-element harmonic termination by an open-stub structure connected to the floating source end of the differential injection pair. With this topology together with an N-MOS cross-coupled oscillator core, the supply voltage and power consumption of the divider can be greatly reduced. A test circuit is implemented in a 90-nm CMOS process. With the added λ/4 open stub, the simulated frequency locking range of the designed ILFD with the distributed-element harmonic termination scheme has been greatly extended over 70%. The measured power consumption is 3.75 mW at a supply voltage of 0.6 V and the locking range is 4.1 GHz. A good figure of merit (FOM) of 69.4 is achieved.
{"title":"60GHz CMOS divide-by-5 injection-locked frequency divider with an open-stub-loaded floating-source injector","authors":"Ming-Wei Li, Hsin-Chih Kuo, Tzuen-Hsi Huang, H. Chuang","doi":"10.1109/RFIC.2011.5940608","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940608","url":null,"abstract":"A new injector topology is adopted for the design of a 60-GHz CMOS divide-by-5 injection-locked frequency divider (ILFD). The topology is based on a distributed-element harmonic termination by an open-stub structure connected to the floating source end of the differential injection pair. With this topology together with an N-MOS cross-coupled oscillator core, the supply voltage and power consumption of the divider can be greatly reduced. A test circuit is implemented in a 90-nm CMOS process. With the added λ/4 open stub, the simulated frequency locking range of the designed ILFD with the distributed-element harmonic termination scheme has been greatly extended over 70%. The measured power consumption is 3.75 mW at a supply voltage of 0.6 V and the locking range is 4.1 GHz. A good figure of merit (FOM) of 69.4 is achieved.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":" 37","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120829939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940706
M. Elsayed, Mohammed M. Abdul-Latif, E. Sánchez-Sinencio
An architectural solution for designing a low-reference-spur PLL is presented. A spur frequency-booster block is inserted between the phase-frequency-detector and the charge pump to boost the charge pump's input frequency. Hence, the reference-spurs theoretically vanish. The proposed technique adds additional degrees of freedom in the design of PLLs to reduce the spur level without sacrificing neither the loop bandwidth nor the voltage-controlled oscillator's gain. A prototype is fabricated using UMC 90nm digital CMOS technology and achieves −74dBc reference-spur suppression along with (KVCO/fref) ratio of 17 at a (fBW/fref) ratio of 1/20.
{"title":"A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS","authors":"M. Elsayed, Mohammed M. Abdul-Latif, E. Sánchez-Sinencio","doi":"10.1109/RFIC.2011.5940706","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940706","url":null,"abstract":"An architectural solution for designing a low-reference-spur PLL is presented. A spur frequency-booster block is inserted between the phase-frequency-detector and the charge pump to boost the charge pump's input frequency. Hence, the reference-spurs theoretically vanish. The proposed technique adds additional degrees of freedom in the design of PLLs to reduce the spur level without sacrificing neither the loop bandwidth nor the voltage-controlled oscillator's gain. A prototype is fabricated using UMC 90nm digital CMOS technology and achieves −74dBc reference-spur suppression along with (KVCO/fref) ratio of 17 at a (fBW/fref) ratio of 1/20.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124422786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-06-05DOI: 10.1109/RFIC.2011.5940694
Hsien-Ku Chen, Kuan-Ting Lin, Tao Wang, Shey-Shi Lu
In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, −28/−27dBm of P1dB, −16/−16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.
{"title":"A compact-size dual-band (tri-mode) receiver front-end with switched harmonic mixer and technology scaling","authors":"Hsien-Ku Chen, Kuan-Ting Lin, Tao Wang, Shey-Shi Lu","doi":"10.1109/RFIC.2011.5940694","DOIUrl":"https://doi.org/10.1109/RFIC.2011.5940694","url":null,"abstract":"In this paper, a new dual-band receiver frontend for 2.5GHz and 4.9 to 5.9GHz is proposed in 90nm CMOS technology. The proposed receiver front-end embraces a 2.5/5∼6GHz dual-band low noise amplifier (LNA), a switchable harmonic mixer, an octuple-phase generator, and a wideband 10GHz phase locked-loop. By scaling LC VCO with constant performance, the chip size for LO part is reduced readily. The receiver front-end has 27.5/26.5dB of conversion gain, −28/−27dBm of P1dB, −16/−16.5dBm of IIP3, and 10.2/9dBm of IIP2 in 2.5/5∼6GHz bands. The power consumption of the receiver and the PLL are 42mW and 18mW, respectively under 1.2V supply voltage. Such a low power dissipation is due to short routing path of the new proposed frequency planning.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"1046 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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