Pub Date : 2025-02-14DOI: 10.1109/TNANO.2025.3542165
Anant Singhal;Harshit Agarwal
In this article, we present an Artificial Neural Network (ANN)-based compact model that accurately captures the complete current characteristics of gate-all-around transistors, including drain, gate, and substrate currents. Unlike previous models, our approach simplifies the modeling of substrate current by defining a simple conversion function and by utilizing simpler loss functions that account for physical effects such as impact ionization. This accurate representation of substrate current is critical for addressing hot-carrier-induced reliability concerns. The proposed model is extensively validated with calibrated Technology Computer-Aided Design (TCAD) simulations as well as with experimental data from multiple technologies. Additionally, it demonstrates smooth higher-order derivatives in symmetry tests, ensuring its suitability for RF applications.
{"title":"ANN-Driven Modeling of Gate-All-Around Transistors Incorporating Complete Current Profiles","authors":"Anant Singhal;Harshit Agarwal","doi":"10.1109/TNANO.2025.3542165","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3542165","url":null,"abstract":"In this article, we present an Artificial Neural Network (ANN)-based compact model that accurately captures the complete current characteristics of gate-all-around transistors, including drain, gate, and substrate currents. Unlike previous models, our approach simplifies the modeling of substrate current by defining a simple conversion function and by utilizing simpler loss functions that account for physical effects such as impact ionization. This accurate representation of substrate current is critical for addressing hot-carrier-induced reliability concerns. The proposed model is extensively validated with calibrated Technology Computer-Aided Design (TCAD) simulations as well as with experimental data from multiple technologies. Additionally, it demonstrates smooth higher-order derivatives in symmetry tests, ensuring its suitability for RF applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"110-114"},"PeriodicalIF":2.1,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143496549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Junctionless Nanosheet gate-all-around Field Effect Transistor (JL-NSGAAFET) is a promising technology characterized by the absence of any junctions between source-channel-drain. This absence allows to further scale down transistors while limiting short-channel effects. In this article, JL-NSGAAFET is explored as a potential candidate for the next 3 nm technology node through 3D TCAD simulations. First, we propose and simulate, through fabrication process simulations, a fabrication strategy for the JL-NSGAAFET compatible with the current manufacturing technology and based on the inversion mode NSGAAFET fabrication process. The high-k gate dielectric (HfO2) and metal-gate technology (TiN) are also adopted in the fabrication process to enhance the electrostatic gate control over the channel for the n-type and p-type transistors. Then, we perform electrical simulations of the device by also including drift-diffusion model and quantum density gradient correction. We characterize the device in terms of electrical performance and compare with the conventional NSGAAFET. Furthermore, to investigate the impact of the device scaling on the unwanted short channel effects, we simulate and analyze the devices while varying the gate length (LG) from 20 nm to 12 nm. Our reported simulation results prove that JL-NSGAAFET exhibits near-ideal subthreshold slope, low drain-induced barrier lowering (DIBL) and high on-to-off current ratio (ION/IOFF) with superior advantages of greater drive currents and a simpler fabrication process because of the absence of junctions.
{"title":"Simulation Study on the Impact of Miniaturization in 3 nm Node 3D Junctionless Transistors","authors":"Luca Scognamiglio;Fabrizio Mo;Chiara Elfi Spano;Marco Vacca;Gianluca Piccinini","doi":"10.1109/TNANO.2025.3539457","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3539457","url":null,"abstract":"Junctionless Nanosheet gate-all-around Field Effect Transistor (JL-NSGAAFET) is a promising technology characterized by the absence of any junctions between source-channel-drain. This absence allows to further scale down transistors while limiting short-channel effects. In this article, JL-NSGAAFET is explored as a potential candidate for the next 3 nm technology node through 3D TCAD simulations. First, we propose and simulate, through fabrication process simulations, a fabrication strategy for the JL-NSGAAFET compatible with the current manufacturing technology and based on the inversion mode NSGAAFET fabrication process. The high-k gate dielectric (HfO<sub>2</sub>) and metal-gate technology (TiN) are also adopted in the fabrication process to enhance the electrostatic gate control over the channel for the n-type and p-type transistors. Then, we perform electrical simulations of the device by also including drift-diffusion model and quantum density gradient correction. We characterize the device in terms of electrical performance and compare with the conventional NSGAAFET. Furthermore, to investigate the impact of the device scaling on the unwanted short channel effects, we simulate and analyze the devices while varying the gate length (L<sub>G</sub>) from 20 nm to 12 nm. Our reported simulation results prove that JL-NSGAAFET exhibits near-ideal subthreshold slope, low drain-induced barrier lowering (DIBL) and high on-to-off current ratio (I<sub>ON</sub>/I<sub>OFF</sub>) with superior advantages of greater drive currents and a simpler fabrication process because of the absence of junctions.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"102-109"},"PeriodicalIF":2.1,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-03DOI: 10.1109/TNANO.2025.3537416
{"title":"2024 Index IEEE Transactions on Nanotechnology Vol. 23","authors":"","doi":"10.1109/TNANO.2025.3537416","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3537416","url":null,"abstract":"","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"822-847"},"PeriodicalIF":2.1,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10869628","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-21DOI: 10.1109/TNANO.2025.3532313
S. Sharma;J. Madan;R. Chaujar
This research delves into the temperature-dependent performance of a novel polarity-controlled charge plasma-based InAs/AlGaSb tunneling interfaced junctionless TFET (H-JLTFET). The device leverages the benefits of both charge plasma and heterojunction engineering to enhance device performance. Comprehensive simulations were conducted to assess the impact of temperature on device characteristics. Results indicate that while the device exhibits promising ON-state current and high-frequency metrics, with a peak fT of 417 GHz and an fmax of 4390 GHz, the subthreshold region is significantly influenced by temperature. The observed increase in OFF-state current and degradation in subthreshold swing highlight the need for careful thermal management and circuit design. Furthermore, the study reveals a moderate impact of temperature on intrinsic delay and a slight increase in ambipolar current. Overall, this work provides valuable insights into the thermal behavior of H-JLTFETs, paving the way for optimized device design and reliable operation in various applications.
{"title":"Insights Into Temperature Sensitivity Analysis of Polarity Controlled Charge Plasma Based Tunable Arsenide/Antimonide Tunneling Interfaced Junctionless TFET","authors":"S. Sharma;J. Madan;R. Chaujar","doi":"10.1109/TNANO.2025.3532313","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3532313","url":null,"abstract":"This research delves into the temperature-dependent performance of a novel polarity-controlled charge plasma-based InAs/AlGaSb tunneling interfaced junctionless TFET (H-JLTFET). The device leverages the benefits of both charge plasma and heterojunction engineering to enhance device performance. Comprehensive simulations were conducted to assess the impact of temperature on device characteristics. Results indicate that while the device exhibits promising ON-state current and high-frequency metrics, with a peak <italic>f<sub>T</sub></i> of 417 GHz and an <italic>f</i><sub>max</sub> of 4390 GHz, the subthreshold region is significantly influenced by temperature. The observed increase in OFF-state current and degradation in subthreshold swing highlight the need for careful thermal management and circuit design. Furthermore, the study reveals a moderate impact of temperature on intrinsic delay and a slight increase in ambipolar current. Overall, this work provides valuable insights into the thermal behavior of H-JLTFETs, paving the way for optimized device design and reliable operation in various applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"96-101"},"PeriodicalIF":2.1,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143465613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Novel negative capacitance reconfigurable field effect transistor with arch-shaped source (NC-ESRFET) is proposed in this work. The performance is evaluated by combining 3D TCAD simulation with Laudau-Khalatnikov equation. Because of the amplified vertical electric field, the negative capacitance induced by ferroelectric (FE) layer improves the vertical line tunneling around the embedded source, and an enhanced NC effect is found in proposed NC-ESRFET, no matter for N-type or P-type program. Compared to the conventional nanowire negative capacitance RFET (NC-RFET), a larger critical FE layer thickness and lower subthreshold swing (SS) are obtained in NC-ESRFE, and the lowest SS is lower than 43 mV/dec and average SS is 63 mV/dec, which declines by 33% compared with NC-RFET. Besides, the diameter of embedded source DAS has greater influence on NC enhancement than the length LAS. By reasonably choosing the structure parameters, a 54.4% improvement on driven current and 14.3% decline in SS is obtained in the optimized NC-ESRFET. The results here demonstrate the great attentions of NC-ESRFET in future low power application.
{"title":"Novel Negative Capacitance Reconfigurable Transistor With Arch-Shaped Source","authors":"Hongbo Ye;Junfeng Hu;Xinyu Zou;Zihan Sun;Xianglong Li;Yang Shen;Ziyu Liu;Xiaojin Li;Yanling Shi;Zhigang Mao;Yabin Sun","doi":"10.1109/TNANO.2025.3531844","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531844","url":null,"abstract":"Novel negative capacitance reconfigurable field effect transistor with arch-shaped source (NC-ESRFET) is proposed in this work. The performance is evaluated by combining 3D TCAD simulation with Laudau-Khalatnikov equation. Because of the amplified vertical electric field, the negative capacitance induced by ferroelectric (FE) layer improves the vertical line tunneling around the embedded source, and an enhanced NC effect is found in proposed NC-ESRFET, no matter for N-type or P-type program. Compared to the conventional nanowire negative capacitance RFET (NC-RFET), a larger critical FE layer thickness and lower subthreshold swing (<italic>SS</i>) are obtained in NC-ESRFE, and the lowest <italic>SS</i> is lower than 43 mV/dec and average SS is 63 mV/dec, which declines by 33% compared with NC-RFET. Besides, the diameter of embedded source <italic>D<sub>AS</sub></i> has greater influence on NC enhancement than the length <italic>L<sub>AS</sub></i>. By reasonably choosing the structure parameters, a 54.4% improvement on driven current and 14.3% decline in <italic>SS</i> is obtained in the optimized NC-ESRFET. The results here demonstrate the great attentions of NC-ESRFET in future low power application.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"209-215"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TNANO.2025.3531937
Kajal Verma;Rishu Chaujar
This paper focuses on the device to circuit level assessment of Si/SiGe strained vertically stacked ferroelectric based FinFETs (VS-FeFinFETs) for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. The device is designed with the amalgamation of several advanced technologies such as SOI, strained tri-layered silicon channel system along with the integration of ferroelectric material in superior gate controlled FinFET. Gate engineering has also been incorporated to further improve the device's reliability against ITCs, forming hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET) and it is found to possess superior analog, linearity, and harmonic distortion performance. It shows 91.48% reduction in leakage current resulting in 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance by 32.77%, and device efficiency by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15% ) in VIP2 and 6.525% (25.3% ) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortion less wireless communication applications. Further logic circuit application of HD-VS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.674% in voltage gain along with ITCs induced average variation of 3.66% (15.88% ) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit thus led to its development with enhanced functionality, reliability, and performance, poised to shape the landscape of modern electronics.
{"title":"Unveiling the Impact of Interfacial Trap Charges on Strained VS-FeFinFETs for Improved Reliability:Device to Circuit Level Assessment","authors":"Kajal Verma;Rishu Chaujar","doi":"10.1109/TNANO.2025.3531937","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531937","url":null,"abstract":"This paper focuses on the device to circuit level assessment of Si/SiGe strained vertically stacked ferroelectric based FinFETs (VS-FeFinFETs) for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. The device is designed with the amalgamation of several advanced technologies such as SOI, strained tri-layered silicon channel system along with the integration of ferroelectric material in superior gate controlled FinFET. Gate engineering has also been incorporated to further improve the device's reliability against ITCs, forming hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET) and it is found to possess superior analog, linearity, and harmonic distortion performance. It shows 91.48% reduction in leakage current resulting in 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance by 32.77%, and device efficiency by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15% ) in VIP2 and 6.525% (25.3% ) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortion less wireless communication applications. Further logic circuit application of HD-VS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.674% in voltage gain along with ITCs induced average variation of 3.66% (15.88% ) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit thus led to its development with enhanced functionality, reliability, and performance, poised to shape the landscape of modern electronics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"88-95"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transformers are widely used in natural language processing and computer vision, and Bidirectional Encoder Representations from Transformers (BERT) is one of the most popular pre-trained transformer models for many applications. This paper studies the dependability and impact of soft errors on BERT implemented with different floating-point formats using two case studies: sentence emotion classification and question answering. Simulation by error injection is conducted to assess the impact of errors on different parts of the BERT model and different bits of the parameters. The analysis of the results leads to the following findings: 1) in both single and half precision, there is a Critical Bit (CB) on which errors significantly affect the performance of the model; 2) in single precision, errors on the CB may cause overflow in many cases, which leads to a fixed result regardless of the input; 3) in half precision, the errors do not cause overflow but they may still introduce a large accuracy loss. In general, the impact of errors is significantly larger in single-precision than half-precision parameters. Error propagation analysis is also considered to further study the effects of errors on different types of parameters and reveal the mitigation effects of the activation function and the intrinsic redundancy of BERT.
{"title":"On the Dependability of Bidirectional Encoder Representations from Transformers (BERT) to Soft Errors","authors":"Zhen Gao;Ziye Yin;Jingyan Wang;Rui Su;Jie Deng;Qiang Liu;Pedro Reviriego;Shanshan Liu;Fabrizio Lombardi","doi":"10.1109/TNANO.2025.3531721","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531721","url":null,"abstract":"Transformers are widely used in natural language processing and computer vision, and Bidirectional Encoder Representations from Transformers (BERT) is one of the most popular pre-trained transformer models for many applications. This paper studies the dependability and impact of soft errors on BERT implemented with different floating-point formats using two case studies: sentence emotion classification and question answering. Simulation by error injection is conducted to assess the impact of errors on different parts of the BERT model and different bits of the parameters. The analysis of the results leads to the following findings: 1) in both single and half precision, there is a Critical Bit (CB) on which errors significantly affect the performance of the model; 2) in single precision, errors on the CB may cause overflow in many cases, which leads to a fixed result regardless of the input; 3) in half precision, the errors do not cause overflow but they may still introduce a large accuracy loss. In general, the impact of errors is significantly larger in single-precision than half-precision parameters. Error propagation analysis is also considered to further study the effects of errors on different types of parameters and reveal the mitigation effects of the activation function and the intrinsic redundancy of BERT.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"73-87"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-homogeneous orthorhombic phase in doped ferroelectric (FE) HfO$_{2}$ film presents challenges towards the optimization and performance predictability of negative capacitance (NC) field-effect transistor (FET) performance. We set out to understand the consequences of these dielectric (DE) phases in doped FE-HfO$_{2}$ on steep-switching device performance through self-consistent quantum transport simulations. Firstly, we consider a fixed DE phase study to understand how the position, percentage, and number of phase components alter the switching characteristics. Then, to predict device performance variation, we conduct a statistical analysis using a large number of randomly distributed DE phase profiles. We find that DE phases positioned near the center of the potential barrier exert the most significant impact on device performance by lowering the top-of-the-barrier, while those closer to the drain have minimal influence on carrier transport and current. While DE phases in the FE layer degrade the subthreshold swing, they also favorably narrow the hysteretic window, which presents opportunities for optimization in logic devices. Through dimensional scaling and statistical analysis, we demonstrate how optimized performance can be achieved even with large variations in device performance.
{"title":"Implications of Dielectric Phases in Ferroelectric HfO$_{2}$ Films on the Performance of Negative Capacitance FETs","authors":"Mayuri Sritharan;Hyunjae Lee;Michael Spinazze;Youngki Yoon","doi":"10.1109/TNANO.2025.3531552","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531552","url":null,"abstract":"Non-homogeneous orthorhombic phase in doped ferroelectric (FE) HfO<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> film presents challenges towards the optimization and performance predictability of negative capacitance (NC) field-effect transistor (FET) performance. We set out to understand the consequences of these dielectric (DE) phases in doped FE-HfO<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> on steep-switching device performance through self-consistent quantum transport simulations. Firstly, we consider a fixed DE phase study to understand how the position, percentage, and number of phase components alter the switching characteristics. Then, to predict device performance variation, we conduct a statistical analysis using a large number of randomly distributed DE phase profiles. We find that DE phases positioned near the center of the potential barrier exert the most significant impact on device performance by lowering the top-of-the-barrier, while those closer to the drain have minimal influence on carrier transport and current. While DE phases in the FE layer degrade the subthreshold swing, they also favorably narrow the hysteretic window, which presents opportunities for optimization in logic devices. Through dimensional scaling and statistical analysis, we demonstrate how optimized performance can be achieved even with large variations in device performance.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"67-72"},"PeriodicalIF":2.1,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-31DOI: 10.1109/TNANO.2024.3524567
Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park
Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO2 gate dielectrics and the Si/SiO2 interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO2 dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO2 dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.
{"title":"Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C","authors":"Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park","doi":"10.1109/TNANO.2024.3524567","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3524567","url":null,"abstract":"Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO<sub>2</sub> gate dielectrics and the Si/SiO<sub>2</sub> interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO<sub>2</sub> dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO<sub>2</sub> dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"54-58"},"PeriodicalIF":2.1,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.
{"title":"On the Importance of the Metal Catalyst Layer to the Performance of CNT-Based Supercapacitor Electrodes","authors":"Kingshuk Chatterjee;Vinay Kumar;Prabhat Kumar Agnihotri;Sumit Basu;Nandini Gupta","doi":"10.1109/TNANO.2024.3523412","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3523412","url":null,"abstract":"The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"48-53"},"PeriodicalIF":2.1,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142940840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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