Novel negative capacitance reconfigurable field effect transistor with arch-shaped source (NC-ESRFET) is proposed in this work. The performance is evaluated by combining 3D TCAD simulation with Laudau-Khalatnikov equation. Because of the amplified vertical electric field, the negative capacitance induced by ferroelectric (FE) layer improves the vertical line tunneling around the embedded source, and an enhanced NC effect is found in proposed NC-ESRFET, no matter for N-type or P-type program. Compared to the conventional nanowire negative capacitance RFET (NC-RFET), a larger critical FE layer thickness and lower subthreshold swing (SS) are obtained in NC-ESRFE, and the lowest SS is lower than 43 mV/dec and average SS is 63 mV/dec, which declines by 33% compared with NC-RFET. Besides, the diameter of embedded source DAS has greater influence on NC enhancement than the length LAS. By reasonably choosing the structure parameters, a 54.4% improvement on driven current and 14.3% decline in SS is obtained in the optimized NC-ESRFET. The results here demonstrate the great attentions of NC-ESRFET in future low power application.
{"title":"Novel Negative Capacitance Reconfigurable Transistor With Arch-Shaped Source","authors":"Hongbo Ye;Junfeng Hu;Xinyu Zou;Zihan Sun;Xianglong Li;Yang Shen;Ziyu Liu;Xiaojin Li;Yanling Shi;Zhigang Mao;Yabin Sun","doi":"10.1109/TNANO.2025.3531844","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531844","url":null,"abstract":"Novel negative capacitance reconfigurable field effect transistor with arch-shaped source (NC-ESRFET) is proposed in this work. The performance is evaluated by combining 3D TCAD simulation with Laudau-Khalatnikov equation. Because of the amplified vertical electric field, the negative capacitance induced by ferroelectric (FE) layer improves the vertical line tunneling around the embedded source, and an enhanced NC effect is found in proposed NC-ESRFET, no matter for N-type or P-type program. Compared to the conventional nanowire negative capacitance RFET (NC-RFET), a larger critical FE layer thickness and lower subthreshold swing (<italic>SS</i>) are obtained in NC-ESRFE, and the lowest <italic>SS</i> is lower than 43 mV/dec and average SS is 63 mV/dec, which declines by 33% compared with NC-RFET. Besides, the diameter of embedded source <italic>D<sub>AS</sub></i> has greater influence on NC enhancement than the length <italic>L<sub>AS</sub></i>. By reasonably choosing the structure parameters, a 54.4% improvement on driven current and 14.3% decline in <italic>SS</i> is obtained in the optimized NC-ESRFET. The results here demonstrate the great attentions of NC-ESRFET in future low power application.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"209-215"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TNANO.2025.3531937
Kajal Verma;Rishu Chaujar
This paper focuses on the device to circuit level assessment of Si/SiGe strained vertically stacked ferroelectric based FinFETs (VS-FeFinFETs) for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. The device is designed with the amalgamation of several advanced technologies such as SOI, strained tri-layered silicon channel system along with the integration of ferroelectric material in superior gate controlled FinFET. Gate engineering has also been incorporated to further improve the device's reliability against ITCs, forming hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET) and it is found to possess superior analog, linearity, and harmonic distortion performance. It shows 91.48% reduction in leakage current resulting in 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance by 32.77%, and device efficiency by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15% ) in VIP2 and 6.525% (25.3% ) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortion less wireless communication applications. Further logic circuit application of HD-VS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.674% in voltage gain along with ITCs induced average variation of 3.66% (15.88% ) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit thus led to its development with enhanced functionality, reliability, and performance, poised to shape the landscape of modern electronics.
{"title":"Unveiling the Impact of Interfacial Trap Charges on Strained VS-FeFinFETs for Improved Reliability:Device to Circuit Level Assessment","authors":"Kajal Verma;Rishu Chaujar","doi":"10.1109/TNANO.2025.3531937","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531937","url":null,"abstract":"This paper focuses on the device to circuit level assessment of Si/SiGe strained vertically stacked ferroelectric based FinFETs (VS-FeFinFETs) for improved reliability under the influence of interfacial trap charges (ITCs) at the semiconductor/oxide interface. The device is designed with the amalgamation of several advanced technologies such as SOI, strained tri-layered silicon channel system along with the integration of ferroelectric material in superior gate controlled FinFET. Gate engineering has also been incorporated to further improve the device's reliability against ITCs, forming hetero dielectric vertically stacked ferroelectric based FinFET (HD-VS-FeFinFET) and it is found to possess superior analog, linearity, and harmonic distortion performance. It shows 91.48% reduction in leakage current resulting in 13 times increment in switching ratio along with improvement in quality factor by 46.01%, transconductance by 32.77%, and device efficiency by 26.54% with negligible variations due to ITCs as compared to VS-FeFinFET. Various linearity and harmonic parameters also improved and showed negligible average variations like 4.72% (177.15% ) in VIP2 and 6.525% (25.3% ) in 1-dB compression point for HD-VS-FeFinFET (VS-FeFinFET) against different ITCs polarity making it more reliable for low power microwave and distortion less wireless communication applications. Further logic circuit application of HD-VS-FeFinFET based CMOS inverter has been analysed and it shows improvement by 17.9% in transition range, 51.674% in voltage gain along with ITCs induced average variation of 3.66% (15.88% ) in noise margin for HD-VS-FeFinFET(VS-FeFinFET) based circuit thus led to its development with enhanced functionality, reliability, and performance, poised to shape the landscape of modern electronics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"88-95"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transformers are widely used in natural language processing and computer vision, and Bidirectional Encoder Representations from Transformers (BERT) is one of the most popular pre-trained transformer models for many applications. This paper studies the dependability and impact of soft errors on BERT implemented with different floating-point formats using two case studies: sentence emotion classification and question answering. Simulation by error injection is conducted to assess the impact of errors on different parts of the BERT model and different bits of the parameters. The analysis of the results leads to the following findings: 1) in both single and half precision, there is a Critical Bit (CB) on which errors significantly affect the performance of the model; 2) in single precision, errors on the CB may cause overflow in many cases, which leads to a fixed result regardless of the input; 3) in half precision, the errors do not cause overflow but they may still introduce a large accuracy loss. In general, the impact of errors is significantly larger in single-precision than half-precision parameters. Error propagation analysis is also considered to further study the effects of errors on different types of parameters and reveal the mitigation effects of the activation function and the intrinsic redundancy of BERT.
{"title":"On the Dependability of Bidirectional Encoder Representations from Transformers (BERT) to Soft Errors","authors":"Zhen Gao;Ziye Yin;Jingyan Wang;Rui Su;Jie Deng;Qiang Liu;Pedro Reviriego;Shanshan Liu;Fabrizio Lombardi","doi":"10.1109/TNANO.2025.3531721","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531721","url":null,"abstract":"Transformers are widely used in natural language processing and computer vision, and Bidirectional Encoder Representations from Transformers (BERT) is one of the most popular pre-trained transformer models for many applications. This paper studies the dependability and impact of soft errors on BERT implemented with different floating-point formats using two case studies: sentence emotion classification and question answering. Simulation by error injection is conducted to assess the impact of errors on different parts of the BERT model and different bits of the parameters. The analysis of the results leads to the following findings: 1) in both single and half precision, there is a Critical Bit (CB) on which errors significantly affect the performance of the model; 2) in single precision, errors on the CB may cause overflow in many cases, which leads to a fixed result regardless of the input; 3) in half precision, the errors do not cause overflow but they may still introduce a large accuracy loss. In general, the impact of errors is significantly larger in single-precision than half-precision parameters. Error propagation analysis is also considered to further study the effects of errors on different types of parameters and reveal the mitigation effects of the activation function and the intrinsic redundancy of BERT.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"73-87"},"PeriodicalIF":2.1,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-homogeneous orthorhombic phase in doped ferroelectric (FE) HfO$_{2}$ film presents challenges towards the optimization and performance predictability of negative capacitance (NC) field-effect transistor (FET) performance. We set out to understand the consequences of these dielectric (DE) phases in doped FE-HfO$_{2}$ on steep-switching device performance through self-consistent quantum transport simulations. Firstly, we consider a fixed DE phase study to understand how the position, percentage, and number of phase components alter the switching characteristics. Then, to predict device performance variation, we conduct a statistical analysis using a large number of randomly distributed DE phase profiles. We find that DE phases positioned near the center of the potential barrier exert the most significant impact on device performance by lowering the top-of-the-barrier, while those closer to the drain have minimal influence on carrier transport and current. While DE phases in the FE layer degrade the subthreshold swing, they also favorably narrow the hysteretic window, which presents opportunities for optimization in logic devices. Through dimensional scaling and statistical analysis, we demonstrate how optimized performance can be achieved even with large variations in device performance.
{"title":"Implications of Dielectric Phases in Ferroelectric HfO$_{2}$ Films on the Performance of Negative Capacitance FETs","authors":"Mayuri Sritharan;Hyunjae Lee;Michael Spinazze;Youngki Yoon","doi":"10.1109/TNANO.2025.3531552","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3531552","url":null,"abstract":"Non-homogeneous orthorhombic phase in doped ferroelectric (FE) HfO<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> film presents challenges towards the optimization and performance predictability of negative capacitance (NC) field-effect transistor (FET) performance. We set out to understand the consequences of these dielectric (DE) phases in doped FE-HfO<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> on steep-switching device performance through self-consistent quantum transport simulations. Firstly, we consider a fixed DE phase study to understand how the position, percentage, and number of phase components alter the switching characteristics. Then, to predict device performance variation, we conduct a statistical analysis using a large number of randomly distributed DE phase profiles. We find that DE phases positioned near the center of the potential barrier exert the most significant impact on device performance by lowering the top-of-the-barrier, while those closer to the drain have minimal influence on carrier transport and current. While DE phases in the FE layer degrade the subthreshold swing, they also favorably narrow the hysteretic window, which presents opportunities for optimization in logic devices. Through dimensional scaling and statistical analysis, we demonstrate how optimized performance can be achieved even with large variations in device performance.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"67-72"},"PeriodicalIF":2.1,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-31DOI: 10.1109/TNANO.2024.3524567
Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park
Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO2 gate dielectrics and the Si/SiO2 interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO2 dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO2 dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.
{"title":"Improvement of Surface Roughness in SiO2 Thin Films via Deuterium Annealing at 300 °C","authors":"Ju-Won Yeon;Hyo-Jun Park;Eui-Cheol Yun;Moon-Kwon Lee;Tae-Hyun Kil;Yong-Sik Kim;Jun-Young Park","doi":"10.1109/TNANO.2024.3524567","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3524567","url":null,"abstract":"Recently, deuterium annealing at a reduced temperature range of 300 °C has been proposed to enhance SiO<sub>2</sub> gate dielectrics and the Si/SiO<sub>2</sub> interface, thereby improving device reliability. As a further investigation into deuterium annealing, for the first time this study compared deuterium absorption characteristics with various SiO<sub>2</sub> dielectrics formed by wet oxidation, dry oxidation, low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Deuterium annealing can also be used to reduce the roughness and improve the uniformity of SiO<sub>2</sub> dielectric films. Surface roughness of various samples was measured and quantitatively compared using atomic force microscopy (AFM) after deuterium annealing.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"54-58"},"PeriodicalIF":2.1,"publicationDate":"2024-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.
{"title":"On the Importance of the Metal Catalyst Layer to the Performance of CNT-Based Supercapacitor Electrodes","authors":"Kingshuk Chatterjee;Vinay Kumar;Prabhat Kumar Agnihotri;Sumit Basu;Nandini Gupta","doi":"10.1109/TNANO.2024.3523412","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3523412","url":null,"abstract":"The power and energy densities of a Supercapacitor (SC) is largely dictated by the accessibility of the nano-porous area of the electrode to the electrolyte ions. Carbon nanotubes (CNT) have high electrical conductivity, and more importantly, may be grown into architectures with high surface area. However, this is not easy to achieve in practice. CNT electrodes are fabricated by chemical vapor deposition (CVD), after a metal catalyst layer is coated on a current collector. In this work, the control of the metal catalyst layer, by varying the dip-coating time and CVD process parameters, is shown to be crucial to pore morphology and consequent SC performance. The dip-coating time is adjusted to obtain thin and uniform coating. Further, optimum reduction of the nickel layer with hydrogen is required to produce thin CNTs with adequate inter-tube separation that facilitate ion accessibility within the pores. The height of the CNT forest is also optimized to prevent decrease in specific capacitance due to reduced accessibility. Proper optimization of the process parameters results in a pore morphology conductive to ion diffusion, and simultaneous improvement in energy and power density.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"48-53"},"PeriodicalIF":2.1,"publicationDate":"2024-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142940840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-25DOI: 10.1109/TNANO.2024.3522371
Tsung-Ying Yang;Mei-Yan Kuo;Jui-Sheng Wu;Yan-Kui Liang;Rahul Rai;Shivendra K. Rathaur;Edward Yi Chang
This study tested fluorine doping on various regions of the ferroelectric charge trap gate stack (FEG stack). Fluorine doping effectively reduces oxygen vacancies in the dielectric layer, thus reducing leakage current and stabilizing charge in the dielectric layer. Moreover, fluorine doping can passivate the dangling bonds at the interface and increase the ability of trapping carriers in the trap layer. The FEG stack comprises a tunnel oxide layer (TL), a charge trap layer (CTL), and a ferroelectric layer (FE). Four types of devices were fabricated: undoped, doping in TL, doping in CTL, and doping in both TL and CTL, to investigate the impact of fluorine doping on the FEG gate stack. Devices doping in TL and CTL demonstrated superior performance, achieving the highest V th of 5.4 V with a retention time of 70.42% after 10, 000 seconds. The off-state and gate leakage tests revealed impressive breakdown voltages of 735 V and 24.55 V, respectively. Furthermore, the device exhibited a high operation voltage of 14.3 V for a 10-year lifetime prediction, enabling a wide operating range.
{"title":"Improvement of the Enhancement-Mode GaN MIS-HEMTs by Fluorine Doping in the Dielectric Gate Stack","authors":"Tsung-Ying Yang;Mei-Yan Kuo;Jui-Sheng Wu;Yan-Kui Liang;Rahul Rai;Shivendra K. Rathaur;Edward Yi Chang","doi":"10.1109/TNANO.2024.3522371","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3522371","url":null,"abstract":"This study tested fluorine doping on various regions of the ferroelectric charge trap gate stack (FEG stack). Fluorine doping effectively reduces oxygen vacancies in the dielectric layer, thus reducing leakage current and stabilizing charge in the dielectric layer. Moreover, fluorine doping can passivate the dangling bonds at the interface and increase the ability of trapping carriers in the trap layer. The FEG stack comprises a tunnel oxide layer (TL), a charge trap layer (CTL), and a ferroelectric layer (FE). Four types of devices were fabricated: undoped, doping in TL, doping in CTL, and doping in both TL and CTL, to investigate the impact of fluorine doping on the FEG gate stack. Devices doping in TL and CTL demonstrated superior performance, achieving the highest V\u0000<sub>th</sub>\u0000 of 5.4 V with a retention time of 70.42% after 10, 000 seconds. The off-state and gate leakage tests revealed impressive breakdown voltages of 735 V and 24.55 V, respectively. Furthermore, the device exhibited a high operation voltage of 14.3 V for a 10-year lifetime prediction, enabling a wide operating range.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"42-47"},"PeriodicalIF":2.1,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-25DOI: 10.1109/TNANO.2024.3522368
Sanjana Devi VS;Balraj B;Amuthameena S;Joby Titus T
This study investigates the enhancement of hydrogen (H 2 ) gas sensing in nitrogen-doped Zinc Oxide (ZnO) nanomaterials through the decoration of gold (Au) nanoparticles. ZnO nanoparticles were synthesized via a wet chemical method, doped with nitrogen at 0.5%, 1.0%, and 1.5% concentrations, and decorated with Au nanoparticles. Characterization using X-ray diffraction (XRD) revealed that the ZnO structure remained intact, with the addition of a peak corresponding to Au at 38.19°. Transmission electron microscopy (TEM) confirmed the uniform distribution of spherical Au nanoparticles on the ZnO surfaces. UV-Vis spectroscopy showed an enhanced absorption peak at 532 nm due to surface plasmon resonance. Photoluminescence (PL) spectra indicated reduced emission intensity, suggesting effective charge transfer between ZnO and Au. Gas sensing tests revealed that Au-decorated 1.0 wt. % N exhibited a maximum H 2 gas response of 89% at 200 °C, significantly higher than the 46% response of non-decorated 1.0 wt. % N. Additionally, the Au-decorated N sensors demonstrated a rapid response time of 10 sec and a recovery time of 15 sec. These results highlight the potential of Au-decorated N-doped nanomaterials as highly efficient H 2 gas sensors, combining enhanced sensitivity with fast response kinetics.
{"title":"Enhanced Hydrogen Gas Sensing Performance of Gold Nanoparticle Decorated Nitrogen-Doped ZnO Nanomaterials for Improved Sensitivity and Rapid Response","authors":"Sanjana Devi VS;Balraj B;Amuthameena S;Joby Titus T","doi":"10.1109/TNANO.2024.3522368","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3522368","url":null,"abstract":"This study investigates the enhancement of hydrogen (H\u0000<sub>2</sub>\u0000) gas sensing in nitrogen-doped Zinc Oxide (ZnO) nanomaterials through the decoration of gold (Au) nanoparticles. ZnO nanoparticles were synthesized via a wet chemical method, doped with nitrogen at 0.5%, 1.0%, and 1.5% concentrations, and decorated with Au nanoparticles. Characterization using X-ray diffraction (XRD) revealed that the ZnO structure remained intact, with the addition of a peak corresponding to Au at 38.19°. Transmission electron microscopy (TEM) confirmed the uniform distribution of spherical Au nanoparticles on the ZnO surfaces. UV-Vis spectroscopy showed an enhanced absorption peak at 532 nm due to surface plasmon resonance. Photoluminescence (PL) spectra indicated reduced emission intensity, suggesting effective charge transfer between ZnO and Au. Gas sensing tests revealed that Au-decorated 1.0 wt. % N exhibited a maximum H\u0000<sub>2</sub>\u0000 gas response of 89% at 200 °C, significantly higher than the 46% response of non-decorated 1.0 wt. % N. Additionally, the Au-decorated N sensors demonstrated a rapid response time of 10 sec and a recovery time of 15 sec. These results highlight the potential of Au-decorated N-doped nanomaterials as highly efficient H\u0000<sub>2</sub>\u0000 gas sensors, combining enhanced sensitivity with fast response kinetics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"27-33"},"PeriodicalIF":2.1,"publicationDate":"2024-12-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142938283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-13DOI: 10.1109/TNANO.2024.3517161
Valeriy A. Slipko;Yuriy V. Pershin
This theoretical study investigates strategies for minimizing Joule losses in resistive random access memory (ReRAM) cells, which are also referred to as memristive devices. Typically, the structure of ReRAM cells involves a nanoscale layer of resistance-switching material sandwiched between two metal electrodes. The basic question that we ask is what is the optimal driving protocol to switch a memristive device from one state to another. In the case of ideal memristors, in the most basic scenario, the optimal protocol is determined by solving a variational problem without constraints with the help of the Euler-Lagrange equation. In the case of memristive systems, for the same situation, the optimal protocol is found using the method of Lagrange multipliers. We demonstrate the advantages of our approaches through specific examples and compare our results with those of switching with constant voltage or current. Our findings suggest that voltage or current control can be used to reduce Joule losses in emerging memory devices.
{"title":"Reduction of Joule Losses in Memristive Switching Using Optimal Control","authors":"Valeriy A. Slipko;Yuriy V. Pershin","doi":"10.1109/TNANO.2024.3517161","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3517161","url":null,"abstract":"This theoretical study investigates strategies for minimizing Joule losses in resistive random access memory (ReRAM) cells, which are also referred to as memristive devices. Typically, the structure of ReRAM cells involves a nanoscale layer of resistance-switching material sandwiched between two metal electrodes. The basic question that we ask is what is the optimal driving protocol to switch a memristive device from one state to another. In the case of ideal memristors, in the most basic scenario, the optimal protocol is determined by solving a variational problem without constraints with the help of the Euler-Lagrange equation. In the case of memristive systems, for the same situation, the optimal protocol is found using the method of Lagrange multipliers. We demonstrate the advantages of our approaches through specific examples and compare our results with those of switching with constant voltage or current. Our findings suggest that voltage or current control can be used to reduce Joule losses in emerging memory devices.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"8-16"},"PeriodicalIF":2.1,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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