Pub Date : 2024-04-02DOI: 10.1109/TSM.2024.3378160
Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee
Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and $1.289~mu text{m}$ , respectively, representing an improvement of approximately 15.81%.
{"title":"Improving the Reliability of Through Silicon Vias: Reducing Copper Protrusion by Artificial Defect Manipulation and Annealing","authors":"Won-Jun Choi;Myong Jae Yoo;Joonho Bae;Ji-Hun Seo;Churl Seung Lee","doi":"10.1109/TSM.2024.3378160","DOIUrl":"10.1109/TSM.2024.3378160","url":null,"abstract":"Through silicon vias (TSVs) are a critical technology for manufacturing three-dimensional stacked structure of semiconductor packages by forming holes that penetrate silicon wafers and vertically interconnect multiple wafers. Typically, TSVs are created by drilling via holes in wafers and filling their interiors using copper electroplating processes. Subsequently, the wafers are exposed to high-temperature environments during the back-end-of-line (BEOL) process. However, improper copper electroplating conditions can form defects, such as voids and seams, within TSVs, while the high temperature of the BEOL process induces copper protrusion phenomena. These defects and copper protrusion degrade the reliability of TSV. In this brief, copper protrusion behavior, which is a direct cause of reliability degradation in TSVs, was mitigated by experimentally exploring the seam defects that can occur during the TSV filling process. Subsequent annealing processes were applied to remove the seam defects based on the copper-grain growth. The copper protrusion height was analyzed based on the size of the seam defects and annealing temperature. From the proposed process in this brief, the copper protrusion heights of TSVs without and with seam defects were confirmed to be 1.531 and \u0000<inline-formula> <tex-math>$1.289~mu text{m}$ </tex-math></inline-formula>\u0000, respectively, representing an improvement of approximately 15.81%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"166-173"},"PeriodicalIF":2.7,"publicationDate":"2024-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140565020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-29DOI: 10.1109/TSM.2024.3383287
Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht
For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (< $1 ~mu text{m}$ ), doped epitaxial SCD layers with very low (<1> $4.5 mm^{2}$ area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.
{"title":"Chemical Mechanical Polishing of Single-Crystalline Diamond Epitaxial Layers for Electronics Applications","authors":"Aaron Hardy;Matthias Muehle;Cristian Herrera-Rodriguez;Michael Becker;Edward Drown;Nina Baule;Mark Tompkins;Timothy Grotjohn;John D. Albrecht","doi":"10.1109/TSM.2024.3383287","DOIUrl":"10.1109/TSM.2024.3383287","url":null,"abstract":"For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (<\u0000<inline-formula> <tex-math>$1 ~mu text{m}$ </tex-math></inline-formula>\u0000), doped epitaxial SCD layers with very low (<1> <tex-math>$4.5 mm^{2}$ </tex-math></inline-formula>\u0000 area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"190-198"},"PeriodicalIF":2.7,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140564910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized $3times 3$ window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained.
众所周知，确定 "好骰子在坏邻居中"（GDBNs）一直被认为是通过识别和剔除可疑骰子（即使这些骰子在测试中是好的）来降低百万分之缺陷率（DPPM）值的有效技术。与在一个 3/3 乘 3$ 的小窗口中检查八个近邻或利用简单的线性回归不同，可以使用一个大窗口来识别广视角邻域，并准确推断任何给定骰子的可疑程度。本文提出了基于人工神经网络（ANN）的方法来解决 GDBN 识别问题。此外，本文还进一步提出了两种增强技术，通过考虑随时间变化的晶圆图案和相邻两个晶圆之间的晶圆与晶圆关系的变化，来提高基于人工神经网络的原始方法的推断精度。应用这两项增强技术后，基于 ANN 的新方法可以提高商业利润。在两个数据集上进行的各种实验清楚地揭示了所提出的基于 ANN 的方法优于其他现有方法。除了降低 DPPM 值，基于 ANN 的新方法还能使退货授权（RMA）成本降低 1.5 倍至 2 倍。另一方面，实验结果表明，其他低收益产品也能获得类似的结果。通过使用基于 ANN 的新方法，可以捕捉到坏骰子交叉晶圆的关系，并同时保持高精度的推理结果。
{"title":"Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks","authors":"Chia-Heng Yen;Ting-Rui Wang;Ching-Min Liu;Cheng-Hao Yang;Chun-Teng Chen;Ying-Yen Chen;Jih-Nung Lee;Shu-Yi Kao;Kai-Chiang Wu;Mango Chia-Tso Chao","doi":"10.1109/TSM.2024.3406395","DOIUrl":"10.1109/TSM.2024.3406395","url":null,"abstract":"It is known that the determination of the good-dice-in-bad-neighborhoods (GDBNs) has been regarded as an effective technique to reduce the value of the defect parts per million (DPPM) by identifying and rejecting the suspicious dice even though they are good in testing. Instead of examining eight immediate neighbors in a small-sized \u0000<inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula>\u0000 window or exploiting simple linear regression, a large-sized window can be used to recognize the broad-sighted neighborhoods and accurately infer the suspiciousness level for any given die. In this paper, the artificial neural networks (ANN)-based method can be proposed to solve the GDBN identification. Furthermore, two enhanced techniques can be further presented to improve the inference accuracy of the original ANN-based method by considering the variation of the time-dependent wafer patterns and the wafer-to-wafer relationship between two adjacent wafers. After applying the two enhanced techniques, the business profits can be improved in the new ANN-based method. Various experiments on two datasets clearly reveal the superiority of the proposed ANN-based method over the other existing methods. In addition to the reduction of the DPPM value, the new ANN-based method can achieve the 1.5X–2X better reduction in the cost of the return merchandise authorization (RMA). On the other hand, the experimental results show that the similar result can also be obtained in the other lower-yield products. By using the new ANN-based method, the relationships on bad dice cross wafers can be captured and the highly-accurate inference results can be simultaneously maintained.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"280-292"},"PeriodicalIF":2.3,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141188042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1109/TSM.2024.3382511
S. Abdi;V. Nodjiadjim;R. Hersent;M. Riet;C. Mismer;T. de Vries;K. A. Williams;Y. Jiao
In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (< $15 ~mu text{m}$ ).
{"title":"Research Toward Wafer-Scale 3D Integration of InP Membrane Photonics With InP Electronics","authors":"S. Abdi;V. Nodjiadjim;R. Hersent;M. Riet;C. Mismer;T. de Vries;K. A. Williams;Y. Jiao","doi":"10.1109/TSM.2024.3382511","DOIUrl":"10.1109/TSM.2024.3382511","url":null,"abstract":"In this study, we focus on the development of key processes towards wafer-scale 3-dimentional/vertical (3D) integration of Indium-Phosphide (InP) photonic membranes on InP electronics via adhesive bonding. First, we identified the most critical steps and optimized them to achieve high thermal and mechanical compatibility of components for the co-integration process. Next, we developed a strategy for InP-to-InP wafer bonding with high topology tolerance, and introduced hard benzocyclobutene (BCB) anchors to preserve the alignment and BCB thickness uniformity after bonding. The resulting bond layer is homogeneous in terms of physical and mechanical properties. Finally, we developed a novel method to selectively remove the InP substrate from the photonics side via wet etching while protecting the electronics carrier wafer with hermetic multi-layer coatings. The investigation of these key steps is essential for scalable 3D integration of photonics and electronics at ultra short distances (<\u0000<inline-formula> <tex-math>$15 ~mu text{m}$ </tex-math></inline-formula>\u0000).","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"229-237"},"PeriodicalIF":2.3,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140313410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-22DOI: 10.1109/TSM.2024.3379949
Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett
This study focuses on energy saving for a Taiwan high-tech DRAM factory as the primary research subject. Collecting operational parameters related to various facility systems and process equipment is initially performed by using the developed energy conversion factors (ECF) calculator. Moreover, innovative fab energy simulation (FES) software has been designed by Taipei Tech. This software is designed for high-tech fab energy consumption analysis. The annual energy consumption data for fabs can be calculated. This data is then converted into carbon dioxide emissions using the power carbon emission coefficient provided by the Bureau of Energy, Ministry of Economic Affairs Taiwan. In this study, five different energy-saving strategies were proposed. The energy consumption and carbon emissions distribution were evaluated to assess the benefits of those different techniques. The findings show that among the existing operational facilities, the use of an exhaust air conditioning unit with reduced enthalpy value setting, with lowered supply air temperature, demonstrates the highest energy-saving. This technique has the potential to annually reduce carbon emissions by approximately 623,158 kg CO2 and operational costs by NT ${$}$ 6,005,764 (189,602 U.S. ${$}$ ). This can reduce the overall manufacturing cost and is also beneficial for the environment.
本研究以台湾一家高科技 DRAM 工厂的节能为主要研究对象。首先使用已开发的能源转换系数（ECF）计算器收集与各种设施系统和工艺设备相关的运行参数。此外，台北科技大学还设计了创新的工厂能源模拟（FES）软件。该软件专为高科技工厂能耗分析而设计。它可以计算出工厂的年度能耗数据。然后，利用台湾经济部能源局提供的电力碳排放系数，将这些数据转换为二氧化碳排放量。本研究提出了五种不同的节能策略。对能源消耗和碳排放分布进行了评估，以评估这些不同技术的效益。研究结果表明，在现有的运行设施中，使用降低焓值设置的排风空调机，同时降低送风温度，节能效果最好。这项技术每年可减少约 623,158 千克二氧化碳排放，减少运营成本 6,005,764 新台币（189,602 美元）。这可以降低总体制造成本，同时也有利于环境。
{"title":"Energy Consumption and Carbon Emission Reduction in HVAC System of a Dynamic Random Access Memory (DRAM) Semiconductor Fabrication Plant (fab)","authors":"Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Chia-Jen Hsu;Chia-Hung Chou;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett","doi":"10.1109/TSM.2024.3379949","DOIUrl":"10.1109/TSM.2024.3379949","url":null,"abstract":"This study focuses on energy saving for a Taiwan high-tech DRAM factory as the primary research subject. Collecting operational parameters related to various facility systems and process equipment is initially performed by using the developed energy conversion factors (ECF) calculator. Moreover, innovative fab energy simulation (FES) software has been designed by Taipei Tech. This software is designed for high-tech fab energy consumption analysis. The annual energy consumption data for fabs can be calculated. This data is then converted into carbon dioxide emissions using the power carbon emission coefficient provided by the Bureau of Energy, Ministry of Economic Affairs Taiwan. In this study, five different energy-saving strategies were proposed. The energy consumption and carbon emissions distribution were evaluated to assess the benefits of those different techniques. The findings show that among the existing operational facilities, the use of an exhaust air conditioning unit with reduced enthalpy value setting, with lowered supply air temperature, demonstrates the highest energy-saving. This technique has the potential to annually reduce carbon emissions by approximately 623,158 kg CO2 and operational costs by NT\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000 6,005,764 (189,602 U.S.\u0000<inline-formula> <tex-math>${$}$ </tex-math></inline-formula>\u0000). This can reduce the overall manufacturing cost and is also beneficial for the environment.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"174-184"},"PeriodicalIF":2.7,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140203546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-21DOI: 10.1109/TSM.2024.3403230
Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo
In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures.
{"title":"Optimization of Void Defects at TiN/Si:HfO2 Interface for 3-D Ferroelectric Memory","authors":"Dongxue Zhao;Zhiliang Xia;Yi Yang;Meiying Liu;Yuancheng Yang;Zongliang Huo","doi":"10.1109/TSM.2024.3403230","DOIUrl":"10.1109/TSM.2024.3403230","url":null,"abstract":"In the 3D ferroelectric memory fabrication process, the outer Titanium nitride metal electrode and silicon doped hafnium-based ferroelectric layer will produce void defects at the interfaces, causing increased leakage and compromising device performance. These void defects are caused by the volume contraction during the phase transition process, which leads to tension at the outer interface of the 3D ferroelectric capacitor structure. Due to the unavoidable structural stress, it is necessary to optimize the interface bonding energy. First principles simulation revealed insufficient binding energy between titanium nitride and silicon doped hafnium oxide ferroelectric materials, while introducing an amorphous alumina interface layer can effectively improve the binding ability. Experimental verification has confirmed that using an amorphous alumina interface layer as an adhesive layer can successfully solve the interface void defects, thereby improving the ferroelectric properties in three-dimensional structures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"542-545"},"PeriodicalIF":2.3,"publicationDate":"2024-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/TSM.2024.3402214
Se Yun Jo;Minsuk Choi;Sang Jeen Hong
Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms.
{"title":"Plasma Pretreatment System for the Reduction of By-Product Particles in Semiconductor Manufacturing","authors":"Se Yun Jo;Minsuk Choi;Sang Jeen Hong","doi":"10.1109/TSM.2024.3402214","DOIUrl":"10.1109/TSM.2024.3402214","url":null,"abstract":"Titanium tetrachloride (TiCl4) is a well-known source of titanium (Ti) for the formation of titanium nitride (TiN) barrier material in the semiconductor interconnection process; however, the reaction of by-products with airborne molecules can cause unexpected pump trips and equipment breakdown from the by-product powder build-up. Plasma scrubbers are used to decompose by-products, but hydrogen chloride (HCl) and nitrogen oxides are produced during and after the process. The process mechanisms change when the temperature and applied power of the heat source change. In this paper, we study the influence of the reactor temperature and applied power to the heat source on the decomposition capacity of TiCl4 in a plasma pretreatment system (PPS). We examine the effect of the temperature and heat source power to understand the reaction mechanisms for the composition and decomposition of gaseous species with chemical reactions through simultaneous methods. We analyzed the system with computational fluid dynamics (CFD) and chemical kinetic simulation to investigate the changes of the system mechanism. Subsequently, we achieved results for the correlation between the temperature of the reactor, power applied to the heat source, composition and decomposition of species, and chemical reaction mechanisms.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"381-393"},"PeriodicalIF":2.3,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141149660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3394310
{"title":"Call for Nominations: 2024 EDS Early Career Award","authors":"","doi":"10.1109/TSM.2024.3394310","DOIUrl":"https://doi.org/10.1109/TSM.2024.3394310","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"222-222"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3378554
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2024.3378554","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378554","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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