The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.
{"title":"Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN","authors":"Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu","doi":"10.1109/TSM.2024.3418520","DOIUrl":"10.1109/TSM.2024.3418520","url":null,"abstract":"The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"316-328"},"PeriodicalIF":2.3,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-25DOI: 10.1109/TSM.2024.3418827
Qian Yue;Chen Lan
Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.
{"title":"DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2024.3418827","DOIUrl":"10.1109/TSM.2024.3418827","url":null,"abstract":"Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"329-339"},"PeriodicalIF":2.3,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.
本文基于对光学发射光谱（OES）信号的所有时间和波长样本的分析，提出了等离子体蚀刻过程中虚拟计量（VM）的新方法。新方法将每个 OES 信号扁平化为单一向量，然后对训练数据集中扁平化 OES 信号向量形成的矩阵进行奇异值分解（SVD）。扁平化和标准化 OES 记录的低秩 SVD 投影可作为基于岭回归、人工神经网络和随机森林的 VM 模型的输入。随后，对从一家大型 300 毫米晶圆制造厂收集的数据集进行了虚拟机研究，结果表明，使用新提出的基于 SVD 的 OES 特征始终优于基准虚拟机模型特征。根据可分析的岭回归虚拟机模型形式对特征重要性进行的其他分析表明，OES 信号部分的独特时频模式对预测相关临界维度具有很高的参考价值，这清楚地证明了将整个 OES 信号用于虚拟机的必要性。
{"title":"Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum","authors":"Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic","doi":"10.1109/TSM.2024.3416844","DOIUrl":"10.1109/TSM.2024.3416844","url":null,"abstract":"This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"363-372"},"PeriodicalIF":2.3,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/TSM.2024.3416830
Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin
Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.
{"title":"Sustainable Semiconductor Manufacturing: The Role of Lithography","authors":"Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin","doi":"10.1109/TSM.2024.3416830","DOIUrl":"10.1109/TSM.2024.3416830","url":null,"abstract":"Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"440-444"},"PeriodicalIF":2.3,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/TSM.2024.3416055
Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani
Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.
检测晶圆图异常对于防止半导体制造中的良率损失至关重要，但复杂的模式和资源密集型标记数据前提条件阻碍了精确的深度学习分割。本文提出了一种创新的无监督方法，用于检测晶圆图中的像素级异常。它利用高效的双重关注模块和知识提炼网络来学习无异常的缺陷分布。除了在教师网络的特征金字塔层次结构上加入高效的双重注意模块外，知识转移是通过将预先训练好的教师网络中的信息提炼到具有类似结构的学生网络中来实现的，这种结构通过捕捉位置和通道维度中的上下文关联，增强了金字塔层次结构中的特征表示和分割，从而有选择性地强调相关特征，摒弃无关特征。此外，它还能使学生网络获得更好的分层特征知识，从而准确识别不同尺度的异常情况。特征金字塔中的不相似性可作为一种判别功能，预测异常的可能性，从而实现高精度的像素级异常检测。因此，我们提出的方法在 WM-811K 和 MixedWM38 数据集上表现出色，AUROC、AUPR、AUPRO 和 F1 分数分别为（99.65%、99.35%）、（97.31%、92.13%）、（90.76%、84.66%），推理速度为 3.204 FPS，显示了其高精度和高效率。
{"title":"Efficient Dual-Attention-Based Knowledge Distillation Network for Unsupervised Wafer Map Anomaly Detection","authors":"Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani","doi":"10.1109/TSM.2024.3416055","DOIUrl":"10.1109/TSM.2024.3416055","url":null,"abstract":"Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"293-303"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.
{"title":"Elimination of Si-C Defect on Wafer Surface in High-Temperature SPM Process Through Nitrogen Purge in 300-mm Single-Wafer Chamber","authors":"Rajan Kumar Singh;Alfie Lin;Haley Lin;Max Chen;Yvonne Pan;Nancy Cho;Willy Chen;Jamiet Tung;Walt Hu;Wilson Huang","doi":"10.1109/TSM.2024.3416079","DOIUrl":"10.1109/TSM.2024.3416079","url":null,"abstract":"During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"355-362"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-13DOI: 10.1109/TSM.2024.3414121
Adam Chalupa;Joel Warner;Jarett Martin
Industrial semiconductor electrodeposition plating cells require recirculation of process chemicals with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow translate to a reduction of in-line defects and increased wafer yield.
{"title":"Computational Study of Chemical Uniformity Impacts on Electrodeposition","authors":"Adam Chalupa;Joel Warner;Jarett Martin","doi":"10.1109/TSM.2024.3414121","DOIUrl":"10.1109/TSM.2024.3414121","url":null,"abstract":"Industrial semiconductor electrodeposition plating cells require recirculation of process chemicals with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow translate to a reduction of in-line defects and increased wafer yield.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"238-243"},"PeriodicalIF":2.3,"publicationDate":"2024-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-10DOI: 10.1109/TSM.2024.3411662
Sanghyuk Hong;Hasung Kong
The increasing number of fires in semiconductor factories requires new approaches to fire safety. It is important to study the specifics of the activities of companies that use potentially flammable materials in production, such as air filtration units, electrical cables and floor panels. The aim of the study was therefore to determine the level of fire risk in the clean rooms of these companies by means of real fire experiments. As a result, a fire risk assessment of the main combustible materials such as air filtration units, electrical cables and floor panels in the plenum room on the top floor of the cleanroom was carried out. The results of the experiment showed a low ignition propensity of the air filtration unit and limited fire propagation in the event of ignition. High calorific materials, such as fibreglass in filters, were identified as increasing the risk. Based on this, it was proposed to replace these materials with flame retardant materials and to improve the stop/fire control systems of the air filtration units. The results obtained in the study should be used for the development of technical recommendations for improving fire safety in critical premises at semiconductor factories.
{"title":"A Study on the Improvement of Safety and Efficiency of Clean Rooms in Semiconductor Factories Through Real Fire Experiments","authors":"Sanghyuk Hong;Hasung Kong","doi":"10.1109/TSM.2024.3411662","DOIUrl":"10.1109/TSM.2024.3411662","url":null,"abstract":"The increasing number of fires in semiconductor factories requires new approaches to fire safety. It is important to study the specifics of the activities of companies that use potentially flammable materials in production, such as air filtration units, electrical cables and floor panels. The aim of the study was therefore to determine the level of fire risk in the clean rooms of these companies by means of real fire experiments. As a result, a fire risk assessment of the main combustible materials such as air filtration units, electrical cables and floor panels in the plenum room on the top floor of the cleanroom was carried out. The results of the experiment showed a low ignition propensity of the air filtration unit and limited fire propagation in the event of ignition. High calorific materials, such as fibreglass in filters, were identified as increasing the risk. Based on this, it was proposed to replace these materials with flame retardant materials and to improve the stop/fire control systems of the air filtration units. The results obtained in the study should be used for the development of technical recommendations for improving fire safety in critical premises at semiconductor factories.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"394-401"},"PeriodicalIF":2.3,"publicationDate":"2024-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-06DOI: 10.1109/TSM.2024.3408926
L.-Y. Liu;L. Van Winckel;L. Boakes;M. Garcia Bardon;C. Rolin;L.-Å. Ragnarsson
The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature.
{"title":"Modeling the Energy Consumption of Integrated Circuit Fab Infrastructure","authors":"L.-Y. Liu;L. Van Winckel;L. Boakes;M. Garcia Bardon;C. Rolin;L.-Å. Ragnarsson","doi":"10.1109/TSM.2024.3408926","DOIUrl":"10.1109/TSM.2024.3408926","url":null,"abstract":"The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"422-427"},"PeriodicalIF":2.3,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-06DOI: 10.1109/TSM.2024.3410513
Benjamin Vavrille;Lionel Vignoud;Laurent-Luc Chapelon;Rafael Estevez
Thermoset resins are singular materials in the field of microelectronics. Because they exhibit a high contrast of thermomechanical properties with other integrated materials like oxides, metals or silicon, polymers can threaten the mechanical integrity of stacks. Knowing polymer properties allows manufacturers to foresee the compatibility between materials and improve chipsets reliability. At a bilayer scale, the properties mismatch between the polymer film and the silicon substrate causes an overall curvature of the wafer which evolves with temperature. By comparing the thermally induced curvature of two distinct substrates with the same film, the biaxial modulus and the coefficient of thermal expansion of the film can be determined. This method can not only check the achievement of the polymer cross-linking, but also estimates their relaxation temperatures. In this article, we present the ability of this method to, not only, measure those properties in the glassy state, but also, for the first time, in the rubbery state. We also illustrate the proficiency of this approach in detecting and characterizing two successive glassy states.
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