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Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN 基于多路径 DCNN 的混合缺陷模式晶片图识别与分类
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-26 DOI: 10.1109/TSM.2024.3418520
Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu
The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.
半导体产业是信息时代的核心产业。作为半导体产业的关键环节,晶圆制造对其发展起着举足轻重的作用。在晶圆检测阶段,对晶圆的每个裸片进行检测和标记,可以形成具有一定空间模式的晶圆图。对这些空间图案进行分析和分类,可以找出晶圆缺陷的原因,从而提高产量。然而,随着晶圆尺寸增大、线宽变小等,出现混合缺陷模式晶圆图案的概率也会增大。此外,混合缺陷模式晶片图比单一缺陷模式晶片图更难识别和分类。因此,本文提出了一种改进的深度卷积神经网络(DCNN)结构模型,用于混合缺陷模式晶圆图的识别和分类。从增加 DCNN 宽度的角度来看,改进后的网络结构可以避免由于 DCNN 的不断加深而导致的过拟合和特征提取受限等问题。该网络被称为多路径 DCNN(MP-DCNN)结构。实验结果表明,与现有方法相比,所提出的多路径 DCNN 结构具有更好的性能和更高的分类精度。
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引用次数: 0
DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy 从 DSH 到扩展-DSH:基于解耦回归策略的芯片级化学机械平坦化 (CMP) 模型升级
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-25 DOI: 10.1109/TSM.2024.3418827
Qian Yue;Chen Lan
Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.
化学机械平坦化(CMP)对于确保纳米尺度的芯片制造一致性至关重要。一系列现象学 CMP 过程模型的出现(Stine 等人,1997 年;Gbondo-Tugbawa,2002 年;Xie,2007 年;Vasilev,2011 年)表明,现有的模型升级方法在很大程度上是基于现象学模型假设的改变,需要深入了解复杂的过程机理,并需要较长的时间来提高精度。为解决这一问题,本文提出了一种用于模型升级的解耦回归策略。该策略采用数据驱动的方法来增强模型内部的耦合关系,从而在现有模型的基础上不断提高模拟精度。即使在建模人员缺乏对复杂过程机制的洞察力的情况下,它也能实现模型精度的提高。我们通过将密度阶梯高度(DSH)模型升级为扩展-DSH 模型来验证我们的方法,以解决 28 纳米节点侵蚀预测不佳的问题。将模型预测与硅数据进行比较后发现,Extend-DSH 模型与测量数据的吻合度更高,均方根误差从 159.31Å 减小到 6.89Å,决定系数从 -0.83561 增加到 0.6058,展示了基于解耦回归策略的芯片级 CMP 模型升级方法的有效性。
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引用次数: 0
Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum 利用整个光学发射光谱对等离子体蚀刻过程中的关键尺寸进行虚拟测量
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-24 DOI: 10.1109/TSM.2024.3416844
Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic
This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.
本文基于对光学发射光谱(OES)信号的所有时间和波长样本的分析,提出了等离子体蚀刻过程中虚拟计量(VM)的新方法。新方法将每个 OES 信号扁平化为单一向量,然后对训练数据集中扁平化 OES 信号向量形成的矩阵进行奇异值分解(SVD)。扁平化和标准化 OES 记录的低秩 SVD 投影可作为基于岭回归、人工神经网络和随机森林的 VM 模型的输入。随后,对从一家大型 300 毫米晶圆制造厂收集的数据集进行了虚拟机研究,结果表明,使用新提出的基于 SVD 的 OES 特征始终优于基准虚拟机模型特征。根据可分析的岭回归虚拟机模型形式对特征重要性进行的其他分析表明,OES 信号部分的独特时频模式对预测相关临界维度具有很高的参考价值,这清楚地证明了将整个 OES 信号用于虚拟机的必要性。
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引用次数: 0
Sustainable Semiconductor Manufacturing: The Role of Lithography 可持续半导体制造:光刻技术的作用
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-19 DOI: 10.1109/TSM.2024.3416830
Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin
Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.
可持续发展与半导体制造之间的联系,对于这两个领域的专家来说可能都不明显;但随着企业纷纷承诺到 2050 年实现碳净零排放,这种不明显的联系正在慢慢消失。2023 年,imec 发布了一个模型(imec.netzero),用于量化集成电路(IC)制造对环境的影响。在本文中,我们将利用排放趋势来了解造成影响的工艺。光刻技术--193 纳米(DUV)和 13.5 纳米(EUV)--在改变集成电路芯片制造的总体排放量方面发挥着重要作用。减少与光刻技术相关的排放的方法包括最大限度提高产量的设计和工艺选择,以及减少消耗的工具操作选择。制造过程中的低排放行为一旦被量化,其潜在效益就会得到推广。工程师们习惯于优化性能,现在我们必须同时优化降低排放。
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引用次数: 0
Efficient Dual-Attention-Based Knowledge Distillation Network for Unsupervised Wafer Map Anomaly Detection 基于知识蒸馏网络的高效双注意无监督晶圆图异常检测
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-18 DOI: 10.1109/TSM.2024.3416055
Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani
Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.
检测晶圆图异常对于防止半导体制造中的良率损失至关重要,但复杂的模式和资源密集型标记数据前提条件阻碍了精确的深度学习分割。本文提出了一种创新的无监督方法,用于检测晶圆图中的像素级异常。它利用高效的双重关注模块和知识提炼网络来学习无异常的缺陷分布。除了在教师网络的特征金字塔层次结构上加入高效的双重注意模块外,知识转移是通过将预先训练好的教师网络中的信息提炼到具有类似结构的学生网络中来实现的,这种结构通过捕捉位置和通道维度中的上下文关联,增强了金字塔层次结构中的特征表示和分割,从而有选择性地强调相关特征,摒弃无关特征。此外,它还能使学生网络获得更好的分层特征知识,从而准确识别不同尺度的异常情况。特征金字塔中的不相似性可作为一种判别功能,预测异常的可能性,从而实现高精度的像素级异常检测。因此,我们提出的方法在 WM-811K 和 MixedWM38 数据集上表现出色,AUROC、AUPR、AUPRO 和 F1 分数分别为(99.65%、99.35%)、(97.31%、92.13%)、(90.76%、84.66%),推理速度为 3.204 FPS,显示了其高精度和高效率。
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引用次数: 0
Elimination of Si-C Defect on Wafer Surface in High-Temperature SPM Process Through Nitrogen Purge in 300-mm Single-Wafer Chamber 在高温 SPM 工艺中通过 300 毫米单晶片室中的氮气吹扫消除晶圆表面的 Si-C 缺陷
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-18 DOI: 10.1109/TSM.2024.3416079
Rajan Kumar Singh;Alfie Lin;Haley Lin;Max Chen;Yvonne Pan;Nancy Cho;Willy Chen;Jamiet Tung;Walt Hu;Wilson Huang
During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.
在半导体制造过程中,高温过氧化硫酸混合物(SPM)和空气中的分子污染物(AMC)会在晶片表面形成碳化硅(Si-C)等缺陷。此外,缺陷还会对设备性能、产量和生产效率产生不利影响。在这项工作中,我们提出了一种新方法,即在单晶圆腔内引入一个额外的氮气(N2)吹扫喷嘴,以减少总挥发性有机化合物(t-VOC)。此外,我们还深入探讨了 SPM 中缺陷形成的内在机理,而这一机理此前尚未得到解释。在 SPM 过程中,缺陷是由 AMC 和高温形成的。因此,本研究对各种 AMC 进行了研究。此外,还分析了 Si-C 缺陷数量与温度和化学流动持续时间的相关性。实验结果表明,缺陷和 t-VOC 遵循相同的浓度趋势。我们的氮气吹扫方法有效地稀释了腔室环境,降低了污染颗粒与晶片表面之间的附着能量。单晶圆室内合适的氮气吹扫率有助于消除晶圆表面约 63% 的缺陷。因此,这种方法对于最大限度地减少 Si-C 缺陷和改善高温 SPM 湿式清洁工艺的腔室环境至关重要。
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引用次数: 0
Computational Study of Chemical Uniformity Impacts on Electrodeposition 化学均匀性对电沉积影响的计算研究
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-13 DOI: 10.1109/TSM.2024.3414121
Adam Chalupa;Joel Warner;Jarett Martin
Industrial semiconductor electrodeposition plating cells require recirculation of process chemicals with consistent flow and minimal contaminants to prevent defects from developing during film deposition. This manuscript investigates how recirculation nozzle quality and nozzle machining can affect bath chemical uniformity. Computational fluid dynamics simulations are utilized to visualize bath chemical velocities based on variable nozzle conditions in four case studies. Results show that strict quality control of inlet nozzles, in conjunction with proper mounting angles, induce laminar bath flow. Greater fluid uniformity and laminar flow translate to a reduction of in-line defects and increased wafer yield.
工业半导体电沉积电镀单元要求工艺化学品的再循环具有稳定的流量和最少的污染物,以防止薄膜沉积过程中产生缺陷。本手稿研究了再循环喷嘴质量和喷嘴加工如何影响镀液化学均匀性。在四个案例研究中,利用计算流体动力学模拟可视化基于不同喷嘴条件的熔池化学速度。结果表明,严格的入口喷嘴质量控制与适当的安装角度相结合,可产生层流浴。更高的流体均匀性和层流可减少在线缺陷,提高晶片产量。
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引用次数: 0
A Study on the Improvement of Safety and Efficiency of Clean Rooms in Semiconductor Factories Through Real Fire Experiments 通过真实火灾实验提高半导体工厂洁净室安全性和效率的研究
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-10 DOI: 10.1109/TSM.2024.3411662
Sanghyuk Hong;Hasung Kong
The increasing number of fires in semiconductor factories requires new approaches to fire safety. It is important to study the specifics of the activities of companies that use potentially flammable materials in production, such as air filtration units, electrical cables and floor panels. The aim of the study was therefore to determine the level of fire risk in the clean rooms of these companies by means of real fire experiments. As a result, a fire risk assessment of the main combustible materials such as air filtration units, electrical cables and floor panels in the plenum room on the top floor of the cleanroom was carried out. The results of the experiment showed a low ignition propensity of the air filtration unit and limited fire propagation in the event of ignition. High calorific materials, such as fibreglass in filters, were identified as increasing the risk. Based on this, it was proposed to replace these materials with flame retardant materials and to improve the stop/fire control systems of the air filtration units. The results obtained in the study should be used for the development of technical recommendations for improving fire safety in critical premises at semiconductor factories.
随着半导体工厂火灾数量的不断增加,需要采取新的消防安全方法。研究在生产中使用潜在易燃材料(如空气过滤装置、电缆和地板)的企业的具体活动非常重要。因此,研究的目的是通过真实的火灾实验来确定这些公司无尘室的火灾风险水平。因此,我们对无尘室顶层通风室中的空气过滤装置、电缆和地板等主要可燃材料进行了火灾风险评估。实验结果表明,空气过滤装置的着火倾向较低,着火时火势蔓延有限。高热量材料(如过滤器中的玻璃纤维)被认为会增加风险。在此基础上,建议用阻燃材料取代这些材料,并改进空气过滤装置的阻燃/防火控制系统。研究结果应用于制定技术建议,以改善半导体工厂关键场所的消防安全。
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引用次数: 0
Modeling the Energy Consumption of Integrated Circuit Fab Infrastructure 集成电路制造基础设施能耗建模
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-06 DOI: 10.1109/TSM.2024.3408926
L.-Y. Liu;L. Van Winckel;L. Boakes;M. Garcia Bardon;C. Rolin;L.-Å. Ragnarsson
The bottom-up assessment of environmental impact of the fabrication of integrated circuit chips relies on accurate modeling of the operation of a high-volume semiconductor fab. In our virtual fab model, we structure fab operation in three concentric sectors: the wafer processing equipment, the generation of utilities that feeds the equipment, and the fab infrastructure that provides a suitable environment for the equipment and the workers. In this paper, we first address the correlation between process flow, wafer demand and fab dimension, which sets the scale of the virtual fab and enables global fab energy consumption estimates. Next, we describe how energy consumption calculations are performed sector-by-sector and how these evolve over the deployment of successive generations of logic nodes. In particular, we propose an original bottom-up model for fab infrastructure energy consumption that takes into account local climate dependence of a fab’s geographical location. The essence of these learnings is condensed into a normalized power consumption per manufacturing area (in kW/m2) that is deduced from our models as a function of technology maturity and location. These values form a good comparison basis with data from industry and literature.
自下而上地评估集成电路芯片制造对环境的影响,有赖于对大批量半导体工厂运作的精确建模。在我们的虚拟工厂模型中,我们将工厂的运行分为三个同心圆部分:晶圆加工设备、为设备供电的公用设施以及为设备和工人提供合适环境的工厂基础设施。在本文中,我们首先讨论了工艺流程、晶圆需求和工厂规模之间的相关性,从而确定了虚拟工厂的规模,并实现了全球工厂能耗估算。接下来,我们介绍了如何逐个部门进行能耗计算,以及这些计算如何随着连续几代逻辑节点的部署而演变。特别是,我们提出了一种自下而上的工厂基础设施能耗原创模型,该模型考虑到了工厂地理位置对当地气候的依赖性。这些经验的精髓浓缩为每个制造区域的归一化能耗(单位:千瓦/平方米),该能耗是根据我们的模型推导出来的,是技术成熟度和地理位置的函数。这些数值是与行业和文献数据进行比较的良好基础。
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引用次数: 0
Advances in the Thermal Study of Polymers for Microelectronics Using the Thermally Induced Curvature Approach 利用热诱导曲率法对微电子聚合物进行热研究的进展
IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-06 DOI: 10.1109/TSM.2024.3410513
Benjamin Vavrille;Lionel Vignoud;Laurent-Luc Chapelon;Rafael Estevez
Thermoset resins are singular materials in the field of microelectronics. Because they exhibit a high contrast of thermomechanical properties with other integrated materials like oxides, metals or silicon, polymers can threaten the mechanical integrity of stacks. Knowing polymer properties allows manufacturers to foresee the compatibility between materials and improve chipsets reliability. At a bilayer scale, the properties mismatch between the polymer film and the silicon substrate causes an overall curvature of the wafer which evolves with temperature. By comparing the thermally induced curvature of two distinct substrates with the same film, the biaxial modulus and the coefficient of thermal expansion of the film can be determined. This method can not only check the achievement of the polymer cross-linking, but also estimates their relaxation temperatures. In this article, we present the ability of this method to, not only, measure those properties in the glassy state, but also, for the first time, in the rubbery state. We also illustrate the proficiency of this approach in detecting and characterizing two successive glassy states.
热固性树脂是微电子领域的一种特殊材料。由于聚合物与氧化物、金属或硅等其他集成材料的热机械特性反差很大,因此会威胁到堆栈的机械完整性。了解聚合物的特性可以让制造商预见材料之间的兼容性,提高芯片组的可靠性。在双层尺度上,聚合物薄膜和硅衬底之间的特性不匹配会导致晶片整体弯曲,这种弯曲会随温度变化而变化。通过比较使用相同薄膜的两种不同基底的热诱导曲率,可以确定薄膜的双轴模量和热膨胀系数。这种方法不仅能检测聚合物交联的实现情况,还能估算它们的弛豫温度。在本文中,我们介绍了这种方法不仅能测量玻璃态的这些特性,还首次测量了橡胶态的这些特性。我们还说明了这种方法在检测和表征两种连续玻璃态时的熟练程度。
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引用次数: 0
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IEEE Transactions on Semiconductor Manufacturing
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