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Circuits and Systems for Green Video Communications: Fundamentals and Recent Trends 绿色视频通信的电路和系统:基本原理和最新趋势
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-02-10 DOI: 10.1109/JETCAS.2025.3540360
Christian Herglotz;Daniel Palomino;Olivier Le Meur;C.-C. Jay Kuo
The past years have shown that due to the global success of video communication technology, the corresponding hardware systems nowadays contribute significantly to pollution and resource consumption on a global scale, accounting for 1% of global green house gas emissions in 2018. This aspect of sustainability has thus reached increasing attention in academia and industry. In this paper, we present different aspects of sustainability including resource consumption and greenhouse gas emissions, while putting a major focus on the energy consumption during the use of video systems. Finally, we provide an overview on recent research in the domain of green video communications showing promising results and highlighting areas where more research should be performed.
过去几年的情况表明,由于视频通信技术在全球范围内的成功,如今相应的硬件系统在全球范围内造成了巨大的污染和资源消耗,2018年占全球温室气体排放量的1%。因此,可持续性的这一方面在学术界和工业界受到越来越多的关注。在本文中,我们介绍了可持续性的不同方面,包括资源消耗和温室气体排放,同时主要关注视频系统使用过程中的能源消耗。最后,我们概述了绿色视频通信领域的最新研究,展示了有希望的结果,并强调了应该进行更多研究的领域。
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引用次数: 0
Real-Time Quality- and Energy-Aware Bitrate Ladder Construction for Live Video Streaming 实时视频流的质量和能量感知比特率阶梯结构
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-02-07 DOI: 10.1109/JETCAS.2025.3539948
Mohammad Ghasempour;Hadi Amirpour;Christian Timmerer
Live video streaming’s growing demand for high-quality content has resulted in significant energy consumption, creating challenges for sustainable media delivery. Traditional adaptive video streaming approaches rely on the over-provisioning of resources leading to a fixed bitrate ladder, which is often inefficient for the heterogeneous set of use cases and video content. Although dynamic approaches like per-title encoding optimize the bitrate ladder for each video, they mainly target video-on-demand to avoid latency and fail to address energy consumption. In this paper, we present LiveESTR, a method for building a quality- and energy-aware bitrate ladder for live video streaming. LiveESTR eliminates the need for exhaustive video encoding processes on the server side, ensuring that the bitrate ladder construction process is fast and energy efficient. A lightweight model for multi-label classification, along with a lookup table, is utilized to estimate the optimized resolution-bitrate pair in the bitrate ladder. Furthermore, both spatial and temporal resolutions are supported to achieve high energy savings while preserving compression efficiency. Therefore, a tunable parameter $lambda $ and a threshold $tau $ are introduced to balance the trade-off between compression/quality and energy efficiency. Experimental results show that LiveESTR reduces the encoder and decoder energy consumption by 74.6 % and 29.7 %, with only a 2.1 % increase in Bjøntegaard Delta Rate (BD-Rate) compared to traditional per-title encoding. Furthermore, it is shown that by increasing $lambda $ to prioritize video quality, LiveESTR achieves 2.2 % better compression efficiency in terms of BD-Rate while still reducing decoder energy consumption by 7.5 %.
直播视频流对高质量内容的需求不断增长,导致了大量的能源消耗,为可持续的媒体交付带来了挑战。传统的自适应视频流方法依赖于资源的过度供应,导致固定的比特率阶梯,这对于异构的用例和视频内容集通常是低效的。虽然像按标题编码这样的动态方法优化了每个视频的比特率阶梯,但它们主要针对视频点播,以避免延迟,无法解决能耗问题。在本文中,我们提出了LiveESTR,一种为实时视频流构建质量和能量感知比特率阶梯的方法。LiveESTR消除了在服务器端进行详尽的视频编码过程的需要,确保了比特率阶梯构建过程的快速和节能。使用轻量级的多标签分类模型和查找表来估计比特率阶梯中优化的分辨率-比特率对。此外,支持空间和时间分辨率,在保持压缩效率的同时实现高能量节约。因此,引入可调参数$lambda $和阈值$tau $来平衡压缩/质量和能源效率之间的权衡。实验结果表明,LiveESTR将编码器和解码器的能耗降低了74.6% % and 29.7 %, with only a 2.1 % increase in Bjøntegaard Delta Rate (BD-Rate) compared to traditional per-title encoding. Furthermore, it is shown that by increasing $lambda $ to prioritize video quality, LiveESTR achieves 2.2 % better compression efficiency in terms of BD-Rate while still reducing decoder energy consumption by 7.5 %.
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引用次数: 0
Learned Image Compression With Efficient Cross-Platform Entropy Coding 学习图像压缩与高效的跨平台熵编码
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-02-04 DOI: 10.1109/JETCAS.2025.3538652
Runyu Yang;Dong Liu;Feng Wu;Wen Gao
Learned image compression has shown remarkable compression efficiency gain over the traditional image compression solutions, which is partially attributed to the learned entropy models and the adopted entropy coding engine. However, the inference of the entropy models and the sequential nature of the entropy coding both incur high time complexity. Meanwhile, the neural network-based entropy models usually involve floating-point computations, which incur inconsistent probability estimation and decoding failure in different platforms. We address these limitations by introducing an efficient and cross-platform entropy coding method, chain coding-based latent compression (CC-LC), into learned image compression. First, we leverage the classic chain coding and carefully design a block-based entropy coding procedure, significantly reducing the number of coding symbols and thus the coding time. Second, since CC-LC is not based on neural networks, we propose a rate estimation network as a surrogate of CC-LC during the end-to-end training. Third, we alternately train the analysis/synthesis networks and the rate estimation network for the rate-distortion optimization, making the learned latent fit CC-LC. Experimental results show that our method achieves much lower time complexity than the other learned image compression methods, ensures cross-platform consistency, and has comparable compression efficiency with BPG. Our code and models are publicly available at https://github.com/Yang-Runyu/CC-LC.
与传统的图像压缩方案相比,学习图像压缩显示出显著的压缩效率提高,这部分归功于学习熵模型和所采用的熵编码引擎。然而,熵模型的推断性和熵编码的时序性都会导致较高的时间复杂度。同时,基于神经网络的熵模型通常涉及浮点计算,在不同的平台上导致概率估计不一致和解码失败。我们通过在学习图像压缩中引入一种高效的跨平台熵编码方法,基于链编码的潜在压缩(CC-LC)来解决这些限制。首先,我们利用经典的链编码,精心设计了基于块的熵编码过程,显著减少了编码符号的数量,从而缩短了编码时间。其次,由于CC-LC不是基于神经网络,我们提出了一个速率估计网络作为端到端训练CC-LC的替代品。第三,我们交替训练速率失真优化的分析/综合网络和速率估计网络,使学习到的潜在拟合CC-LC。实验结果表明,该方法的时间复杂度远低于其他已学习的图像压缩方法,并保证了跨平台的一致性,压缩效率与BPG相当。我们的代码和模型可以在https://github.com/Yang-Runyu/CC-LC上公开获得。
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引用次数: 0
BiDSRS+: Resource Efficient Reconfigurable Real Time Bidirectional Super Resolution System for FPGAs BiDSRS+: fpga的资源高效可重构实时双向超分辨率系统
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-02-03 DOI: 10.1109/JETCAS.2025.3538016
Rashed Al Amin;Roman Obermaisser
Super-resolution (SR) systems represent a rapidly advancing area within Information and Communication Technology (ICT) due to their significant applications in computer vision and visual communication. Integrating SR systems with Deep Neural Networks (DNNs) is a widely adopted method for leveraging faster and improved image reconstruction. However, the real-time computational demands, extensive energy overhead and the huge memory footprints associated with DNN-based SR systems limit their throughput and scalability. Field-programmable gate arrays (FPGAs) present a viable and promising solution for exploring the structure and architecture of SR systems due to their reconfigurable nature and parallel computing capabilities. The existing FPGA-based solutions can effectively reduce the computational latency in SR systems, they often result in higher resource and energy consumption. Besides, the traditional SR techniques generally focus on either upscaling or downscaling images or videos without offering any scaling reconfigurability. To address these limitations, this paper introduces BiDSRS+, a novel FPGA based resource-efficient and reconfigurable real-time SR system using modified bicubic interpolation method. In addition, BiDSRS+ supports both upscaling and downscaling of images and videos, enhancing its versatility. Evaluations conducted on the Xilinx ZCU 102 FPGA board reveal substantial resource savings, with reductions of 44x LUT, 31x BRAM, and 35x DSP utilization compared to state-of-the-art DNN-based SR systems, albeit with a trade-off in throughput of 0.5x. Furthermore, when compared to leading algorithm-based SR systems, BiDSRS+ achieves reductions of 5.8x LUT, 1.75x BRAM, and 2.3x Power consumption, without compromising the throughput. Due to its high resource efficiency and reconfigurability with a throughput of 4K@60 FPS, BiDSRS+ offers significant advantages in promoting sustainable and energy-efficient green video communication.
超分辨率(SR)系统由于其在计算机视觉和视觉通信中的重要应用,代表了信息和通信技术(ICT)中快速发展的领域。将SR系统与深度神经网络(dnn)集成是一种广泛采用的方法,可以利用更快、更好的图像重建。然而,与基于dnn的SR系统相关的实时计算需求、广泛的能源开销和巨大的内存占用限制了它们的吞吐量和可扩展性。现场可编程门阵列(fpga)由于其可重构特性和并行计算能力,为探索SR系统的结构和架构提供了一个可行且有前途的解决方案。现有的基于fpga的解决方案可以有效地降低SR系统的计算延迟,但往往会导致更高的资源和能源消耗。此外,传统的SR技术通常只关注图像或视频的升级或降级,而不提供任何缩放可重构性。为了解决这些限制,本文介绍了一种基于FPGA的资源高效可重构实时SR系统BiDSRS+,该系统采用改进的双三次插值方法。此外,BiDSRS+支持图像和视频的放大和缩小,增强了其通用性。对Xilinx ZCU 102 FPGA板进行的评估显示,与最先进的基于dnn的SR系统相比,节省了大量资源,减少了44倍的LUT, 31倍的BRAM和35倍的DSP利用率,尽管吞吐量降低了0.5倍。此外,与领先的基于算法的SR系统相比,BiDSRS+实现了5.8倍的LUT, 1.75倍的BRAM和2.3倍的功耗降低,而不影响吞吐量。BiDSRS+具有较高的资源效率和可重构性,吞吐量可达4K@60 FPS,在推动可持续节能的绿色视频通信方面具有显著优势。
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引用次数: 0
ApprOchs: A Memristor-Based In-Memory Adaptive Approximate Adder 一种基于忆阻器的内存自适应近似加法器
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-01-31 DOI: 10.1109/JETCAS.2025.3537328
Dominik Ochs;Lukas Rapp;Leandro Borzyk;Nima Amirafshar;Nima TaheriNejad
As silicon scaling nears its limits and the Big Data era unfolds, in-memory computing is increasingly important for overcoming the Von Neumann bottleneck and thus enhancing modern computing performance. One of the rising in-memory technologies are Memristors, which are resistors capable of memorizing state based on an applied voltage, making them useful for storage and computation. Another emerging computing paradigm is Approximate Computing, which allows for errors in calculations to in turn reduce die area, processing time and energy consumption. In an attempt to combine both concepts and leverage their benefits, we propose the memristor-based adaptive approximate adder ApprOchs - which is able to selectively compute segments of an addition either approximately or exactly. ApprOchs is designed to adapt to the input data given and thus only compute as much as is needed, a quality current State-of-the-Art (SoA) in-memory adders lack. Despite also using OR-based approximation in the lower k bit, ApprOchs has the edge over S-SINC because ApprOchs can skip the computation of the upper n-k bit for a small number of possible input combinations (22k of 22n possible combinations skip the upper bits). Compared to SoA in-memory approximate adders, ApprOchs outperforms them in terms of energy consumption while being highly competitive in terms of error behavior, with moderate speed and area efficiency. In application use cases, ApprOchs demonstrates its energy efficiency, particularly in machine learning applications. In MNIST classification using Deep Convolutional Neural Networks, we achieve 78.4% energy savings compared to SoA approximate adders with the same accuracy as exact adders at 98.9%, while for k-means clustering, we observed a 69% reduction in energy consumption with no quality drop in clustering results compared to the exact computation. For image blurring, we achieve up to 32.7% energy reduction over the exact computation and in its most promising configuration ( $k=3$ ), the ApprOchs adder consumes 13.4% less energy than the most energy-efficient competing SoA design (S-SINC+), while achieving a similarly excellent median image quality at 43.74dB PSNR and 0.995 SSIM.
随着芯片规模接近极限和大数据时代的到来,内存计算对于克服冯·诺伊曼瓶颈从而提高现代计算性能变得越来越重要。记忆电阻器是一种新兴的内存技术,它是一种能够根据施加的电压记忆状态的电阻器,可用于存储和计算。另一种新兴的计算范式是近似计算,它允许计算中的错误,从而减少模具面积、处理时间和能耗。为了结合这两个概念并利用它们的优点,我们提出了基于忆阻器的自适应近似加法器方法-它能够有选择地近似或精确地计算加法的部分。方法被设计为适应给定的输入数据,因此只计算所需的数据,这是当前最先进的(SoA)内存加法器所缺乏的质量。尽管在较低的k位也使用基于or的近似,但ApprOchs比S-SINC有优势,因为对于少量可能的输入组合,ApprOchs可以跳过较高的n-k位的计算(22n种可能的组合中有22k种会跳过较高的位)。与SoA内存中的近似加法器相比,方法在能耗方面优于它们,同时在错误行为方面具有很强的竞争力,具有中等的速度和面积效率。在应用用例中,ApprOchs展示了其能源效率,特别是在机器学习应用中。在使用深度卷积神经网络的MNIST分类中,与SoA近似加法器相比,我们实现了78.4%的节能,而精确加法器的准确率为98.9%,而对于k-means聚类,我们观察到与精确计算相比,能耗降低了69%,聚类结果的质量没有下降。对于图像模糊,我们在精确计算中实现了高达32.7%的能量减少,并且在其最有前途的配置($k=3$)中,ApprOchs加器比最节能的SoA设计(S-SINC+)消耗的能量少13.4%,同时在43.74dB PSNR和0.995 SSIM上实现了同样出色的中位数图像质量。
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引用次数: 0
Do We Need 10 bits? Assessing HEVC Encoders for Energy-Efficient HDR Video Streaming 我们需要10位吗?评估高效节能HDR视频流的HEVC编码器
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-01-23 DOI: 10.1109/JETCAS.2025.3533041
Alexandre Mercat;Joose Sainio;Steven Le Moan;Christian Herglotz
High-dynamic range (HDR) video content has gained popularity due to its enhanced color depth and luminance range, but it also presents new challenges in terms of compression efficiency and energy consumption. In this paper, we present an in-depth study of the compression performance and energy efficiency of HDR video encoding using High-Efficiency Video Coding (HEVC). In addition to using a native 10-bit HDR encoding configuration as a reference, we explore whether applying tone mapping to an 8-bit representation before encoding can result in additional bitrate and energy savings without compromising visual quality. The main contributions of this work are as follows: 1) a detailed evaluation of four HDR video encoding configurations, three of which leverage tone mapping techniques, 2) a comprehensive experimental setup involving over 15,000 individual encodings across three open-source HEVC encoders (Kvazaar, x265, and SVT-HEVC) and multiple presets, 3) the use of two advanced perception-based metrics for BD-rate calculations, one of which is specifically tailored to capture colour distortions and 4) an open-source dataset consisting of all experimental results for further research. Among the three tone-mapping configurations tested, our findings show that a simple bit-shifting approach can achieves significant reductions in both bitrate and energy consumption compared to the native 10-bit HDR encoding configuration. This research aims to lay an initial foundation for understanding the balance between coding efficiency and energy consumption in HDR video encoding, offering valuable insights to guide future advancements in the field.
高动态范围(HDR)视频内容因其增强的色彩深度和亮度范围而受到欢迎,但它也在压缩效率和能耗方面提出了新的挑战。本文采用高效视频编码(High-Efficiency video Coding, HEVC)技术对HDR视频编码的压缩性能和能效进行了深入研究。除了使用原生10位HDR编码配置作为参考外,我们还探讨了在编码之前将色调映射应用于8位表示是否可以在不影响视觉质量的情况下节省额外的比特率和能源。本工作的主要贡献如下:1)对四种HDR视频编码配置进行详细评估,其中三种利用色调映射技术;2)在三个开源HEVC编码器(Kvazaar, x265和SVT-HEVC)和多个预设中涉及超过15,000个单独编码的综合实验设置;3)使用两个基于感知的高级指标进行bd率计算;其中一个是专门为捕获颜色失真而定制的,4)一个由所有实验结果组成的开源数据集,用于进一步研究。在测试的三种色调映射配置中,我们的研究结果表明,与原生10位HDR编码配置相比,简单的位移位方法可以显著降低比特率和能耗。本研究旨在为理解HDR视频编码中编码效率和能耗之间的平衡奠定初步基础,为指导该领域的未来发展提供有价值的见解。
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引用次数: 0
Energy-Efficient Saliency-Guided Video Coding Framework for Real-Time Applications 面向实时应用的高能效显著性视频编码框架
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2025-01-02 DOI: 10.1109/JETCAS.2024.3525339
Tero Partanen;Minh Hoang;Alexandre Mercat;Joose Sainio;Jarno Vanne
The significant growth in global video data traffic can be mitigated by saliency-based video coding schemes that seek to increase coding efficiency without any loss of objective visual quality by compressing salient video regions less heavily than non-salient regions. However, conducting salient object detection (SOD) on every video frame before encoding tends to lead to substantial complexity and energy consumption overhead, especially if state-of-the-art deep learning techniques are used in saliency detection. This work introduces a saliency-guided video encoding framework that reduces the energy consumption over frame-by-frame SOD by increasing the detection interval and applying the proposed region-of-interest (ROI) tracking between successive detections. The computational complexity of our ROI tracking technique is kept low by predicting object movements from motion vectors, which are inherently calculated during encoding. Our experimental results demonstrate that the proposed ROI tracking solution saves energy by 86-95% and attains 84-94% accuracy over frame-by-frame SOD. Correspondingly, integrating our proposal into the complete saliency-guided video coding scheme reduces energy consumption on CPU by 79-82% at a cost of weighted PSNR of less than 5%. These findings indicate that our solution has significant potential for low-cost and low-power streaming media applications.
全球视频数据流量的显著增长可以通过基于显著性的视频编码方案来缓解,该方案通过压缩显著视频区域而不是非显著视频区域来寻求在不损失客观视觉质量的情况下提高编码效率。然而,在编码之前对每个视频帧进行显著目标检测(SOD)往往会导致大量的复杂性和能耗开销,特别是在显著性检测中使用最先进的深度学习技术时。这项工作引入了一个显著性引导的视频编码框架,通过增加检测间隔和在连续检测之间应用提议的感兴趣区域(ROI)跟踪来减少逐帧SOD的能量消耗。我们的ROI跟踪技术通过从运动向量预测物体运动来保持较低的计算复杂度,运动向量在编码过程中固有地计算。实验结果表明,所提出的ROI跟踪方案在逐帧SOD上节能86-95%,准确率达到84-94%。相应地,将我们的建议集成到完整的显著性引导视频编码方案中,以加权PSNR小于5%为代价,减少了79-82%的CPU能耗。这些发现表明,我们的解决方案在低成本和低功耗的流媒体应用中具有巨大的潜力。
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引用次数: 0
Compact Visual Data Representation for Green Multimedia–A Human Visual System Perspective 绿色多媒体的紧凑视觉数据表示——人类视觉系统视角
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-12-30 DOI: 10.1109/JETCAS.2024.3524260
Peilin Chen;Xiaohan Fang;Meng Wang;Shiqi Wang;Siwei Ma
The Human Visual System (HVS), with its intricate sophistication, is capable of achieving ultra-compact information compression for visual signals. This remarkable ability is coupled with high generalization capability and energy efficiency. By contrast, the state-of-the-art Versatile Video Coding (VVC) standard achieves a compression ratio of around 1,000 times for raw visual data. This notable disparity motivates the research community to draw inspiration to effectively handle the immense volume of visual data in a green way. Therefore, this paper provides a survey of how visual data can be efficiently represented for green multimedia, in particular when the ultimate task is knowledge extraction instead of visual signal reconstruction. We introduce recent research efforts that promote green, sustainable, and efficient multimedia in this field. Moreover, we discuss how the deep understanding of the HVS can benefit the research community, and envision the development of future green multimedia technologies.
人类视觉系统(HVS)具有复杂的复杂性,能够实现对视觉信号的超紧凑信息压缩。这种卓越的能力与高泛化能力和能源效率相结合。相比之下,最先进的通用视频编码(VVC)标准对原始视觉数据实现了约1000倍的压缩比。这种显著的差异促使研究界汲取灵感,以一种绿色的方式有效地处理大量的视觉数据。因此,本文对绿色多媒体中如何有效地表示视觉数据进行了研究,特别是当最终任务是知识提取而不是视觉信号重构时。我们介绍了在该领域促进绿色、可持续和高效多媒体的最新研究成果。此外,我们还讨论了对HVS的深入理解如何使研究界受益,并展望了未来绿色多媒体技术的发展。
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引用次数: 0
Low-Power Multiversion Interpolation Filter Accelerator With Hardware Reuse for AV1 Codec 低功耗多版本插值滤波器加速器与硬件复用AV1编解码器
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-12-25 DOI: 10.1109/JETCAS.2024.3523246
Daiane Freitas;Patrick Rosa;Leonardo Müller;Daniel Palomino;Cláudio M. Diniz;Mateus Grellert;Guilherme Corrêa
In modern video encoders, sub-pixel motion models are used to represent smoother transitions between neighboring frames, which is specially useful in regions with intense movement. The AV1 video codec introduces adaptive filtering for sub-pixel interpolation in the inter-frame prediction stage, enhancing flexibility in Motion Estimation (ME) and Motion Compensation (MC), using three filter types: Regular, Sharp, and Smooth. However, the increased variety of filters leads to higher complexity and energy consumption, particularly during the resource-intensive generation of sub-pixel samples. To address this challenge, this paper presents a hardware accelerator optimized for AV1 interpolation, incorporating energy-saving features for unused filters. The accelerator includes one precise version that can be used for both MC and ME and two approximate versions for ME, designed to maximize hardware efficiency and minimize implementation costs. The proposed design can process videos at resolutions up to 4320p at 50 frames per second for MC and 2,656.14 million samples per second for ME, with a power dissipation ranging between 21.25 mW and 40.06 mW, and an average coding efficiency loss of 0.67% and 1.11%, depending on the filter type and version.
在现代视频编码器中,亚像素运动模型用于表示相邻帧之间更平滑的过渡,这在运动剧烈的区域特别有用。AV1视频编解码器在帧间预测阶段引入了亚像素插值的自适应滤波,增强了运动估计(ME)和运动补偿(MC)的灵活性,使用三种滤波器类型:常规,锐利和平滑。然而,过滤器种类的增加导致了更高的复杂性和能量消耗,特别是在资源密集型的亚像素样本生成过程中。为了解决这一挑战,本文提出了一种针对AV1插值进行优化的硬件加速器,并结合了未使用滤波器的节能特性。加速器包括一个可用于MC和ME的精确版本和两个用于ME的近似版本,旨在最大限度地提高硬件效率并最小化实施成本。所提出的设计可以处理分辨率高达4320p的视频,MC为每秒50帧,ME为每秒2665614万样本,功耗范围为21.25 mW至40.06 mW,根据滤波器类型和版本的不同,平均编码效率损失为0.67%和1.11%。
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引用次数: 0
IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors IEEE关于电路和系统信息中新兴和选定主题的作者期刊
IF 3.7 2区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-12-13 DOI: 10.1109/JETCAS.2024.3502893
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IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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