Pub Date : 2024-01-19DOI: 10.1109/JETCAS.2024.3356010
Zi-Hao Fu;Ming-Xuan Li;Tzyh-Ghuang Ma;Chan-Shin Wu;Kun-You Lin
This paper presents an ultra-wideband (UWB) medium power amplifier (MPA) and a broadband high-power power amplifier (HPA) operating at the 5G/6G frequency bands. By using $0.15~mu text{m}$ GaAs pseudomorphic high electron mobility transistor (pHEMT) technology process, the proposed UWB MPA delivers an average small-signal gain of 16.5 dB, a saturation output power ( $text{P}_{mathrm {sat}}$ ) of 24 dBm, and a peak power-added efficiency (PAE) over 24% from 24 to 38 GHz with a chip area of $2times1$ mm2. The broadband HPA demonstrates a 17-dB average small-signal gain, 29-dBm $text{P}_{mathrm {sat}}$ , and a PAE over 28% from 24 to 32 GHz with a $2.4times1.1$ mm2 chip size. The measurement results have demonstrated the great potential of the proposed PA for 5G/6G millimeter-wave applications.
{"title":"Millimeter-Wave GaAs Ultra-Wideband Medium Power Amplifier and Broadband High-Power Power Amplifier for 5G/6G Applications","authors":"Zi-Hao Fu;Ming-Xuan Li;Tzyh-Ghuang Ma;Chan-Shin Wu;Kun-You Lin","doi":"10.1109/JETCAS.2024.3356010","DOIUrl":"10.1109/JETCAS.2024.3356010","url":null,"abstract":"This paper presents an ultra-wideband (UWB) medium power amplifier (MPA) and a broadband high-power power amplifier (HPA) operating at the 5G/6G frequency bands. By using \u0000<inline-formula> <tex-math>$0.15~mu text{m}$ </tex-math></inline-formula>\u0000 GaAs pseudomorphic high electron mobility transistor (pHEMT) technology process, the proposed UWB MPA delivers an average small-signal gain of 16.5 dB, a saturation output power (\u0000<inline-formula> <tex-math>$text{P}_{mathrm {sat}}$ </tex-math></inline-formula>\u0000) of 24 dBm, and a peak power-added efficiency (PAE) over 24% from 24 to 38 GHz with a chip area of \u0000<inline-formula> <tex-math>$2times1$ </tex-math></inline-formula>\u0000 mm2. The broadband HPA demonstrates a 17-dB average small-signal gain, 29-dBm \u0000<inline-formula> <tex-math>$text{P}_{mathrm {sat}}$ </tex-math></inline-formula>\u0000, and a PAE over 28% from 24 to 32 GHz with a \u0000<inline-formula> <tex-math>$2.4times1.1$ </tex-math></inline-formula>\u0000 mm2 chip size. The measurement results have demonstrated the great potential of the proposed PA for 5G/6G millimeter-wave applications.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"111-121"},"PeriodicalIF":4.6,"publicationDate":"2024-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139949310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-16DOI: 10.1109/JETCAS.2024.3355011
Xin Zhang;Nengxu Zhu;Fanyi Meng
It is commonly practiced in millimeter-wave and terahertz cascode amplifiers to enhance the power gain by shorting the base-impedance in the common-base transistor. However, it is found that the merit of high output power is not achieved simultaneously under the zero base-impedance scenarios. This paper theoretically analyzes the optimum designs by varying the base-impedances for power gain and output power level enhancement. In addition, numerically results are given to prove that non-zero base-impedances are key parameters towards gain and output power enhancements. Thus, each stages of the power amplifier must contain different and optimized base-impedances, based on their power gain and output power targets. To validate the design theory, a 220 GHz power amplifier is designed and fabricated in a 0.13- $mu text{m}$ SiGe technology. The measurement reveals that the amplifier achieves operation bandwidth of 185 to 240 GHz, power gain of 25 dB, and output $P_{mathrm {1dB}}/P_{mathrm {SAT}}$ of 7.3/9.5 dBm. It consumes 310~324 mW dc power and occupies a core area of 0.09 mm2.
{"title":"A 185-to-240 GHz SiGe Power Amplifier Using Non-Zero Base-Impedances for Power Gain and Output Power Optimizations","authors":"Xin Zhang;Nengxu Zhu;Fanyi Meng","doi":"10.1109/JETCAS.2024.3355011","DOIUrl":"10.1109/JETCAS.2024.3355011","url":null,"abstract":"It is commonly practiced in millimeter-wave and terahertz cascode amplifiers to enhance the power gain by shorting the base-impedance in the common-base transistor. However, it is found that the merit of high output power is not achieved simultaneously under the zero base-impedance scenarios. This paper theoretically analyzes the optimum designs by varying the base-impedances for power gain and output power level enhancement. In addition, numerically results are given to prove that non-zero base-impedances are key parameters towards gain and output power enhancements. Thus, each stages of the power amplifier must contain different and optimized base-impedances, based on their power gain and output power targets. To validate the design theory, a 220 GHz power amplifier is designed and fabricated in a 0.13-\u0000<inline-formula> <tex-math>$mu text{m}$ </tex-math></inline-formula>\u0000 SiGe technology. The measurement reveals that the amplifier achieves operation bandwidth of 185 to 240 GHz, power gain of 25 dB, and output \u0000<inline-formula> <tex-math>$P_{mathrm {1dB}}/P_{mathrm {SAT}}$ </tex-math></inline-formula>\u0000 of 7.3/9.5 dBm. It consumes 310~324 mW dc power and occupies a core area of 0.09 mm2.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"67-74"},"PeriodicalIF":4.6,"publicationDate":"2024-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139949286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-16DOI: 10.1109/JETCAS.2024.3354778
Yutong Wang;Bo Li;Feng Lin;Houjun Sun;Hongjiang Wu;Chunliang Xu;Yuan Fang;Zhiqiang Li
This paper presents millimeter-wave (mmW) wide-band dual-function switching attenuator chips based on gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT). The broadband attenuator chips integrate the function of absorption single-pole-single-throw (SPST) switch by using balanced architecture. By analyzing the effects of transistor size and parasitic couplings from bias lines on mmW attenuator chips, the attenuation range is further improved. Based on the 90-nm GaAs pHEMT process, a 26~80 GHz attenuator chip I and a 40~110 GHz attenuator chip II were designed and measured, with chip sizes of $1.65ast 0.85$ mm2 and $1.30ast 0.80$ mm2, respectively. In the operating frequency band, the measured insertion losses (IL) of chips I and II are less than 2.8 dB and 2.2 dB, respectively, with the return losses (RL) of better than 12.4 dB and 11.6 dB. At the center frequency, the measured attenuation ranges of Chip I and II are $1.4sim 34.4$ dB and $1.1sim 30.9$ dB, respectively, and the 1dB compressed input power ( $IP_{mathrm {1dB}})$ of both chips are greater than 21 dBm. To the best of authors’ knowledge, this is the first wide-band mmW GaAs pHEMT attenuator chip integrated with absorption SPST switching function.
本文介绍了基于砷化镓（GaAs）拟态高电子迁移率晶体管（pHEMT）的毫米波（mmW）宽带双功能开关衰减器芯片。这种宽带衰减器芯片采用平衡式结构，集成了吸收式单刀单掷（SPST）开关的功能。通过分析晶体管尺寸和偏置线寄生耦合对毫米波衰减器芯片的影响，衰减范围得到了进一步改善。基于 90 纳米砷化镓 pHEMT 工艺，设计并测量了 26~80 GHz 衰减器芯片 I 和 40~110 GHz 衰减器芯片 II，芯片尺寸分别为 1.65/ast 0.85$ mm2 和 1.30/ast 0.80$ mm2。在工作频段，芯片 I 和芯片 II 测得的插入损耗（IL）分别小于 2.8 dB 和 2.2 dB，回波损耗（RL）分别优于 12.4 dB 和 11.6 dB。在中心频率，芯片 I 和芯片 II 的测量衰减范围分别为 1.4/sim 34.4$ dB 和 1.1/sim 30.9$ dB，两个芯片的 1dB 压缩输入功率 ( $IP_{mathrm {1dB}})$ 均大于 21 dBm。据作者所知，这是第一款集成了吸收 SPST 开关功能的宽带毫米波砷化镓 pHEMT 衰减器芯片。
{"title":"Broadband Millimeter-Wave GaAs Dual-Function Switching Attenuators With Low Insertion Loss and Large Attenuation Range","authors":"Yutong Wang;Bo Li;Feng Lin;Houjun Sun;Hongjiang Wu;Chunliang Xu;Yuan Fang;Zhiqiang Li","doi":"10.1109/JETCAS.2024.3354778","DOIUrl":"10.1109/JETCAS.2024.3354778","url":null,"abstract":"This paper presents millimeter-wave (mmW) wide-band dual-function switching attenuator chips based on gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT). The broadband attenuator chips integrate the function of absorption single-pole-single-throw (SPST) switch by using balanced architecture. By analyzing the effects of transistor size and parasitic couplings from bias lines on mmW attenuator chips, the attenuation range is further improved. Based on the 90-nm GaAs pHEMT process, a 26~80 GHz attenuator chip I and a 40~110 GHz attenuator chip II were designed and measured, with chip sizes of \u0000<inline-formula> <tex-math>$1.65ast 0.85$ </tex-math></inline-formula>\u0000mm2 and \u0000<inline-formula> <tex-math>$1.30ast 0.80$ </tex-math></inline-formula>\u0000mm2, respectively. In the operating frequency band, the measured insertion losses (IL) of chips I and II are less than 2.8 dB and 2.2 dB, respectively, with the return losses (RL) of better than 12.4 dB and 11.6 dB. At the center frequency, the measured attenuation ranges of Chip I and II are \u0000<inline-formula> <tex-math>$1.4sim 34.4$ </tex-math></inline-formula>\u0000 dB and \u0000<inline-formula> <tex-math>$1.1sim 30.9$ </tex-math></inline-formula>\u0000 dB, respectively, and the 1dB compressed input power (\u0000<inline-formula> <tex-math>$IP_{mathrm {1dB}})$ </tex-math></inline-formula>\u0000 of both chips are greater than 21 dBm. To the best of authors’ knowledge, this is the first wide-band mmW GaAs pHEMT attenuator chip integrated with absorption SPST switching function.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"100-110"},"PeriodicalIF":4.6,"publicationDate":"2024-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139949312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-15DOI: 10.1109/JETCAS.2024.3354503
Ge Bai;Zhijiang Dai;Jingsong Wang;Cheng Bi;Weimin Shi;Jingzhou Pang;Mingyu Li
This paper proposes a Doherty power amplifier (DPA) architecture with potential for wideband and high efficiency, denoted as single-loop load matching network DPA (SL-LMN). The conventional single combination node network is replaced by an SL-LMN, which adds a new current combination node. This architecture can bring new circuit design freedom, which expands the operating bandwidth of the load modulation network. Using the same prototype topology, the working mechanism of SL-LMN DPA is further illustrated based on three sets of comparative designs. To prove this theory, a broadband asymmetric DPA (ADPA) functioning over 1.9-2.9 GHz is developed and fabricated using two asymmetric GaN transistors. Under continuous wave excitation, the observed data indicates that the drain efficiency of this ADPA is 42.1%-68.9% at saturation and 45.5%-58.5% at 8 dB back-off, respectively. The ADPA has a maximum output power and saturated gain of 44–46 dBm and 6.8-10.9 dB, respectively.
{"title":"Design of Broadband Doherty Power Amplifier Based on Single Loop Load Modulation Network","authors":"Ge Bai;Zhijiang Dai;Jingsong Wang;Cheng Bi;Weimin Shi;Jingzhou Pang;Mingyu Li","doi":"10.1109/JETCAS.2024.3354503","DOIUrl":"10.1109/JETCAS.2024.3354503","url":null,"abstract":"This paper proposes a Doherty power amplifier (DPA) architecture with potential for wideband and high efficiency, denoted as single-loop load matching network DPA (SL-LMN). The conventional single combination node network is replaced by an SL-LMN, which adds a new current combination node. This architecture can bring new circuit design freedom, which expands the operating bandwidth of the load modulation network. Using the same prototype topology, the working mechanism of SL-LMN DPA is further illustrated based on three sets of comparative designs. To prove this theory, a broadband asymmetric DPA (ADPA) functioning over 1.9-2.9 GHz is developed and fabricated using two asymmetric GaN transistors. Under continuous wave excitation, the observed data indicates that the drain efficiency of this ADPA is 42.1%-68.9% at saturation and 45.5%-58.5% at 8 dB back-off, respectively. The ADPA has a maximum output power and saturated gain of 44–46 dBm and 6.8-10.9 dB, respectively.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"122-132"},"PeriodicalIF":4.6,"publicationDate":"2024-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139949447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-08DOI: 10.1109/JETCAS.2024.3351075
Lang Chen;Lisheng Chen;Depeng Sun;Yichuang Sun;Yulin Pan;Xi Zhu
The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical load-modulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non- $50~Omega $ load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the S-LMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power ( $text{P}_{mathrm {sat}}$ ) with a maximum power-added efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVM $_{mathrm {rms}}$ ) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadrature-amplitude-modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.
{"title":"A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off","authors":"Lang Chen;Lisheng Chen;Depeng Sun;Yichuang Sun;Yulin Pan;Xi Zhu","doi":"10.1109/JETCAS.2024.3351075","DOIUrl":"10.1109/JETCAS.2024.3351075","url":null,"abstract":"The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical load-modulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-\u0000<inline-formula> <tex-math>$50~Omega $ </tex-math></inline-formula>\u0000 load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the S-LMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (\u0000<inline-formula> <tex-math>$text{P}_{mathrm {sat}}$ </tex-math></inline-formula>\u0000) with a maximum power-added efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVM\u0000<inline-formula> <tex-math>$_{mathrm {rms}}$ </tex-math></inline-formula>\u0000) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadrature-amplitude-modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"14 1","pages":"88-99"},"PeriodicalIF":4.6,"publicationDate":"2024-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139949280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/JETCAS.2023.3343932
Jason K. Eshraghian;Arindam Basu;Corey Lammie;Shih-Chii Liu;Priydarshini Panda
This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on dynamical neuro-artificial intelligence (AI) learning systems that bridge the gap between devices, circuits, architectures, and algorithms. The growing demand for AI has spurred the development of systems that: 1) co-localize computation and memory; 2) enhance circuits and devices optimized for operations prevalent in deep learning; and 3) implement lightweight and compressed machine learning models thereby achieving greater accuracy with less resources.
{"title":"Guest Editorial Dynamical Neuro-AI Learning Systems: Devices, Circuits, Architecture and Algorithms","authors":"Jason K. Eshraghian;Arindam Basu;Corey Lammie;Shih-Chii Liu;Priydarshini Panda","doi":"10.1109/JETCAS.2023.3343932","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3343932","url":null,"abstract":"This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on dynamical neuro-artificial intelligence (AI) learning systems that bridge the gap between devices, circuits, architectures, and algorithms. The growing demand for AI has spurred the development of systems that: 1) co-localize computation and memory; 2) enhance circuits and devices optimized for operations prevalent in deep learning; and 3) implement lightweight and compressed machine learning models thereby achieving greater accuracy with less resources.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"873-876"},"PeriodicalIF":4.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375873","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/JETCAS.2023.3340568
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/JETCAS.2023.3340568","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3340568","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"C3-C3"},"PeriodicalIF":4.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375870","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/JETCAS.2023.3340572
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information","authors":"","doi":"10.1109/JETCAS.2023.3340572","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3340572","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"C2-C2"},"PeriodicalIF":4.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375872","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/JETCAS.2023.3340570
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors","authors":"","doi":"10.1109/JETCAS.2023.3340570","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3340570","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"1148-1148"},"PeriodicalIF":4.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375871","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/JETCAS.2023.3345229
{"title":"TechRxiv: Share Your Preprint Research with the World!","authors":"","doi":"10.1109/JETCAS.2023.3345229","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3345229","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"13 4","pages":"1147-1147"},"PeriodicalIF":4.6,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375845","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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