Pub Date : 2024-06-20DOI: 10.1109/mdat.2024.3393829
Scott Davidson
Many who have worked for vertically integrated companies making both ICs and computer equipment have experience in tracking ICs in the field. This is the subject of this issue of IEEE Design&Test on Silicon Lifecycle Management. If your company dealt with high-end equipment, where every failure mattered, you could close the loop on IC quality and see the failure rate of parts in use.
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Pub Date : 2024-06-20DOI: 10.1109/mdat.2024.3405059
{"title":"TechRxiv: Share Your Preprint Research With the World!","authors":"","doi":"10.1109/mdat.2024.3405059","DOIUrl":"https://doi.org/10.1109/mdat.2024.3405059","url":null,"abstract":"","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"19 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141507569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/mdat.2024.3392620
Mehdi Tahoori, Yervant Zorian
The Semiconductor Industry faces mounting challenges with the rapid advancement of device and system complexity. While increased transistor densities and smaller feature sizes present opportunities for enhanced capabilities, they also bring about significant hurdles such as heightened manufacturing variability and sensitivity to runtime and workload effects. Moreover, higher design densities result in elevated current and power densities, necessitating solutions for maintaining voltage supply levels and managing heat dissipation. Complicated factors like chip placement, system arrangements, and hardware–software interactions further elevate the risk of physical failure, making it challenging to model, mitigate, or identify issues during the design, manufacturing, and testing phases.
{"title":"Special Issue on Silicon Lifecycle Management","authors":"Mehdi Tahoori, Yervant Zorian","doi":"10.1109/mdat.2024.3392620","DOIUrl":"https://doi.org/10.1109/mdat.2024.3392620","url":null,"abstract":"The Semiconductor Industry faces mounting challenges with the rapid advancement of device and system complexity. While increased transistor densities and smaller feature sizes present opportunities for enhanced capabilities, they also bring about significant hurdles such as heightened manufacturing variability and sensitivity to runtime and workload effects. Moreover, higher design densities result in elevated current and power densities, necessitating solutions for maintaining voltage supply levels and managing heat dissipation. Complicated factors like chip placement, system arrangements, and hardware–software interactions further elevate the risk of physical failure, making it challenging to model, mitigate, or identify issues during the design, manufacturing, and testing phases.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"59 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141507572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/mdat.2024.3393834
Partha Pratim Pande
The focus of this issue is the special issue on the broad topic of silicon lifecycle management (SLM). Additionally, we have the interview with Janusz Rajski, who is the vice president of engineering at Siemens Tessent Wilsonville, Wilsonville, OR, USA.
本期的重点是关于硅生命周期管理 (SLM) 这一广泛主题的特刊。此外，我们还采访了 Janusz Rajski，他是美国俄勒冈州威尔逊维尔市西门子泰森特威尔逊维尔公司的工程副总裁。
{"title":"Silicon Lifecycle Management","authors":"Partha Pratim Pande","doi":"10.1109/mdat.2024.3393834","DOIUrl":"https://doi.org/10.1109/mdat.2024.3393834","url":null,"abstract":"<fig orientation=\"portrait\" position=\"float\" xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"> <graphic orientation=\"portrait\" position=\"float\" xlink:href=\"pande-3393834.tif\"/> </fig>\u0000The focus of this issue is the special issue on the broad topic of silicon lifecycle management (SLM). Additionally, we have the interview with Janusz Rajski, who is the vice president of engineering at Siemens Tessent Wilsonville, Wilsonville, OR, USA.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"1 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141507571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-20DOI: 10.1109/mdat.2024.3386106
Nicola Nicolici
Nicola Nicolici: Good evening and I would like to welcome Janusz Rajski, a Life Fellow of IEEE, who received the Ph.D. degree in electrical engineering from Poznan textasciiacute University of Technology, Poland, in 1982. He is currently the vice president of engineering at Siemens Tessent Wilsonville, Wilsonville, OR, USA. During his tenure at Siemens, he has built a strong international research and development organization with a focus on innovative DFT technologies. His team has developed several revolutionary products widely adopted by the semiconductor industry: TestKompress, cell-aware test, and streaming scan networks. He has published 300 IEEE research papers and is a co-inventor of 130 U.S. and international patents. His papers won prestigious awards, including two best paper awards published in IEEE Transactions on CAD, one on logic synthesis and another on test compression. In 2009, Janusz received the Stephen Swerling Innovation Award from Mentor Graphics for his breakthrough innovation TestKompress and revitalizing Mentor’s DFT business to its current position as the number one test business in EDA. In 2018, he received the Siemens Inventor of the Year Lifetime Achievement Award for his extensive contributions to DFT. In 2023, he received the prestigious Bob Madge Innovation Award. Welcome, Janusz.
{"title":"Interview With Janusz Rajski","authors":"Nicola Nicolici","doi":"10.1109/mdat.2024.3386106","DOIUrl":"https://doi.org/10.1109/mdat.2024.3386106","url":null,"abstract":"Nicola Nicolici: Good evening and I would like to welcome Janusz Rajski, a Life Fellow of IEEE, who received the Ph.D. degree in electrical engineering from Poznan textasciiacute University of Technology, Poland, in 1982. He is currently the vice president of engineering at Siemens Tessent Wilsonville, Wilsonville, OR, USA. During his tenure at Siemens, he has built a strong international research and development organization with a focus on innovative DFT technologies. His team has developed several revolutionary products widely adopted by the semiconductor industry: TestKompress, cell-aware test, and streaming scan networks. He has published 300 IEEE research papers and is a co-inventor of 130 U.S. and international patents. His papers won prestigious awards, including two best paper awards published in IEEE Transactions on CAD, one on logic synthesis and another on test compression. In 2009, Janusz received the Stephen Swerling Innovation Award from Mentor Graphics for his breakthrough innovation TestKompress and revitalizing Mentor’s DFT business to its current position as the number one test business in EDA. In 2018, he received the Siemens Inventor of the Year Lifetime Achievement Award for his extensive contributions to DFT. In 2023, he received the prestigious Bob Madge Innovation Award. Welcome, Janusz.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"162 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141507573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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