Pub Date : 2023-10-01DOI: 10.1109/MDAT.2023.3286335
M. Corrêa, D. Palomino, G. Corrêa, L. Agostini
This article presents a fast mode decision scheme and a mode-adaptive subsampling algorithm to accelerate AV1 encoding.
本文提出了一种快速模式决策方案和一种模式自适应子采样算法来加速AV1编码。
{"title":"Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction","authors":"M. Corrêa, D. Palomino, G. Corrêa, L. Agostini","doi":"10.1109/MDAT.2023.3286335","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3286335","url":null,"abstract":"This article presents a fast mode decision scheme and a mode-adaptive subsampling algorithm to accelerate AV1 encoding.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"26-33"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62453903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/MDAT.2023.3277813
R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes
This article presents a method for the secure execution of applications on MPSoCs by adopting spatial isolation of applications and a secure communication mechanism with peripherals.
{"title":"SeMAP—A Method to Secure the Communication in NoC-Based Many-Cores","authors":"R. Faccenda, Gustavo Comarú, L. L. Caimi, F. Moraes","doi":"10.1109/MDAT.2023.3277813","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3277813","url":null,"abstract":"This article presents a method for the secure execution of applications on MPSoCs by adopting spatial isolation of applications and a secure communication mechanism with peripherals.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"42-51"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45724358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/MDAT.2023.3261799
Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen
Multisite testing, where multiple ICs are tested in parallel sharing the same automatic test equipment, is a widely used method today in IC high-volume test facilities. This article provides a survey of best practices to deal with the problem of site-to-site variation, specifically in the case of analog and mixed-signal ICs.
{"title":"Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction","authors":"Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, S. Ravi, Degang Chen","doi":"10.1109/MDAT.2023.3261799","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3261799","url":null,"abstract":"Multisite testing, where multiple ICs are tested in parallel sharing the same automatic test equipment, is a widely used method today in IC high-volume test facilities. This article provides a survey of best practices to deal with the problem of site-to-site variation, specifically in the case of analog and mixed-signal ICs.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"52-61"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46096965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1109/MDAT.2023.3270234
Md Sami Ul Islam Sami, H. M. Kamali, Farimah Farahmandi, Fahim Rahman, M. Tehranipoor
Due to slowdown of Moore’s law and Dennard scaling, modern hardware design has shifted to heterogenous integration (HI) instead of traditional monolithic ICs. However, HI incurs its own security vulnerabilities. In this article, the authors analyze the security issues pertaining to HI and provide defense strategies for the same.
{"title":"Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations","authors":"Md Sami Ul Islam Sami, H. M. Kamali, Farimah Farahmandi, Fahim Rahman, M. Tehranipoor","doi":"10.1109/MDAT.2023.3270234","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3270234","url":null,"abstract":"Due to slowdown of Moore’s law and Dennard scaling, modern hardware design has shifted to heterogenous integration (HI) instead of traditional monolithic ICs. However, HI incurs its own security vulnerabilities. In this article, the authors analyze the security issues pertaining to HI and provide defense strategies for the same.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"86-95"},"PeriodicalIF":2.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42717387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-25DOI: 10.1109/mdat.2023.3306719
Kamil Khan, Sudeep Pasricha
In this article, the authors introduce a regional congestion-aware reinforcement learning (RL)-based routing policy for Network-on-Chip (NoC) architectures.
在本文中，作者介绍了一种基于区域拥塞感知强化学习(RL)的片上网络(NoC)架构路由策略。
{"title":"A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip","authors":"Kamil Khan, Sudeep Pasricha","doi":"10.1109/mdat.2023.3306719","DOIUrl":"https://doi.org/10.1109/mdat.2023.3306719","url":null,"abstract":"In this article, the authors introduce a regional congestion-aware reinforcement learning (RL)-based routing policy for Network-on-Chip (NoC) architectures.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"21 1","pages":""},"PeriodicalIF":2.0,"publicationDate":"2023-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138520570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-01DOI: 10.1109/MDAT.2023.3237942
Boris Oróstica, Isaac Núñez, Tamara Matúte, Felipe Núñez, Fernán Federici
This article introduces an open-source thermal cycling machine designed specifically for Golden Gate DNA assembly. The prototype device can achieve efficiency similar to a commercial PCR thermocycler.
{"title":"Building an Open-Source DNA Assembler Device","authors":"Boris Oróstica, Isaac Núñez, Tamara Matúte, Felipe Núñez, Fernán Federici","doi":"10.1109/MDAT.2023.3237942","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3237942","url":null,"abstract":"This article introduces an open-source thermal cycling machine designed specifically for Golden Gate DNA assembly. The prototype device can achieve efficiency similar to a commercial PCR thermocycler.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"69-77"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47833580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.
{"title":"Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O","authors":"A. Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal","doi":"10.1109/MDAT.2023.3269389","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3269389","url":null,"abstract":"This article discusses the method of using the functional protocol of an existing high-speed I/O port for testing. This method enables reduced GPIO pin requirement during manufacturing test and running full structural content while embedded in a functioning system. Frequency of on-chip scan networks can be increased as it is no longer limited by pin timing bottlenecks of regular, slow-speed I/Os. The same HSAT-based test infrastructure can be used for enabling system-level and in-system test for monitoring throughout the lifecycle of the chip.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"17-24"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41883224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-01DOI: 10.1109/MDAT.2023.3270126
Soyed Tuhin Ahmed, M. Tahoori
This article focuses on recalibration of neural networks implemented in neuromorphic in-memory computing with memristors. The primary goal of the article is to reduce the amount of data required for recalibration which makes it particularly useful in scenarios where data availability is limited or where recalibration overhead is a concern. Moreover, the proposed approach is robust against both process and temperature variations at a significantly lower overhead compared to related works. This practical method addresses an important issue that can affect the accuracy of neural networks implemented using emerging resistive nonvolatile memories.
{"title":"Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration","authors":"Soyed Tuhin Ahmed, M. Tahoori","doi":"10.1109/MDAT.2023.3270126","DOIUrl":"https://doi.org/10.1109/MDAT.2023.3270126","url":null,"abstract":"This article focuses on recalibration of neural networks implemented in neuromorphic in-memory computing with memristors. The primary goal of the article is to reduce the amount of data required for recalibration which makes it particularly useful in scenarios where data availability is limited or where recalibration overhead is a concern. Moreover, the proposed approach is robust against both process and temperature variations at a significantly lower overhead compared to related works. This practical method addresses an important issue that can affect the accuracy of neural networks implemented using emerging resistive nonvolatile memories.","PeriodicalId":48917,"journal":{"name":"IEEE Design & Test","volume":"40 1","pages":"42-50"},"PeriodicalIF":2.0,"publicationDate":"2023-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42709978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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