Iet Circuits Devices & Systems最新文献

This paper presents a new method for direct sampling of the backscattered signal in ultrawideband (UWB) impulse radar for vital sign detection. One of the standard methods for direct sampling in UWB radars is the time-interleaving technique. In these converters, NOT gates (logical inverter gates) and tunable delay cells are typically used to create time delays and generate delayed replicas of the sampling clock. However, the challenge arises from the nonuniform delay associated with these gates and dependency on the process, voltage, and temperature (PVT), which affects the converter spurious-free dynamic range (SFDR). This paper employs a new structure using a ring counter to overcome this issue. As a result, a stable and PVT-independent sampling clock is obtained without significant overhead, compared to the conventional inverter-based delay cells approach. The proposed flip-flop-based ring counter architecture eliminates the need for analog delay tuning, offering a fully digital, PVT-resilient solution for uniform sampling in high-speed radar systems. The proposed structure has been utilized to design a 12-channel, six-bit time-interleaved swept-threshold analog to digital converter (ADC). The ADC has been in 65 nm complementary metal-oxide-semiconductor (CMOS) technology and simulated using the foundry design kit. Postlayout simulation results demonstrate a total power consumption of 28.54 mW with a 16.66 GS/s sampling rate.

The carry select adder (CSA) is a highly efficient arithmetic component commonly utilized in digital systems due to its superior speed performance. In the context of energy-efficient computing and fault-tolerant quantum computing, reversible logic emerges as a critical technology owing to its potential to reduce energy dissipation by retaining information. This article introduces an efficient design for a reversible carry select adder (ERCSA), constructed using fundamental lossless logic gates such as modified TSG (MTSG), Peres, and Fredkin Gate (FRG). The proposed design eliminates the need to compute the carry for the default carry input of “1.” Additionally, an optimized architecture is proposed to reduce the quantum cost of the circuit. The design achieves significant improvements by minimizing quantum cost, unused outputs, and gate count, while ensuring scalability for higher bit-width additions. A comparative analysis with existing reversible adder highlights substantial performance enhancements, including reduction in the number of gates (35.4%), garbage outputs (18.9%), ancillary inputs (25%), quantum cost (22.7%), and delay (29.5%) compared to recent designs. The proposed architecture was modeled in Verilog and synthesized using Xilinx Vivado Design Suite targeting the Xilinx Artix-7 FPGA family. The proposed 16-bit ERCA architecture achieves 10.86% lower power, 76.43% reduced delay, and 21.7% better area efficiency compared to existing methods. These improvements make it highly suitable for low-power and high-speed VLSI applications.

This article proposes a new high step-down converter which, on the input side, there are two series switches. The coupled inductors are used to decrease voltage gain, but on the output side of the proposed converter, two independent inductances are placed and act like interleaved, which cause to decrease output current ripple. Soft switching condition is provided for all semiconductors in the proposed converter. As described, considering the structure of the proposed converter, the converter has two switches, which is the minimum switch used in this structure. Also, the switches do not impose complexity to the converter in terms of control, because these switches are controlled complementary each other. In the structure of the proposed converter, the minimum semiconductor elements are used, which include two switches and three diodes; this design makes the conduction loss of the proposed converter low and achieves higher efficiency. A sample laboratory of the proposed converter is implemented to verify theoretical analysis, which the experimental results are presented in 300 W power with 320 V input voltage and 24 V output voltage. In this test, an efficiency of about 94.6% is achieved.

This study examines the influence of cell capacitance on data retention characteristics in dynamic random access memory (DRAM) cells composed of two transistors, in short, 2-transistor (2T) DRAM. The 2T DRAM is gaining attention not only as a standalone memory technology but also as a critical component for processing-in-memory (PIM) applications, offering the full compatibility with standard Si processing. The 2T configuration employs separate transistors for write and read operations, enabling flexible bit-cell design and efficient parallel processing in PIM architectures. However, the small storage node (SN) capacitance, especially when the cell capacitor is truncated, poses challenges for data retention. This work presents a design methodology to enhance data retention in 2T DRAM cells by optimizing transistor dimensions and biasing schemes. Circuit simulations using the 180 nm standard process show that the proposed approach improves retention time by 35% and reduces leakage current by 22% compared to baseline designs. Furthermore, the write transistor current demonstrates a 15% improvement in stability during repeated read operations within the retention time. These results highlight the potential of the proposed design to mitigate retention-related issues and enhance computational accuracy in PIM applications.

This article introduces a multiresponse image fusion method tailored for a high dynamic range (HDR) CMOS image sensor (CIS), which combines dual conversion gain (DCG) and logarithmic responses within a single exposure. Utilizing the imaging characteristics of the sensor together with a proposed quality perceptive strategy, the presented fusion method achieves a light-weight multiresponse fusion stage, which selects the optimal response of the pixels under different illumination from the captured images. The fused image is of better quality compared to a linear combination of weighted images. Moreover, the proposed multiresponse image fusion method can eventually acquire HDR image in real-time.

The coexistence of nonvolatile and volatile switching characteristics in ZnO-based conducting bridge random access memory (CBRAM) devices and the feasibility of the cycle-to-cycle fluctuation of both characteristics for data storage and random number generator (RNG) applications are investigated. The insertion of a 6-nm-thick Ti barrier layer between the Ag top electrode (TE) and the ZnO switching layer improves the switching stability and the memory window up to five orders of magnitude. The employment of current compliance (CC) of 1 mA leads to a permanent LRS; meanwhile, CC lower than 100 uA exhibits volatile switching characteristics. Although the lower CC operations might not be applicable for data storage applications, their switching fluctuations can be used as inputs for generating random bitstreams. An RNG circuit design is proposed, and the randomness of the bitstreams is evaluated using the NIST randomness test suite. The volatile switching induced by the lower CC tends to produce bitstreams with a better randomicity than the nonvolatile one, where the resistance state of the device operated with a CC of 10 uA is able to generate 1600 bits that pass seven out of seven NIST tests. We conduct statistical analysis to shed light on the relationship between the resistance states and the quality of the produced random bitstream. In contrast to popular opinion, the coefficient of variation might not be the best method to quantify the fluctuation of the resistance state in our case. Therefore, we propose the switching fluctuation factor (FF) to determine the threshold value of the resistance state that can produce a sufficient random bitstream; it is found that our RNG circuit requires a threshold FF of 96% to produce a bitstream that passes at least four out of seven tests. This work not only proposes a solution to enhance the switching stability for data storage applications but also provides insight into the exploitation of switching instability for RNG applications, where a single device can be programmed to have both capabilities, rendering programmable and multifunctional electronics.

In this article, we present a lead-free hybrid-halide perovskite solar cell (PSC) using guanidinium (GA)-formamidinium tin iodide (GA_0.05FA_0.93SnI₃) as the absorber layer (AL), the performance metrics analyses on the light of short-circuit current (I_sc), power conversion efficiency (PCE), open circuit voltage (V_oc), and fill-factor (FF). Utilizing the SCAPS-1D numerical program, we have optimized the material and device parameters, including thickness of AL, electron affinity, defect density, doping concentration, and series and shunt resistances. The GA_0.05FA_0.93SnI₃ AL exhibits highly stable and nontoxic in nature. The proposed hybrid halide-based PSC achieved an enhanced PCE (27.55%) in comparison with reported cutting-edge PSCs, under the AM1.5G spectrum.

In the field of hardware accelerators for convolutional neural network (CNN) inference, quantization techniques have been widely employed to enhance the performance. The prevailing quantization scheme of the accelerator at present is using signed 8-bit integer variables (INT8). CNN accelerators support INT8, while lower precision INT4 is less common. Accelerators supporting INT4 depthwise separable convolution (DWC) are even rarer. Therefore, this article presents a high-performance CNN accelerator that not only supports 8-bit and 4-bit data but also supports standard convolution (SC) and DWC. Additionally, in order to improve the transmission efficiency of DWC, an intermediate cache strategy is proposed, using a pointwise convolution (PW) input buffer (PW BUF) to store output data from depthwise convolution (DW) to avoid off-chip transmission. Furthermore, to address the issue of a DSP cannot perform two 4 × 4-bit multiplications when dealing with DW, a processing element (PE) is designed to make full use of DSP hardware resources. Finally, this accelerator is implemented on ZYNQ ZC706 with a frequency of 200 MHz. Experimental results show that it achieves a performance up to 307.88 giga operations per second (GOPS) on VGG, reaching 97.9% peak performance; while on MobileNet, it achieves efficient performance with 206.43 GOPS with only 392 DSPs. Compared with mainstream CNN accelerators, it increases DSP utilization rate (GOPS/DSP) by 1.5× to 33.5×.

Physically unclonable function-based authentication is one of the widely accepted and promising hardware security primitives. For security applications, strong PUF circuits can generate a large number of challenge–response pairs (CRPs) for authentication. These CRPs can, however, be utilised by machine learning (ML) techniques to model the physically unclonable function (PUF) and forecast its responses. In this paper, we evaluate the robustness of analog PUF designs, specifically hybrid current mirror inverter (HCMI) and diode triode current mirror inverter (DTCMI) PUFs, against ML attacks. The XOR-tree configuration in the PUF amplifies entropy and introduces additional nonlinearity, making the CRP mapping significantly harder to model. Deep neural networks (DNNs) attack and the PyPUF toolbox were utilised to evaluate the modelling attacks on the HCMI and DTCMI PUFs. Experiments were conducted using CRP counts ranging from 10,000 to 1,000,000. Despite varying the number of hidden layers and nodes in the DNN model, the attack accuracy consistently remained near 50%, indicating the robustness of analog PUFs to ML-based modelling techniques. The evaluation using the PyPUF toolbox also resulted in consistent accuracy near 50%, indicating poor learnability. The results highlight the strong resistance of XOR-tree-enhanced HCMI and DTCMI analog PUF designs to advanced machine-learning attacks compared to the vulnerabilities of conventional digital PUFs.

This paper presents an enhanced linear pulse-frequency modulator (LPFM) ion-sensitive field-effect transistor (ISFET) architecture with a programmable dynamic range for pH detection. The circuit encodes the pH signal into the frequency domain. This proposed method is shown to have higher stability for supply variation. A dynamic referencing scheme is used to increase the stability of the recording over long periods. The circuit’s operating point and dynamic range can be programmed, enhancing the versatility of the architecture. The design was implemented in a 0.18 µm standard CMOS process, with a sensing area as an extended gate electrode of 125 µm × 125 µm. The architecture was electrically and electrochemically characterised. The ISFET chip was post-processed by thinning the passivation layer over the sensing area. The results showed a boost in the sensitivity of 230%, an increase of 9% in the passivation capacitance with an intact SiO2 layer, and a 45% reduction of the Si3N4 layer. Compared to a rapid decay in signal quality, the dynamic reference method showed consistent measurements over hours. The circuit also showed very low sensitivity for around 25% supply variation.