Iet Circuits Devices & Systems最新文献

英文中文

System for PCB Defect Detection Using Visual Computing and Deep Learning for Production Optimization 基于视觉计算和深度学习的PCB缺陷检测系统

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-11-03 DOI: 10.1049/2023/6681526

Gabriel Gomes de Oliveira, Gabriel Caumo Vaz, Marcos Antonio Andrade, Yuzo Iano, Leandro Ronchini Ximenes, Rangel Arthur

With the growing competition between the various manufacturers of electronic products, the quality of the products developed and the consequent confidence in the brand are fundamental factors for the survival of companies. To guarantee the quality of the products in the manufacturing process, it is crucial to identify defects during the production stage of an electronic device. This study presents a system based on traditional visual computing and new deep learning methods to detect defects in electronic devices during the manufacturing process. A prototype of the proposed system was developed and manufactured for direct use in the production line of electronic devices. Tests were performed using a particular smartphone model that had 22 critical components to inspect and the results showed that the proposed system achieved an average accuracy of more than 90% in defect detection when it was directly used in the operational production line. Other studies in this field perform measurements in controlled laboratory environments and identify fewer critical components. Therefore, the proposed method is a real-time high-performance system. Furthermore, the proposed system conforms with the Industry 4.0 goal that process system digitization is essential to improve indicators and optimize production.

随着各电子产品制造商之间的竞争日益激烈，所开发产品的质量以及由此产生的对品牌的信心是公司生存的根本因素。为了保证产品在制造过程中的质量，在电子设备的生产阶段对缺陷进行识别是至关重要的。本文提出了一种基于传统视觉计算和新型深度学习方法的电子器件制造过程缺陷检测系统。所提出的系统的原型被开发和制造，直接用于电子设备的生产线。使用特定的智能手机模型进行测试，该模型有22个关键部件需要检查，结果表明，当该系统直接用于运营生产线时，缺陷检测的平均准确率超过90%。该领域的其他研究在受控的实验室环境中进行测量，并确定较少的关键成分。因此，所提出的方法是一个实时的高性能系统。此外，所提出的系统符合工业4.0的目标，即过程系统数字化是提高指标和优化生产的关键。

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引用次数: 0

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit 一种基于7nm的5R4W高时序可靠性调档电路

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-31 DOI: 10.1049/2023/1548352

Wanlong Zhao, Yuejun Zhang, Liang Wen, Pengjun Wang

Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

寄存器文件(Regfile)作为处理器数据交互的瓶颈电路，直接决定了系统的计算性能。为了解决寄存器堆的读写冲突和时序错误问题，本文提出了一种5R4W高时序可靠性的Regfile电路设计方案。首先，该方案分析了Regfile电路中读写冲突、写错误和读错误等时序错误的原理;然后采用时钟双边独立控制读写过程的时序分离方法解决多端口读写冲突，设计镜像存储器校验电路避免字行延时导致的写入错误，采用锁相时钟反馈结构消除数据时序波动导致的读取错误;在台积电7nm FinFET工艺中，采用完全定制的布局实现了64 × 74位5R4W Regfile电路。实验结果表明，Regfile电路的面积为0.13 mm2，功耗为5.541 mW。该电路在−40 ~−125℃、0.75 V工作时的最大工作频率为3.8 GHz，能够检测时钟抖动超过30ps或频率高于5ghz所导致的写错误。

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引用次数: 0

The Design and Process Reliability Analysis of Millimeter Wave CMOS Power Amplifier with a Cold Mode MOSFET Linearization 冷模MOSFET线性化毫米波CMOS功率放大器设计及工艺可靠性分析

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-31 DOI: 10.1049/2023/2265697

N. A. Quadir, Amit Jain, S. Kashfi, Lutfi Albasha, Nasser Qaddoumi

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

本文介绍了一种用于通信应用的28ghz功率放大器的设计。采用模拟预失真技术，利用冷模MOSFET线性化器改善线性度。该电路的输出峰值功率为+19.8 dBm，功率附加效率(PAE)为17%。1db压缩点线性度为+18.6 dBm。对802_11n_40M、CDMA、IS-95和802_11n_20M等不同通信标准进行了相邻信道功率比(ACPR)仿真。分析了放大器在五个工艺角上的设计规范变化，并进行了仿真，以验证所设计电路的符合标准和鲁棒性。通过蒙特卡罗模拟来评估PAE和功率增益的统计变异性的性能。据信，这种线性化设计和所使用的验证是首次在65纳米RFCMOS工艺上完成的。

引用次数: 0

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device 一种改善LDMOS器件电学特性的Mini-LOCOS场板廓形工艺优化方法

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-31 DOI: 10.1049/2023/5298361

Shaoxin Yu, Weiheng Shao, Pei-Xiong Gao, Xiang Li, Rongsheng Chen, Bin Zhao

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

本文通过计算机辅助设计模拟技术，分析了硅微局部氧化(LOCOS)场极板底部物理剖面对器件击穿性能的影响。指出“突兀”的底部轮廓肯定可以进行优化。本文介绍了一种有效的工艺改进方法，即蚀刻偏压功率调整和时间缩短。通过透射电镜的截面分析，证明了场板物理剖面的改进。mini-LOCOS场板θ2底表面角度由11.9°提高到12.6°，上、底场板氧化层厚度Hup/Hbottom比由71.8%提高到76.6%。最后，制作了优化后的横向扩散金属氧化物半导体器件，并测量了性能曲线和安全操作面积曲线。比导通电阻Ron,sp可低至11.3 mΩ mm2，击穿电压BVds,max可达37.4 V，提高近19.3%。

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引用次数: 0

Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator 利用TCAD模拟器设计基于硅反馈场效应管的二、三元逻辑逆变器

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-23 DOI: 10.1049/2023/8833764

Ashkan Horri

A feedback field effect transistor (FBFET) with p-n-p-n structure benefits from a positive feedback mechanism. In this structure, the accumulated charges in its potential well and limitation of carrier flow by its internal potential barrier lead to superior electrical properties such as lower subthreshold swing (SS) and higher

I_{ON} / I_{OFF}

ratio in comparison with FinFET. Thus, FBFET is a promising alternative for digital applications such as logic inverters. In this paper, binary and ternary logic inverters are designed by using FBFETs with 40 nm channel length. The doping profile in the device plays an essential role and specifies the binary or ternary operation of the inverter. The inverter is analyzed by using a TCAD mixed-mode simulator. The results indicate the high value of 1010 for

I_{ON} / I_{OFF}

ratio with an extremely low SS (1 mV/decade). The voltage transfer characteristics of the inverter and its dependence on doping levels have been investigated. Also, the electrical properties of this inverter are compared with previous inverter counterparts.

具有p-n-p-n结构的反馈场效应晶体管(FBFET)得益于正反馈机制。在这种结构中，与FinFET相比，电势阱中的累积电荷和内部势垒对载流子流动的限制导致了更优越的电学性能，例如更低的亚阈值摆幅(SS)和更高的I ON / I OFF比。因此，fbet是一种很有前途的数字应用替代方案，如逻辑逆变器。本文采用40 nm通道长度的fbfet设计了二、三元逻辑逆变器。器件中的掺杂剖面起着至关重要的作用，它规定了逆变器的二进制或三元操作。利用TCAD混合模模拟器对逆变器进行了分析。结果表明，在极低的SS (1 mV/ 10)下，I - ON / I - OFF比的高值为1010。研究了逆变器的电压传递特性及其与掺杂水平的关系。并将该逆变器的电学性能与以往同类逆变器进行了比较。

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引用次数: 0

Design of Low-Cost Full W-Band 8th Harmonic Mixers for Frequency Extension of Spectrum Analyzer 频谱分析仪扩频用低成本全w波段8次谐波混频器的设计

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-23 DOI: 10.1049/2023/8196039

Jian Guo, Kaiyi Zang, Zihan Zhang, Liang Zhao, Jie Xu, Zhengbin Xu

High-order harmonic mixer is popular for frequency extension of spectrum analyzer (SA) from microwave to millimeter-wave or even terahertz band. The manufactures of SA usually offer expensive harmonic mixers where frequency extension is needed. In this work, low-cost designs of 2-port and 3-port W-band 8th harmonic mixers covering 75–110 GHz are proposed, and design method of two port mixer without frequency diplexer to separate local oscillator (LO) and intermediate frequency (IF) signals are first presented. These two kinds of mixers are compatible with almost all the current SAs with frequency extension options, which provides LO for the external harmonic mixer. The mixers are designed with planar microstrip lines and antiparallel Schottky diodes. The circuit of 2-port mixer includes the input broadband bandpass filter, diodes, output lowpass filter, and matching circuits. As for 3-port mixer, only an extra diplexer is needed to separate the IF signal and LO signal. The diplexer is composed of a planar semi-lumped lowpass and a highpass filter. The planar circuits are easily fabricated with low-cost print circuit board process on polytetrafluoroethylene substrate. The measured conversion loss of 2-port 8th harmonic mixer is from 20 to 26 dB, and 23 to 28 dB for 3-port mixer at full W-band. The good measured results indicate the proposed mixers are simple and effective.

高次谐波混频器是频谱分析仪从微波到毫米波甚至太赫兹波段进行频率扩展的常用方法。在需要频率扩展的地方，SA的制造商通常提供昂贵的谐波混频器。本文提出了覆盖75-110 GHz的2口和3口w波段8次谐波混频器的低成本设计方案，并首次提出了不带频率双工器的两口混频器的设计方法，用于分离本振(LO)和中频(IF)信号。这两种混频器兼容几乎所有当前的sa与频率扩展选项，这为外部谐波混频器提供了LO。该混频器采用平面微带线和反平行肖特基二极管设计。二端口混频器电路包括输入宽带带通滤波器、二极管、输出低通滤波器和匹配电路。对于3端口混频器，只需要一个额外的双工器来分离IF信号和LO信号。双工器由平面半集总低通和高通滤波器组成。采用低成本的印刷电路板工艺在聚四氟乙烯衬底上易于制作平面电路。在全w波段，2口8次谐波混频器的转换损耗为20 ~ 26 dB, 3口混频器的转换损耗为23 ~ 28 dB。实测结果表明，该混合器简单有效。

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引用次数: 0

An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology 采用0.18µm CMOS技术提高5 GHz E类功率放大器的功率增益效率的方法

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-23 DOI: 10.1049/2023/5586912

Hemad Heidari Jobaneh

A new approach to increasing the power-added efficiency (PAE) of a class E power amplifier (PA) is proposed in this paper. The PA operates at a 5 GHz frequency and a reactance compensation technique is utilized to maximize the bandwidth at the operating frequency. The driver stage creates either a half-wave rectified sine wave or a half-wave rectified sawtooth wave. By applying each one of the waves, the performance of the PA is examined and PAE = 70% and PAE = 50% is achieved. Plus, the output power of the PA is about 26 dBm when the DC voltage supply is 1.8 V. Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.

提出了一种提高E类功率放大器功率附加效率(PAE)的新方法。该放大器工作在5ghz频率，利用电抗补偿技术最大限度地提高工作频率下的带宽。驱动级产生半波整流正弦波或半波整流锯齿波。通过应用每一个波，测试了PA的性能，达到了PAE = 70%和PAE = 50%。另外，在直流电压为1.8 V时，PA的输出功率约为26 dBm。采用先进的设计系统和TSMC 0.18µm CMOS工艺进行仿真。

引用次数: 0

Generative Target Tracking Method with Improved Generative Adversarial Network 基于改进生成对抗网络的生成目标跟踪方法

4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-10-23 DOI: 10.1049/2023/6620581

Yongping Yang, Hongshun Chen

Multitarget tracking is prone to target loss, identity exchange, and jumping problems in the context of complex background, target occlusion, target scale, and pose transformation. In this paper, we proposed a target tracking algorithm based on the conditional adversarial generative twin networks, using the improved you only look once multitarget association algorithm to classify and detect the position of the target to be detected in the current frame, constructing a feature extraction model using generative adversarial networks (GANs) to learn the main features and subtle features of the target, and then using GANs to generate the motion trajectories of multiple targets, finally fuzing the motion and appearance information of the target to obtain the optimal match. The optimal matching of the tracked targets is obtained. The experimental results under OTB2015 and IVOT2018 datasets demonstrate that the proposed multitarget tracking algorithm has high accuracy and robustness, with 65% less jumps and 0.25% more accuracy than the current algorithms with minimal identity exchange and jumps.

在复杂背景、目标遮挡、目标尺度、姿态变换等环境下，多目标跟踪容易出现目标丢失、身份交换、跳跃等问题。在本文中，我们提出了一种基于条件对抗生成孪生网络的目标跟踪算法，使用改进的“只看一次”多目标关联算法对当前帧中待检测目标的位置进行分类和检测，使用生成对抗网络(GANs)构建特征提取模型来学习目标的主要特征和细微特征;然后利用gan生成多个目标的运动轨迹，最后融合目标的运动和外观信息，得到最优匹配。得到了跟踪目标的最优匹配。在OTB2015和IVOT2018数据集上的实验结果表明，所提出的多目标跟踪算法具有较高的精度和鲁棒性，在最小身份交换和最小跳变的情况下，比现有算法减少65%的跳变，提高0.25%的精度。

引用次数: 0

Linear broadband interference suppression circuit based on GaN monolithic microwave integrated circuits 基于GaN单片微波集成电路的线性宽带干扰抑制电路

IF 1.3 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-07-26 DOI: 10.1049/cds2.12159

Megan C. Robinson, Zoya Popović, Gregor Lasser

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold-FET connected high electron mobility transistors acting as varactors. Two types of periodically-loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two-tone measurements, and the circuit demonstrates a 3rd-order intercept input power larger than 30 dBm for control biases above −12 V.

本文介绍了2–4GHz倍频程带宽干扰抑制电路的仿真和测量结果。该电路通过干涉仪结构实现了可调谐频率陷波的功能。干涉仪路径中的相对延迟随着GaN单片微波集成电路可调谐延迟线而变化。通过改变用作变容二极管的冷FET连接的高电子迁移率晶体管的漏极电压来调节延迟。比较了两种类型的周期性加载延迟线：均匀设计和锥形设计。开发了一个简单的理论研究，将干涉仪电路分支中的延迟和振幅联系起来，为设计提供信息。实现了两个干扰抑制混合电路，测量结果表明，均匀延迟线在2.24–4 GHz范围内具有25–40 dB的陷波，锥形设计在2.32–4.13 GHz范围内。两种设计的回波损耗都保持在10dB以下。对于不同的音调功率，用间隔0.5和1GHz的两个音调进行测量以量化抑制。该电路可以处理37dBm的输入功率，并保持两个同时间隔0.5GHz的25dBm音调的性能。线性度的特点是10 MHz双音测量，该电路在−12 V以上的控制偏压下表现出大于30 dBm的三阶截距输入功率。

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引用次数: 0

Mechanical model analysis and reliability design approach of Quartz Flexible Accelerometer under fractured state 石英挠性加速度计断裂状态下的力学模型分析及可靠性设计方法

IF 1.3 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Iet Circuits Devices & Systems

Pub Date : 2023-07-06 DOI: 10.1049/cds2.12161

Tingyu Xiao, Chunxi Zhang, Lailiang Song, Longjun Ran, Wanying Huang

Currently, the Quartz Flexible Accelerometer (QFA) mounted for the applications working in high acceleration environment are suffering from the fracture of the flexible beams under external acceleration shock. This paper presents the mechanical model and reliability design approach of QFA to maintain the measuring ability under a fractured state. The structural parameters changed significantly in the mechanical model under a fractured state compared to those in the original model. A modified structure to maintain the measuring ability of QFA under a fractured state is designed with the reference of the sensitive module in Electrostatic Suspended Accelerometer (ESA). The corresponding close-loop system is corrected and discretised to ensure the stability requirements of the mechanical model. A static experiment is conducted to prove the effectiveness of the proposed model by a prototype QFA with completely fractured flexible beams. The result shows helpful on the preliminary research for QFA with the similar sensitive structure to ESA.

目前，应用于高加速度环境中的石英柔性加速度计（QFA）在外部加速度冲击下会发生柔性梁断裂。本文提出了QFA在断裂状态下保持测量能力的力学模型和可靠性设计方法。与原始模型相比，断裂状态下的力学模型中的结构参数发生了显著变化。参考静电悬浮加速度计中的敏感模块，设计了一种在断裂状态下保持QFA测量能力的改进结构。对相应的闭环系统进行了校正和离散，以确保力学模型的稳定性要求。通过一个具有完全断裂柔性梁的QFA原型进行了静态实验，验证了该模型的有效性。研究结果对类似ESA灵敏结构的QFA的初步研究具有一定的指导意义。

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引用次数: 0

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