Iet Circuits Devices & Systems最新文献

In this article, we present a lead-free hybrid-halide perovskite solar cell (PSC) using guanidinium (GA)-formamidinium tin iodide (GA_0.05FA_0.93SnI₃) as the absorber layer (AL), the performance metrics analyses on the light of short-circuit current (I_sc), power conversion efficiency (PCE), open circuit voltage (V_oc), and fill-factor (FF). Utilizing the SCAPS-1D numerical program, we have optimized the material and device parameters, including thickness of AL, electron affinity, defect density, doping concentration, and series and shunt resistances. The GA_0.05FA_0.93SnI₃ AL exhibits highly stable and nontoxic in nature. The proposed hybrid halide-based PSC achieved an enhanced PCE (27.55%) in comparison with reported cutting-edge PSCs, under the AM1.5G spectrum.

In the field of hardware accelerators for convolutional neural network (CNN) inference, quantization techniques have been widely employed to enhance the performance. The prevailing quantization scheme of the accelerator at present is using signed 8-bit integer variables (INT8). CNN accelerators support INT8, while lower precision INT4 is less common. Accelerators supporting INT4 depthwise separable convolution (DWC) are even rarer. Therefore, this article presents a high-performance CNN accelerator that not only supports 8-bit and 4-bit data but also supports standard convolution (SC) and DWC. Additionally, in order to improve the transmission efficiency of DWC, an intermediate cache strategy is proposed, using a pointwise convolution (PW) input buffer (PW BUF) to store output data from depthwise convolution (DW) to avoid off-chip transmission. Furthermore, to address the issue of a DSP cannot perform two 4 × 4-bit multiplications when dealing with DW, a processing element (PE) is designed to make full use of DSP hardware resources. Finally, this accelerator is implemented on ZYNQ ZC706 with a frequency of 200 MHz. Experimental results show that it achieves a performance up to 307.88 giga operations per second (GOPS) on VGG, reaching 97.9% peak performance; while on MobileNet, it achieves efficient performance with 206.43 GOPS with only 392 DSPs. Compared with mainstream CNN accelerators, it increases DSP utilization rate (GOPS/DSP) by 1.5× to 33.5×.

Physically unclonable function-based authentication is one of the widely accepted and promising hardware security primitives. For security applications, strong PUF circuits can generate a large number of challenge–response pairs (CRPs) for authentication. These CRPs can, however, be utilised by machine learning (ML) techniques to model the physically unclonable function (PUF) and forecast its responses. In this paper, we evaluate the robustness of analog PUF designs, specifically hybrid current mirror inverter (HCMI) and diode triode current mirror inverter (DTCMI) PUFs, against ML attacks. The XOR-tree configuration in the PUF amplifies entropy and introduces additional nonlinearity, making the CRP mapping significantly harder to model. Deep neural networks (DNNs) attack and the PyPUF toolbox were utilised to evaluate the modelling attacks on the HCMI and DTCMI PUFs. Experiments were conducted using CRP counts ranging from 10,000 to 1,000,000. Despite varying the number of hidden layers and nodes in the DNN model, the attack accuracy consistently remained near 50%, indicating the robustness of analog PUFs to ML-based modelling techniques. The evaluation using the PyPUF toolbox also resulted in consistent accuracy near 50%, indicating poor learnability. The results highlight the strong resistance of XOR-tree-enhanced HCMI and DTCMI analog PUF designs to advanced machine-learning attacks compared to the vulnerabilities of conventional digital PUFs.

This paper presents an enhanced linear pulse-frequency modulator (LPFM) ion-sensitive field-effect transistor (ISFET) architecture with a programmable dynamic range for pH detection. The circuit encodes the pH signal into the frequency domain. This proposed method is shown to have higher stability for supply variation. A dynamic referencing scheme is used to increase the stability of the recording over long periods. The circuit’s operating point and dynamic range can be programmed, enhancing the versatility of the architecture. The design was implemented in a 0.18 µm standard CMOS process, with a sensing area as an extended gate electrode of 125 µm × 125 µm. The architecture was electrically and electrochemically characterised. The ISFET chip was post-processed by thinning the passivation layer over the sensing area. The results showed a boost in the sensitivity of 230%, an increase of 9% in the passivation capacitance with an intact SiO2 layer, and a 45% reduction of the Si3N4 layer. Compared to a rapid decay in signal quality, the dynamic reference method showed consistent measurements over hours. The circuit also showed very low sensitivity for around 25% supply variation.

The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)-based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal-to-noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024-point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256-point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.

This paper presents a software-controlled offset-cancelation technique for analog multipliers that relies on the Bayesian-optimization algorithm. The capability of the technique was investigated on a test multiplier, which was developed for future use in machine learning (ML) accelerators whose convergence is sensitive to process-variation-induced DC offsets. By adjusting the multiplier biasing voltages, the proposed Bayesian-optimization-based method was able to reduce the offset within ±1.8 mV from an uncorrected maximum offset of 10.6 mV. In addition to reducing offsets, the measurements of the 65-nm CMOS multiplier also showed an average linearity-error improvement of nearly 10%, from 12.2% prior to offset correction to 2.2% after correction. We demonstrate that the proposed offset correction improved the learning outcome accuracy for MNIST dataset digit classification from approximately 10% to 90%.

In this article, a phase shifter circuit designed for next-generation communication systems was presented. Operating at 4.5–5.5 GHz, the circuit in question is a 3-bit all-pass LC lattice, which was initially analyzed using MATLAB. Following this analysis, the circuit was set up and simulated in advanced design system (ADS) using numerical values derived from the MATLAB simulations. A switch capacitor is employed as the switching element within the circuit. For phase shifts of 45°, 90°, and 180°, the phase errors are 3°, 9°, and 0°, respectively, while the power losses are 1.5 dB, 3 dB, and 1.9 dB, respectively.

In this paper, various D flip-flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional-bridging FF (CBFF)-S, self-shut-off pulsed latch (SSPL), retentive true signal phased clock (R-TSPC), mTGFF, mC2MOS, FS-TSPC-DET-FF, and P-FF, are briefly reviewed for different architectures and technologies, with the trade-off between the various performance parameters discussed in this paper. Comparative analysis is done for the selected DFFs on technology, supply voltage, set-up time, delay, power consumption, and area. Reliability effects on DFFs and aging effect on FFs are reviewed for timing yield-aware lifetime reliability (TYR) based on the process variations (PVs) and bias temperature instability (BTI). A brief review on applications of DFFs in internet of thing (IoT) devices and artificial intelligence (AI), such as frequency divider, dual-modulus prescaler, time-to-digital converter (TDC), shifter, and synchronizer, is also presented.

This study presents a novel triple-step bias-flip rectifier with a post implementation calibration (PIC) scheme to address both the need for a general-purpose adaptable piezoelectric energy harvester (PEH) interface circuit (PEHIC) and the PVT-related issues while maintaining acceptable efficiency and a smaller inductor. Due to the PIC, the proposed circuit is adaptable to various piezoelectric materials and inductors. Using a 100-µH inductor, a 180 nm standard design kit, and an energy investing (EI) scheme, the proposed rectifier achieves a bias flip efficiency of 100%. Without EI, the proposed circuit achieves the recently reported high bias flip efficiency, that is, ɳ_flip, in the literature with a considerably smaller inductor. According to simulation results, the improvement of the designed circuit relative to the full bridge rectifier (FBR) falls within the scope of 2–3.8. Postsimulation calculations revealed that the figure of merit of adaptivity, that is, FoM_adaptivity, of the proposed circuit is approximately 83.

Restoring load following partial outages or local faults in a section of the distribution system, as addressed in this study, is crucial to minimizing service interruptions and financial damages. Reconfiguring the network is a crucial first step in load restoration. The presence of distributed generation (DG) units, in addition to the reconfiguration of the distribution network, can be very effective in the load recovery process. Therefore, in this study, the problem of reconfiguring the distribution network in the presence of DG units and charging stations of electric vehicles with the goals of reducing energy not supplied (ENS) and losses has been solved. The suggested problem is resolved by introducing and putting into practice the hybrid particle swarm optimization and shuffled frog leaping (HPSO-SFL) algorithm, which is based on hybrid swarm intelligence. The effectiveness and accuracy of the proposed method are validated using a 33-bus test system under multiple scenarios. To assess its performance, the results are compared against those reported in previous studies. Following network reconfiguration, the power losses were reduced by 45% without DG and by 77% with DG, relative to the initial system state. Furthermore, when electric vehicle charging stations (EVCSs), modeled as active loads, were included in the optimization process, power losses decreased by approximately 23% compared to the pre-reconfiguration condition.