Iet Circuits Devices & Systems最新文献

In this contribution, a chaos-based microcontroller electrocardiogram (ECG) signal acquisition-security-transmission system is proposed. It is designed based on a Novel 4Wings-4D Chaotic Oscillator (N4W4DCO) with a hyperbolic sine nonlinearity unbalanced. The classical nonlinear dynamics tools, such as 2D bifurcation and the highest Lyapunov exponent curves, basins of attraction, and power spectral density, help us see that the proposed chaotic oscillator generates periodic oscillations, intermittency + crisis routes to chaos, transient chaos, and the coexistence of 4/2 wings attractors just to name a few dynamics. The data generated using highly chaotic regime are tested using the well-known NIST TEST -800-22 Rev A and the results passed the test successfully. The N4W4DCO oscillator is embedded in an Arduino microcontroller where the discovered interesting dynamics are confirmed. A low-cost ECG acquisition circuit with an AD8232 ECG sensor is also designed and experimented. ECG signals are acquired and directly loaded into MATLAB-Simulink and are successfully encrypted with random data from the N4W4DCO in its chaos regime. The scrambled ECG signals from experiment are sent through an added white gaussian noise (AWGN) channel and thereafter received and decrypted. These results are promising and open the possibility of improving secure telemedicine transmission systems.

This study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual-material gate-oxide-stack double-gate tunnel field-effect transistor (DMGOSDG-TFET). The performance of this DMGOSDG-TFET, employing work-function engineering and gate-oxide-stack techniques, is compared with a GaAs pocket-doped DMGOSDG-TFET. Using the Silvaco Technology Computer-Aided Design tool, the comparison covers DC characteristics, analog/RF behavior, and circuit-level assessments. The research introduces an optimized heterostructure pocket-doped DMGOSDG-TFET to enhance DC characteristics, analog/RF performance, and DC/transient analysis. This novel architecture effectively suppresses ambipolarity, making it more suitable for current conduction. The incorporation of work-function engineering and a gate-oxide-stack approach enhances the device’s current driving capability, while the use of a highly doped GaAs pocket at the source and drain virtually eliminates ambipolar current conduction. Simulation results indicate that the proposed heterostructure device exhibits a high ON-current and switching ratio. For analog/RF applications, the optimized heterostructure device outperforms conventional DMGOSDG-TFET, offering higher cutoff frequency, transconductance, and other analog/RF parameters. Circuit-level performance is assessed using HSPICE, with a focus on the implementation of a resistive-load inverter for both proposed and conventional device topologies through DC and transient evaluations.

A staggering number of applications rely on the network architecture to carry out their tasks, which has led to a fast growth in wireless sensor networks (WSN). The possibility of harmful activity and data theft is growing as a result of the growth in devices and data. Thus, the network’s regular users have an impact on legitimate data delivery, which lowers customer happiness and worsens network standards. The data have been saved using a variety of security procedures that have been developed in past research studies. However, harmful activity continues to engage in its illegal operations despite their efforts to safeguard data transmission in the network. As a result, a number of recent research projects have concentrated on predicting innovative techniques and processes to offer security in WSN. In comparison to existing methods, this work attempted to offer an effective tighter security for WSN and suggested an ML-Based Secured Routing Protocol (MLSRP) for WSN with improved energy efficiency and overall performance. Energy efficiency is the main requirement of WSNs, hence a clustered network is proposed where the data are routed through the cluster head nodes. In this paper, a multicriteria based decision-making (MCDM) model is used by the MLSRP to perform data routing, clustering, and cluster head election while also analyzing a number of network characteristics that might affect the quality of a node, route, and data. In NS2 software, the suggested framework is put into practice and simulated. The results are then validated to gauge performance. The observed quantitative results reveal that the proposed MLSRP method attains an improved network lifetime by 5% and network throughput of 6%. It reduces energy consumption by 40%, curtails overhead to 37%, and minimizes end-to-end delay by 30% than the other conventional methods. The suggested framework performs better than others when its total performance is compared to that of older methods.

Accurate passenger flow forecasting is crucial in urban areas with growing transit demand. In this paper, we propose a method that combines advanced machine learning with rigorous time series analysis to improve prediction accuracy by integrating different datasets, providing a prescriptive example for passenger flow prediction in urban rail transit systems. The study employs advanced machine learning algorithms and proposes a novel prediction model that combines two-stage decomposition (seasonal and trend decomposition using LOESS–ensemble empirical mode decomposition (STL-EEMD)) and gated recurrent units. First, the STL decomposition algorithm is applied to break down the preprocessed data into trend terms, periodic terms, and irregular fluctuation terms. Then, the EEMD decomposition algorithm is employed to further decompose the irregular fluctuation terms, yielding multiple IMF components and residual residuals. Subsequently, the decomposed data from STL and EEMD are partitioned into training and test sets and normalized. The training set is utilized to train the model for optimal performance in predicting subway short-time passenger flow. The synthesis of these sophisticated methodologies serves to substantially enhance both the predictive precision and the broad applicability of the forecasting models. The efficacy of the proposed approach is rigorously evaluated through its application to empirical metro passenger flow datasets from diverse urban centers, demonstrating marked superiority in predictive performance over traditional forecasting methods. The insights gleaned from this study bear significant ramifications for the strategic planning and administration of public transportation infrastructures, potentially leading to more strategic resource allocation and an enhanced commuter experience.

Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.

Diabetic retinopathy (DR) is an ocular ailment that may lead to loss of vision and eventual blindness among individuals diagnosed with diabetes. The blood vessels of the retina, a layer of light-sensitive tissue located at the posterior aspect of the ocular globe, are adversely impacted. The identification of DR entails the utilization of retinal fundus images. The detection of any form of abnormality in the eye through raw fundus images poses a significant challenge for medical practitioners. Hence, it is imperative to engage in the processing of fundus images. This paper delineates several image processing techniques for DR images, including but not limited to, manipulation of brightness levels, application of negative transformation, and utilization of threshold operations. It focuses on elucidating the enhancement techniques that pertain to DR images, which aim to optimize the visual quality of said images in order to facilitate more facile disease detection. The process of detecting edges within DR images is also executed by Sobel edge detection algorithm. In order to successfully execute the aforementioned algorithms, expedient and contemporaneous systems are favored to account for the intricacies of the image processing calculations. The exclusive utilization of software techniques in order to fulfill the prerequisites of advanced algorithms presents a significant challenge, owing to the multifarious processes that are involved in their computation, coupled with an exigent requirement for high processing speeds. The proposed model is utilized to articulate a proficient model for the design and execution of field programable gate array (FPGA)-based image enhancement processes along with the Sobel edge detection algorithm upon DR images. Finally, a Internet Protocol chip is developed that can combine multiple image enhancement operations into a single framework with less complexity.

With the growing competition between the various manufacturers of electronic products, the quality of the products developed and the consequent confidence in the brand are fundamental factors for the survival of companies. To guarantee the quality of the products in the manufacturing process, it is crucial to identify defects during the production stage of an electronic device. This study presents a system based on traditional visual computing and new deep learning methods to detect defects in electronic devices during the manufacturing process. A prototype of the proposed system was developed and manufactured for direct use in the production line of electronic devices. Tests were performed using a particular smartphone model that had 22 critical components to inspect and the results showed that the proposed system achieved an average accuracy of more than 90% in defect detection when it was directly used in the operational production line. Other studies in this field perform measurements in controlled laboratory environments and identify fewer critical components. Therefore, the proposed method is a real-time high-performance system. Furthermore, the proposed system conforms with the Industry 4.0 goal that process system digitization is essential to improve indicators and optimize production.

Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm² and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

A power amplifier design operating at 28 GHz for communication applications is presented in this paper. Analog predistorted technique is used to improve the linearity using a cold mode MOSFET linearizer. The paper reports +19.8 dBm of peak power at the output and power-added efficiency (PAE) of 17% is attained by the designed circuit. The 1-dB compression point linearity was +18.6 dBm. The adjacent channel power ratio (ACPR) simulations were performed for the different communication standards like 802_11n_40M, CDMA, IS-95, and 802_11n_20M. Design specification variations of the amplifier have been analyzed over five process corners and simulations were performed to validate compliance with standards and robustness of the designed circuit. Monte Carlo simulation were performed to assess the performance over statistical variability of PAE and power gain. It is believed that this linearization design and the verifications used are done for the first time on a 65-nm RFCMOS process.

In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ₂ is improved from 11.9° to 12.6°, and the thickness ratio of H_up/H_bottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance R_on,sp could achieve as low as 11.3 mΩ mm², while breakdown voltage BV_ds,max arrives at 37.4 V, which is nearly 19.3% improved.