Iet Circuits Devices & Systems最新文献

Taking the optimal sensor placement problem in bridge structural health monitoring as the study object and relying on the engineering example of a simply supported steel truss bridge, the improved optimal sensor placement method based on sensitivity-effective independence method was proposed. Using the sensitivity coefficient reflecting structural damage, the proposed method could modify the effective independence method reflecting the maximum linear independence. The proposed method further optimizes the sensor placement method. A method for selecting the number of models based on modal closeness was proposed and makes the selection of the number of modes more objective. The example analysis shows that evaluations using this method are effective for multiple evaluation criteria. The method ensures observability of the mode vector and identifiability of structural damage. It is an effective optimal sensor placement algorithm for the bridge structure.

In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor-based large-scale designs. A comprehensive automatic framework for the design and synthesis of large-scale memristor-complementary metal-oxide-semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library file for large-scale simulation. The proposed architecture is based on RRAM and ReRAM redox-based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was verified with Verilog-XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor-based parallel 8-bit adder/subtractor and a 2D memristive-based median filter. Both proposed designs memristor-based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology.

In most of the real time video processing applications, cameras are used to capture live video with embedded systems/Field Programmable Gate Arrays (FPGAs) to process and convert it into the suitable format supported by display devices. In such cases, the interface between the camera and display device plays a vital role with respect to the quality of the captured and displayed video, respectively. In this paper, we propose an efficient FPGA-based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. The novelty of our work is the design of optimised architectures for Controllers, Converters, and several interfacing blocks to extract and process the video frames in real time efficiently. The flexibility of parallelism has been exploited in the design for Image Capture and Video Graphics Array (VGA) Generator blocks. The Display Data Channel Conversion block required for VGA to High Definition Multimedia Interface Conversion has been modified to suit our objective by using optimised Finite State Machine and Transition Minimiszed Differential Signalling Encoder through the use of simple logic architectures, respectively. The hardware utilization of the entire architecture is compared with the existing one which shows that the proposed architecture requires nearly 44% less hardware resources than the existing one.

A pole-converging X-band low-noise amplifier (LNA) using 130 nm CMOS technology is proposed. An on-chip pole-converging capacitor C_PC is added between the gate and drain node of the common-gate (CG) stage. The capacitor C_PC combines with a noise-reducing inductor L₁ to converge poles into the desired band, which results in a pole-converging effect and wideband performance. The proposed modified broadband simultaneous noise and input-matching technique is adopted in triple-cascode configuration to realize good input matching and a low noise figure (NF). Measurement results exhibit a flat maximum power gain of 17.6 dB from 8 to 12 GHz and a reverse isolation over 60 dB within the desired bandwidth along with an NF ranging from 1.5 to 3.6 dB. The LNA core dissipates 17 mW from 2.4 V supply, and the chip size occupies 1.1 × 0.9 mm² including all pads. The simulated and measured results show good agreement from 8 to 12 GHz.

To obtain the required LED-driving current, variable frequency control directly leads to large reactive circulation, and the design of the electromagnetic interference circuit is more complex. However, soft switching cannot be guaranteed by constant frequency operation under load variations. Hence, a multiplex LED-dimming circuit based on a variable inductor is proposed that completes the constant frequency operation and realizes zero-voltage switching to improve efficiency. The proposed circuit with a superimposed half-bridge structure increases the number of outputs and simultaneously shares the resonant inductor so that the power density is improved and the LED-dimming unit is simplified. The working principle of the circuit is described—it uses eight-channel output to build an 80 W experimental prototype to verify the feasibility of the LED driver.

Epilepsy is one of the most common neurological disorders; it affects millions of people globally. Because of the risks to health that it causes, the study and analysis of epilepsy have been given considerable attention in the biomedical field. In a neurological diagnosis, an automated device for detecting seizures or epilepsy from an electroencephalogram (EEG) signal has a significant role. This research work proposes a very large scale integration implementation system for the automatic detection of seizures. Before classification, feature extraction was performed by discrete wavelet transform (DWT) and on-chip classification was performed by a linear support vector machine. The polyphase architecture of Daubechies fourth-order wavelet three-level DWT was used to minimize computational time. The systolic array architecture-based support vector machine classifier using parallel processing helps to minimize the computational complexity of the proposed method. This research work uses an open access EEG dataset. Hardware implementation was done on a field-programmable gate array (FPGA). Efficient results were produced compared with the existing system on chip (SoC) and FPGA seizure detection systems.

To the best of the author's knowledge, several studies during 1960–2019 were carried out on wideband and ultrawideband LNAs just to render optimum LNAs for SAW-less Radio-Frequency Integrated Circuits (RFICs) but none of these works reviewed and taught the proceedings of these six decades, hence the lack of a comprehensive review is quite noticeable. This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, g_m-boosting, active inductor and notch filter. Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High-Electron-Mobility Transistor (HEMT) technologies. This work describes the endeavours of engineers in reaching UWB LNA from narrowband LNA during six decades that have great importance as a chapter in understanding this topic because it teaches all topologies, techniques, circuits and related events in a historical narrative for trained readers who are not experts on this topic.

Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side-channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage-defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull-down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage-defined power-balance (TVD-PB) design is fabricated using a 65-nm CMOS technology, and the core area occupies approximately 0.0044 mm², composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD-PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD-PB universal gate is 99.68%. In addition, the current margin is higher than 55 μA and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state-of-the-art techniques, the power dependency against power attacks is improved effectively.

An energy-efficient regenerative comparator design is unveiled. A floating capacitor is utilized to protect the complete discharge of the preamplifier output nodes by NMOS input transistors. The introduced floating capacitor is flipped around the preamplifier to allow PMOS cross-couple transistor charge reutilization and elevate amplification gain at the integration phase. By increasing amplification gain, the input common mode voltage of the NMOS latch that is toggled within some delay is increased, too. Therefore, the latch stage is activated strongly, and regeneration delay is reduced. Simulation results corroborate that the proposed technique reduces power consumption and input-referred offset by more than 60% compared with results of similar previous works. Furthermore, the referred noise and delay are improved more than 30%.

This work presents a gallium nitride (GaN) high electron mobility transistor (HEMT)–based cascaded multistage power amplifier (MPA) in class-AB for L-band radar applications. The purpose of this endeavour is to develop an MPA using GaN HEMT devices to achieve optimised parameters such as high gain, high power, better efficiency, and linearity in a compact size. In an MPA design with multiple stages, oscillations are common owing to unwanted high gain at the lower frequency range. To overcome this issue, we introduced interstage harmonic termination networks as a novel approach to suppress high gain at low frequencies, which are prone to oscillations. The proposed cascaded MPA provides the maximum radio-frequency output power of 89 W and a power gain of 52 dB with an associated power-added efficiency of 51%. Second and third harmonic levels are −32.5 and −37 dBc, respectively. Two-tone measurements are performed with a frequency separation of 10 MHz, and an intermodulation level of less than −33 dBc is achieved.