Iet Circuits Devices & Systems最新文献

Polymer-dispersed liquid crystal automated quantification system for vision through polymer-dispersed liquid crystal double-glazed windows: Circuit implementation (PDLC)-windows played an essential role in providing a visual comfort for occupants in commercial buildings recently. PDLC windows adjust the visible transparency of the glazing to control the daylight accessed to internal environments. A former study proposed an algorithm to quantify the vision through the PDLC glazing in terms of image contrast. The quantification algorithm determines the minimum level of transparency that maintains a comfortable vision through the window. This study introduced the implementation of a real-time automated system that achieves the vision quantification process. Firstly, system on-chip was utilised to realise the quantification algorithm, including contrast estimation. Secondly, the contrast determination action was re-implemented using MATLAB, Cortex-A9 microcontroller, and Cyclone V field programmable gate array field programmable gate array-chip. The implemented systems were evaluated based on the latency, throughput, power consumption, and cost.

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase-frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage-controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase-frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage-controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed-forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide-by-47 and divide-by-48) that lacks a few extra flip-flops which save considerable power and improves the frequency difficulties of the multi-band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1-μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS-based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

In this correspondence, a mathematical model is developed for the efficient realisation of a generalised M × M polyphase parallel finite impulse response (FIR) filter structure composed of M parallel conventional decimator polyphase filters. Primarily, the proposed structure is designed in such a way that the benefit of coefficient symmetry property of linear-phase FIR filters can be availed without using the pre/post circuit blocks. A numerical example is also studied to validate the proposed structure. Furthermore, the delay-elements reduction approach is given to avoid the excessive usage of memory elements and the performance of the proposed structure is evaluated in terms of the number of delay elements $��\left(��D��\right)�$, adders $��\left(��A��\right)�$ and multipliers $��\left(��M��\right)�$. Compared to the traditional structures, our proposed structure is found to be more efficient in terms of $��M�$. Moreover, in contrast to the fast FIR algorithms, the proposed structure resolves the issues of additional requirements of the pre/post blocks and the absence of parallel structure with coefficient symmetry for higher prime values of M (i.e. M > 3). The synthesis result reveals that the proposed 37-tap filter (with M = 3 and 12-bit inputs) involves 30% less area-delay-product (ADP) per output and 33.05% less power per output compared to the most recent structure.

This study presents the design and analysis of a 180° tunable non-reciprocal active broadband coupler. To increase the bandwidth, the multi-section impedance transformation technique is utilised. The coupler includes two amplifiers, and three filters (phase-shifters) on the gate (drain) line, referred to as through-path (coupled-path). To achieve an accurate 180° broadband coupler, the staggering technique is utilised for designing the filters. Lumped-element analysis, adopted here for the first time to analyse the active coupler, reveals the impacts of each element on directivity, output phase-shift, and phase-error. The design and post-layout simulation of the coupler are performed in 0.18 µm CMOS technology over the frequency range of 10–20 GHz. An output phase of 180° ± 1.7°, a directivity more than 27 dB, and a return loss better than 10 dB are achieved. The coupling gain is 7.7 dB at the centre frequency, the noise figure is 4.8 dB, and the power consumption is 22 mW. By tuning the bias voltage, the phase imbalance caused by process variations can be compensated. Also, a prototype of the coupler was fabricated and tested on a Rogers substrate for 8–10 GHz band, giving an output phase of 180° ± 2° and a directivity >15 dB.

A dual-path open-loop slew-rate (SR) controlled Complementary Metal Oxide Semiconductor (CMOS) driver is presented in this study. The proposed output driver incorporates a delay-locked loop (DLL) to minimise the SR variations over process, voltage and temperature, generating delayed versions of transmitted signal by sampling the input data with adjacent phases of the clock from the DLL. A dual-path open-loop signal-superposition technique is introduced to suppress the high-frequency components of the output driver and thus improves the SR of the CMOS driver. The proposed CMOS output driver achieves a maximum SR of 1.00 and <0.35 V/ns variation operating at 500 Mbps over 32 corners. Both the conventional CMOS driver and the proposed SR controlled output driver were fabricated in a 0.18 μm CMOS process. The proposed driver occupies a compact area of 0.088 mm² and consumes 55.27 mW with a 1.8 V supply voltage. Measurement results show that the SR of the proposed output driver is <0.816 V/ns, corresponding to 62% reduction compared with that of a conventional output driver, and the total jitter is <0.16 unit interval.

To develop an optimised rehabilitation training system for various severity strokes in rats. The method provided feedback regarding the rat's measured position to a microprocessor, which adjusted the training speed accordingly and enables the rat to continuously exercise in the middle position of the ladder. This created a cyclic control system that provided various training intensities based on timely evaluations of the ladder-climbing capabilities of each rat, thus providing a suitable rehabilitation method for subjects with various stroke severities. The modified neurological severity score, rotarod and cerebral infarction volume results for the 60- and 90-min middle cerebral artery occlusion (MCAO) treadmill groups did not differ significantly from those of the control group. Conversely, the cerebral infarction volumes of the ladder-climbing rehabilitation groups in the 30-, 60-, and 90-min MCAO were all significantly lower than those of the control group (84.03 ± 23.24 vs. 256.77 ± 85.63 (mm³), 265.19 ± 41.12 versus 377.17 ± 90.97 (mm³), and 303.80 ± 47.15 versus 452.68 ± 90.44 (mm³) respectively), thereby indicating the optimised ladder-climbing method as effective for subjects with various stroke severities. Individual differences may cause different exercise capacities for each participant. To accommodate for these exercise capacities, an optimised ladder-climbing rehabilitation training system was proposed, which provided training according to the physical abilities of each participant.

Retraction: [Kaiyi Qiu, Xin Liu, Jie Liu, Hongbo Ma, Jingya Li, Zhengchao Zhang, Guangliang Chen, Li Cai, Research on tridimensional monitoring and defence technology of substation, IET Circuits, Devices & Systems 2022 (https://doi.org/10.1049/cds2.12129)].

The above article from IET Circuits, Devices & Systems, published online on 14 September 2022 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer review process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.

Network-on-Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network-based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. For a reliable design against failures, first, the system should be analysed to discover the critical points. Hence, in this research, it is tried first to investigate the scale of fault tolerance effect on the mechanism in the router on the network by injecting simulated errors, and then these errors are prevented. As the major novelty, the authors implemented a router on a synchronised network and calculated the network buffering fault tolerance by injecting error in the buffer. Specifically, a new method for improving fault tolerance is proposed, which uses the existing resources efficiently. So, it does not impose any overhead on hardware and improves the error tolerance scale. The authors also evaluate it from different perspectives to show its superior performance.

This article presents the design and optimisation of a sub-1 GHz class-F ultra-low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class-F PA. The ET consist of a pre-amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class-F with gate-to-drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long-range low power wireless local area network IEEE 802.11ah standard. The inductor-less design for ET supply bias reduces the chip layout size to 0.13 mm² only.