Iet Circuits Devices & Systems最新文献

This study presents a novel triple-step bias-flip rectifier with a post implementation calibration (PIC) scheme to address both the need for a general-purpose adaptable piezoelectric energy harvester (PEH) interface circuit (PEHIC) and the PVT-related issues while maintaining acceptable efficiency and a smaller inductor. Due to the PIC, the proposed circuit is adaptable to various piezoelectric materials and inductors. Using a 100-µH inductor, a 180 nm standard design kit, and an energy investing (EI) scheme, the proposed rectifier achieves a bias flip efficiency of 100%. Without EI, the proposed circuit achieves the recently reported high bias flip efficiency, that is, ɳ_flip, in the literature with a considerably smaller inductor. According to simulation results, the improvement of the designed circuit relative to the full bridge rectifier (FBR) falls within the scope of 2–3.8. Postsimulation calculations revealed that the figure of merit of adaptivity, that is, FoM_adaptivity, of the proposed circuit is approximately 83.

Restoring load following partial outages or local faults in a section of the distribution system, as addressed in this study, is crucial to minimizing service interruptions and financial damages. Reconfiguring the network is a crucial first step in load restoration. The presence of distributed generation (DG) units, in addition to the reconfiguration of the distribution network, can be very effective in the load recovery process. Therefore, in this study, the problem of reconfiguring the distribution network in the presence of DG units and charging stations of electric vehicles with the goals of reducing energy not supplied (ENS) and losses has been solved. The suggested problem is resolved by introducing and putting into practice the hybrid particle swarm optimization and shuffled frog leaping (HPSO-SFL) algorithm, which is based on hybrid swarm intelligence. The effectiveness and accuracy of the proposed method are validated using a 33-bus test system under multiple scenarios. To assess its performance, the results are compared against those reported in previous studies. Following network reconfiguration, the power losses were reduced by 45% without DG and by 77% with DG, relative to the initial system state. Furthermore, when electric vehicle charging stations (EVCSs), modeled as active loads, were included in the optimization process, power losses decreased by approximately 23% compared to the pre-reconfiguration condition.

The geometrical parameters of the fin-shaped field-effect transistor (FinFET) significantly affect the outcomes of the FinFET-based designs. Various machine learning (ML) schemes have been presented to optimize the geometrical parameters of the FinFET devices to limit the adverse effect of scaling. This paper presents the FinFET width and height optimization using the proposed hybrid particle swarm optimization algorithm-based whale optimization algorithm (HPSO-WOA). To improve device performance, the whale optimization algorithm (WOA) is utilized to find optimal geometric parameters of FinFET, such as width and height. Meanwhile, the PSO is used to optimize WOA hyperparameters. It uses various parameters such as on-state current, transconductance, subthreshold swing (SS), early voltage (V_EA), and transconductance generation factor (TGF) for analyzing the impact of fin width and height on the FinFET device. Additionally, we have analyzed the impact of the proposed parameters on the design of 6-T static random access memory (SRAM). Microwind 3.9 EDA is used to design, simulate, and improve the physical layout utilizing the FinFET 14 nm and BSIM 4 MOS modeling technique. The proposed HPSO-WOA improves 0.17% in SS, 0.62% in g_m, 0.05% in TGF, and 70.86% in optimization time over the quasi-random sequence (QRS)-WOA. However, it resulted in overall improvement of 0.90% in SS, 0.74% in g_m, 1.05% in TGF, and 173% in optimization time over traditional WOA.

The charge pump phase-locked loop (CP-PLL) is a critical component in modern mixed-signal electronics, widely used for clock generation, synchronization, and frequency synthesis in digital and wireless applications. However, its performance is significantly impacted by nonideal effects, particularly the current mismatch of the charge pump (CP) and the frequency variation of oscillator, both of which are highly sensitive to temperature fluctuations. To address these challenges, this work leverages the positive temperature coefficient (PTC) of the drain-source on-state resistance in CMOS and the negative temperature coefficient (NTC) of the magnetic tunnel junction (MTJ). Using 28 nm CMOS technology, we analyze and simulate the current mismatch of the CP across a wide temperature range, achieving a current mismatch of less than 0.3%. Furthermore, the proposed approach significantly improves the frequency stability of the ring oscillator. Simulation results validate the effectiveness of our design, demonstrating that the MTJ compensates for 90% of the output frequency drift over a temperature range from −80 to 125°C.

In this paper, an innovative approach for the performance enhancement of tunnel field-effect transistors (TFETs) is presented with the introduction of the stacked gate oxide U-shaped tunnel FET (SUTFET). This novel design incorporates a unique combination of titanium dioxide (TiO₂) and silicon dioxide (SiO₂₎ layers as stacked gate dielectrics, significantly enhancing device performance. The stacked SUTFET achieves a notable reduction in the OFF-current while delivering a substantial improvement in the ON-current and better subthreshold swing (SS). Our research explores varying the thickness of TiO₂ and SiO₂ layers effect on critical electrical parameters, including threshold voltage, ON-current, and leakage current. This study reveals that the use of TiO₂, with its superior dielectric constant compared to the conventional HfO₂, leads to exceptional current capabilities and superior control over the off current. Through detailed simulations, we demonstrate that the adjustment of dielectric thickness can further optimize SS and minimize the leakage. The findings highlight the potential of the stacked gate oxide SUTFET as a major breakthrough in the field of tunnel FETs, paving the way for advancements in high-performance and low-power electronic devices. This novel approach not only addresses key performance limitations of conventional TFET structures but also sets a new benchmark for future research and development in the semiconductor technology.

This paper proposes a high step-up converter featuring zero current (ZC) switching (ZCS) and continuous input current to enhance efficiency. The converter integrates switched capacitor and coupled inductor techniques to improve voltage gain while significantly reducing the voltage stress across the switch. Furthermore, the maximum voltage stress on the diodes remains unaffected by the increase in turn ratio, allowing for unrestricted turn ratio adjustment to boost the gain. ZCS is achieved without requiring auxiliary circuitry or extra switches. The use of pulse width modulation (PWM) for the switch simplifies the control circuit implementation. Additionally, the leakage inductance energy is efficiently absorbed by the clamping capacitor, preventing voltage spikes on the switch. Moreover, the switch source is grounded, enabling the drive circuit to be powered directly from the input. The converter is comprehensively analyzed, and both simulation results from PSPICE and experimental implementation results are presented to validate its performance. The results demonstrate a full-load efficiency of 96.2%.

This paper examines the issue of load management in electrical distribution networks, with a focus on the optimal placement of telecommunication load breaker switches (TCLBSs). The main innovation of this study lies in the introduction of a dual-objective optimization framework that simultaneously aims to minimize energy not supplied (ENS) and preserve critical loads. This approach enables network operators to prioritize switch placement based on the importance of each objective, offering a level of flexibility, and comprehensiveness not thoroughly addressed in previous studies. To solve this problem, an iterative graph-based search algorithm is employed, which dynamically identifies the optimal locations for switch installation. By leveraging graph theory, the proposed method significantly reduces computational complexity and enhances responsiveness to changing network conditions. According to simulation results on the IEEE 33-bus network, switch locations change as the priority of critical loads increases, and the proposed strategy greatly improves the reliability and performance of the power distribution network during peak demand periods. This dual-objective approach, with adjustable settings, enhances the efficiency of load management, and strengthens network dependability.

In order to solve the problems of low contrast and weak detail information of endoscope images, the image adaptive histogram detail enhancement algorithm is presented. Although the adaptive histogram equalization (AHE) algorithm has been studied in some depth, the detail enhancement algorithm is relatively complicated and difficult to implement in endoscope hardware. In order to realize the real-time and adaptive enhancement of endoscope image details on the hardware system, the AHE algorithm is improved to reduce the hardware resource consumption and time complexity. The improved algorithm selects the segmentation condition suitable for real-time image, the threshold interception, and the pipeline structure to process the low contrast endoscopic image. Xilinx’s Artix-7 chip is used to implement the hardware circuit and process images with a resolution of 640 x 480 in real time at a rate of up to 160 frames per second. The design utilizes 25K look-up tables (LUTs), 6K flip–flops, and 33 block RAMS. The experimental results show that the improved algorithm has the characteristics of fast processing speed, good detail enhancement effect, and strong portability, which can meet the requirements of real-time video processing in endoscopy.

The proposed research paper focuses on the study of fully depleted silicon (Si)-on-insulator negative capacitance metal oxide-semiconductor field-effect transistor (FDSOI-NC-MOSFET) performance for biosensor and digital circuit applications. The study mainly aims to use ferroelectric (FE) material to improve the performance and efficiency of FDSOI-NC-MOSFETs compared to conventional planar MOSFETs. Using TCAD software, the proposed device is simulated and analyzed under various parameter conditions (parameters like temperature, channel thickness, input supply voltages, and channel doping levels). Later, the proposed device is also designed for different biomolecular structures to analyze the selectivity and sensitivity behavior of the device. Sensitivity is the change in electrical characteristics in response to applied external stimuli or parameters like current and voltages. Variations in these parameters will affect the operating region of the device, thereby, the choice of parameters in achieving the best performance will depend on the operating conditions and device applications. NC-MOSFET with FE materials can obtain an acceptable on/off current ratio by lowering the off current and can achieve an adequate subthreshold swing (SS), thus, observed that the NC-MOSFET device has enhanced performance and transfer characteristics in comparison to planar MOSFET. For K = 4, at an input voltage of 0.25 V, the I_on/I_off ratio was 6.21 × 10⁵ and the sensitivity was 6.20 × 10⁷ and at 0.5 V, these values rise to 8.07 × 10⁵ and 8.073 × 10⁷, respectively. Similarly for K = 6 and at an input voltage of 0.25 V, we observed an I_on/I_off ratio is 1.5 × 10⁷ and a sensitivity of 1.52 × 10⁹. When the input voltage was increased to 0.5 V, the I_on/I_off ratio improved to 2.07 × 10⁷ and the sensitivity increased to 2.073 × 10⁹. From these analyses, it is apparent that as the K-values increase at a given input voltage, both the I_on/I_off ratio and the sensitivity also increase significantly. Finally, in this paper, we also demonstrated the implementation and simulation of digital logic gates using the proposed NC-MOSFET device, supporting circuit-level design applications.

Open-circuit faults (OCFs) in insulated gate bipolar transistors (IGBTs) within single-phase pulse width modulation (PWM) rectifiers can severely degrade system performance, leading to reduced output voltage, poor power quality, overheating, and safety risks, including electric shocks or fires. Reliable fault detection is critical for maintaining system efficiency and preventing further damage. This study presents an advanced fault detection method based on the H-infinity (H∞) approach, utilizing an extended H∞ filter to monitor system behavior and generate residual signals indicative of faults. The method effectively filters out external disturbances and system noise, minimizing false positives and enhancing detection accuracy. The proposed method was evaluated through hardware-in-the-loop (HIL) simulations that replicated real-world conditions of PWM rectifiers. Results show that the extended H∞ filter successfully detected OCFs with high accuracy and reduced false alarm rates. Performance metrics indicate a significant improvement in detection reliability compared to conventional methods. In conclusion, the H∞-based fault detection method offers a robust solution for real-time monitoring in power electronic systems. It enhances fault detection accuracy, reduces false alarms, and improves the operational safety and reliability of single-phase PWM rectifiers. Integrating this technique into power systems can mitigate risks associated with IGBT failures and ensure optimal performance under varying operational conditions.