Iet Circuits Devices & Systems最新文献

The fast Fourier transform (FFT) is widely used in digital signal processing. However, hardware implementations of the discrete Fourier transform (DFT)/FFT are limited by word length constraints, necessitating truncation, saturation, and scaling operations to balance hardware resources and computational performance. The choice of a suitable scaling vector significantly affects FFT efficiency. This paper introduces a novel estimation model for FFT error power, accounting for both quantization and saturation errors. Based on this model, we propose a dynamic programming (DP)-based scaling vector search scheme to reduce the search space and computational complexity. After 1000 experiments, the model demonstrated a mean and variance of relative error in signal-to-noise ratio (SNR) of 0.063 and 0.35, proving its effectiveness. In a case study of a 1024-point FFT, our model accurately estimated error power. While the exhaustive search yielded an optimal SNR of 65.91 dB, our method reduced the search space by 3600 times, with only a 0.3 dB loss in SNR. In a 256-point FFT hardware implementation, performance improved by over 10 dB. Our scheme achieves SNR performance comparable to other methods when bit width is fixed and superior SNR when bit width is variable. This approach offers guidance for selecting scaling vectors in FFT hardware design.

This paper presents a software-controlled offset-cancelation technique for analog multipliers that relies on the Bayesian-optimization algorithm. The capability of the technique was investigated on a test multiplier, which was developed for future use in machine learning (ML) accelerators whose convergence is sensitive to process-variation-induced DC offsets. By adjusting the multiplier biasing voltages, the proposed Bayesian-optimization-based method was able to reduce the offset within ±1.8 mV from an uncorrected maximum offset of 10.6 mV. In addition to reducing offsets, the measurements of the 65-nm CMOS multiplier also showed an average linearity-error improvement of nearly 10%, from 12.2% prior to offset correction to 2.2% after correction. We demonstrate that the proposed offset correction improved the learning outcome accuracy for MNIST dataset digit classification from approximately 10% to 90%.

In this article, a phase shifter circuit designed for next-generation communication systems was presented. Operating at 4.5–5.5 GHz, the circuit in question is a 3-bit all-pass LC lattice, which was initially analyzed using MATLAB. Following this analysis, the circuit was set up and simulated in advanced design system (ADS) using numerical values derived from the MATLAB simulations. A switch capacitor is employed as the switching element within the circuit. For phase shifts of 45°, 90°, and 180°, the phase errors are 3°, 9°, and 0°, respectively, while the power losses are 1.5 dB, 3 dB, and 1.9 dB, respectively.

In this paper, various D flip-flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional-bridging FF (CBFF)-S, self-shut-off pulsed latch (SSPL), retentive true signal phased clock (R-TSPC), mTGFF, mC2MOS, FS-TSPC-DET-FF, and P-FF, are briefly reviewed for different architectures and technologies, with the trade-off between the various performance parameters discussed in this paper. Comparative analysis is done for the selected DFFs on technology, supply voltage, set-up time, delay, power consumption, and area. Reliability effects on DFFs and aging effect on FFs are reviewed for timing yield-aware lifetime reliability (TYR) based on the process variations (PVs) and bias temperature instability (BTI). A brief review on applications of DFFs in internet of thing (IoT) devices and artificial intelligence (AI), such as frequency divider, dual-modulus prescaler, time-to-digital converter (TDC), shifter, and synchronizer, is also presented.

This study presents a novel triple-step bias-flip rectifier with a post implementation calibration (PIC) scheme to address both the need for a general-purpose adaptable piezoelectric energy harvester (PEH) interface circuit (PEHIC) and the PVT-related issues while maintaining acceptable efficiency and a smaller inductor. Due to the PIC, the proposed circuit is adaptable to various piezoelectric materials and inductors. Using a 100-µH inductor, a 180 nm standard design kit, and an energy investing (EI) scheme, the proposed rectifier achieves a bias flip efficiency of 100%. Without EI, the proposed circuit achieves the recently reported high bias flip efficiency, that is, ɳ_flip, in the literature with a considerably smaller inductor. According to simulation results, the improvement of the designed circuit relative to the full bridge rectifier (FBR) falls within the scope of 2–3.8. Postsimulation calculations revealed that the figure of merit of adaptivity, that is, FoM_adaptivity, of the proposed circuit is approximately 83.

Restoring load following partial outages or local faults in a section of the distribution system, as addressed in this study, is crucial to minimizing service interruptions and financial damages. Reconfiguring the network is a crucial first step in load restoration. The presence of distributed generation (DG) units, in addition to the reconfiguration of the distribution network, can be very effective in the load recovery process. Therefore, in this study, the problem of reconfiguring the distribution network in the presence of DG units and charging stations of electric vehicles with the goals of reducing energy not supplied (ENS) and losses has been solved. The suggested problem is resolved by introducing and putting into practice the hybrid particle swarm optimization and shuffled frog leaping (HPSO-SFL) algorithm, which is based on hybrid swarm intelligence. The effectiveness and accuracy of the proposed method are validated using a 33-bus test system under multiple scenarios. To assess its performance, the results are compared against those reported in previous studies. Following network reconfiguration, the power losses were reduced by 45% without DG and by 77% with DG, relative to the initial system state. Furthermore, when electric vehicle charging stations (EVCSs), modeled as active loads, were included in the optimization process, power losses decreased by approximately 23% compared to the pre-reconfiguration condition.

The geometrical parameters of the fin-shaped field-effect transistor (FinFET) significantly affect the outcomes of the FinFET-based designs. Various machine learning (ML) schemes have been presented to optimize the geometrical parameters of the FinFET devices to limit the adverse effect of scaling. This paper presents the FinFET width and height optimization using the proposed hybrid particle swarm optimization algorithm-based whale optimization algorithm (HPSO-WOA). To improve device performance, the whale optimization algorithm (WOA) is utilized to find optimal geometric parameters of FinFET, such as width and height. Meanwhile, the PSO is used to optimize WOA hyperparameters. It uses various parameters such as on-state current, transconductance, subthreshold swing (SS), early voltage (V_EA), and transconductance generation factor (TGF) for analyzing the impact of fin width and height on the FinFET device. Additionally, we have analyzed the impact of the proposed parameters on the design of 6-T static random access memory (SRAM). Microwind 3.9 EDA is used to design, simulate, and improve the physical layout utilizing the FinFET 14 nm and BSIM 4 MOS modeling technique. The proposed HPSO-WOA improves 0.17% in SS, 0.62% in g_m, 0.05% in TGF, and 70.86% in optimization time over the quasi-random sequence (QRS)-WOA. However, it resulted in overall improvement of 0.90% in SS, 0.74% in g_m, 1.05% in TGF, and 173% in optimization time over traditional WOA.

The charge pump phase-locked loop (CP-PLL) is a critical component in modern mixed-signal electronics, widely used for clock generation, synchronization, and frequency synthesis in digital and wireless applications. However, its performance is significantly impacted by nonideal effects, particularly the current mismatch of the charge pump (CP) and the frequency variation of oscillator, both of which are highly sensitive to temperature fluctuations. To address these challenges, this work leverages the positive temperature coefficient (PTC) of the drain-source on-state resistance in CMOS and the negative temperature coefficient (NTC) of the magnetic tunnel junction (MTJ). Using 28 nm CMOS technology, we analyze and simulate the current mismatch of the CP across a wide temperature range, achieving a current mismatch of less than 0.3%. Furthermore, the proposed approach significantly improves the frequency stability of the ring oscillator. Simulation results validate the effectiveness of our design, demonstrating that the MTJ compensates for 90% of the output frequency drift over a temperature range from −80 to 125°C.

In this paper, an innovative approach for the performance enhancement of tunnel field-effect transistors (TFETs) is presented with the introduction of the stacked gate oxide U-shaped tunnel FET (SUTFET). This novel design incorporates a unique combination of titanium dioxide (TiO₂) and silicon dioxide (SiO₂₎ layers as stacked gate dielectrics, significantly enhancing device performance. The stacked SUTFET achieves a notable reduction in the OFF-current while delivering a substantial improvement in the ON-current and better subthreshold swing (SS). Our research explores varying the thickness of TiO₂ and SiO₂ layers effect on critical electrical parameters, including threshold voltage, ON-current, and leakage current. This study reveals that the use of TiO₂, with its superior dielectric constant compared to the conventional HfO₂, leads to exceptional current capabilities and superior control over the off current. Through detailed simulations, we demonstrate that the adjustment of dielectric thickness can further optimize SS and minimize the leakage. The findings highlight the potential of the stacked gate oxide SUTFET as a major breakthrough in the field of tunnel FETs, paving the way for advancements in high-performance and low-power electronic devices. This novel approach not only addresses key performance limitations of conventional TFET structures but also sets a new benchmark for future research and development in the semiconductor technology.

This paper proposes a high step-up converter featuring zero current (ZC) switching (ZCS) and continuous input current to enhance efficiency. The converter integrates switched capacitor and coupled inductor techniques to improve voltage gain while significantly reducing the voltage stress across the switch. Furthermore, the maximum voltage stress on the diodes remains unaffected by the increase in turn ratio, allowing for unrestricted turn ratio adjustment to boost the gain. ZCS is achieved without requiring auxiliary circuitry or extra switches. The use of pulse width modulation (PWM) for the switch simplifies the control circuit implementation. Additionally, the leakage inductance energy is efficiently absorbed by the clamping capacitor, preventing voltage spikes on the switch. Moreover, the switch source is grounded, enabling the drive circuit to be powered directly from the input. The converter is comprehensively analyzed, and both simulation results from PSPICE and experimental implementation results are presented to validate its performance. The results demonstrate a full-load efficiency of 96.2%.