Iet Circuits Devices & Systems最新文献

A compact frequency reconfigurable beam switching antenna based on a single-layer frequency selective face (FSS) is proposed in this paper. The proposed antenna consists of a dual-band dipole antenna and a single-layer FSS with hexagonally arrangement. The omnidirectional radiation pattern of the dipole antenna designed as a radiation source and surrounded by the FSS can be converted into directional radiation pattern sweeping along the entire azimuthal plane at two single frequency of 2.4 or 5 GHz. The frequency selection is achieved by controlling the diode state of the FSS unit, and the beam switching is realised by a specific combination of electromagnetic wave reflection or transmission from the hexagonal FSS. The novelty lies in applying the hexagonal arrangement to a dual single-frequency single-layer FSS unit. This will not destroy the reflection or transmission characteristics of the FSS unit, but also contribute to reduce the antenna size and achieve a low cost. To validate the design, a prototype is fabricated and measured. The single-layer FSS antenna with a volume of 57 mm × 57 mm × 58.5 mm can be scanned in 12 steps along the azimuth plane at 2.4 and 5 GHz, respectively.

The authors’ present a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with β-Ga₂O₃ , which is a large bandgap semiconductor (β-LDMOSFET), for increasing breakdown voltage (V_BR) and power figure of merit. The fundamental purpose is to use a β-Ga₂O₃ semiconductor instead of silicon material due to its large breakdown field. The characteristics of β-LDMOSFET are analysed to those of standard LDMOSFET, such as V_BR, ON-resistance (R_ON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gate-drain capacitance (C_GD), gate-source capacitance (C_GS), transit frequency (f_T), and maximum frequency of oscillation (f_MAX) have been investigated. The β-LDMOSFET structure outperforms performance in the V_BR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested β-LDMOSFET has R_ON ~ 2.3 mΩ.cm⁻² and increased the PFOM (V_BR²/R_ON) to 108.6 MW/cm². All the simulations are done with TCAD and simulation models are calibrated with the experimental data.

The research on LCC resonant converters has become increasingly popular since the application of the zero-voltage switching can improve the transmission ability and ensure the high efficiency of the power supplies. In this article, a novel quasi-definite frequency-based modulation control method to extend the excellent properties of LCC resonators to a wide range of powers is introduced. By adjusting the frequency and phase in a bidirectional manner in accordance with the design law, excellent output performance can be maintained over a wide power range, which is overcome by adjusting the switching frequency and phase separately in conventional modulation methods. In order to justify the effectiveness of the proposed modulation control method, a simulation and experimental platform of LCC resonators using the proposed modulation method was performed. Simulation and experimental results can effectively demonstrate the performance of the proposed modulation control method for a variety of input voltage and output power cases, and the efficiency of the LCC converters will be improved in higher power systems.

The rapid development of night tourism economy has made people's demand for night scene lighting in architectural blocks increasing, and the night scene lighting situation of urban architectural blocks has gradually received people's attention and attention. Achieving good night lighting visual effects of building blocks can not only meet the needs of residents for entertainment and consumption at night, but also beautify the image of blocks and promote the economic development of building blocks. However, due to the unreasonable planning and management of the night scene lighting design of architectural blocks in some areas, improper application of night scene lighting, and overly commercial night scene lighting effects, it affects people's normal night activity needs and has a negative impact on the long-term block economy of the region. Faced with this situation, the night lighting of architectural blocks and its problems is studied and photos are identified with high lighting visual effect evaluation using multi-target identification and data processing to construct a night lighting visual evaluation system for architectural blocks, and also an experimental study of the visual evaluation system is conducted. The results show that the overall visual suitability evaluation support rate of the respondents for the night scene lighting of architectural blocks is 95.64%, and the visual evaluation system proposed in this paper is reasonable and effective, which is conducive to promoting the improvement of the visual effect of night scene lighting in architectural blocks.

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V_DD. This way, in a single-V_DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.

A quarter-rate PAM-4 FFE employing INCC 1UIPG is implemented in 65 nm CMOS. The proposed INNC 1UIPG reduces the average transition time by ~20%, saving clocking power consumption by ~1.5X, lowering jitter amplification by about 2~5 dB compared with previous works. Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128Gbps PAM-4 data rate with a 0.014 mm² area.

A multi-string LED lamp driver is presented involving a boost converter and a multi-output CLL resonant converter as the first and second stages, respectively. The CLL resonant converter works in a fixed resonant frequency, and output currents are controlled by the boost converter regulated by the Weighting Factor control method. Also, the boost converter improves and controls its input voltage. Since CLL resonant converters operate at fixed resonant frequency, primary-side MOSFETs can achieve zero voltage switching, while secondary-side rectifier diodes achieve zero current switching. A prototype of the proposed system was constructed to verify the theoretical results by practical implementation. Also, the general features of the proposed structure were compared with some other similar works. Results confirmed the accuracy and favourable performance of the proposed system. In fact, the proposed LED driver achieved good current balancing in a wide range of input voltage and unbalanced loads making the structure potentially suitable for application in solar home systems (SHS).

Retraction: [Xiaojian Wang, Zixuan Wang, Xiaoye Sun, Multi-mode urban rail transit and spatial coordinated development based on deep learning system, IET Circuits, Devices & Systems 2023 (https://doi.org/10.1049/cds2.12144)].

The above article from IET Circuits, Devices & Systems, published online on 10 January 2023 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.

A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S₁₁ and S₂₂ parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.

An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.