Iet Circuits Devices & Systems最新文献

Antennas constrained to platforms that require miniaturisation, significantly smaller than the wavelength of the desired frequency, are inefficient radiators and limited to narrowband operations. To overcome these limitations, a technique called direct antenna modulation (DAM), is incorporated with electrically small antennas to enable transmission of high-bandwidth signals through narrowband antennas. DAM utilises switching circuitry to directly modulate the antenna at its corresponding peak energy moments all while being synchronised to the input signal, yet previous iterations were susceptible to low transmit powers due to limitations in the switching network's power handling capability and tremendous coupling between transistor ports that results in an ambiguous switching signal at the gate. A frequency shift keyed (FSK) DAM antenna topology is proposed, which is capable of high-power transmission through a geometrically symmetrical switching circuitry integrating pairs of complementary GaN transistors. The symmetry assists in removing coupling among transistor ports to effectively switch the transistors OFF and ON without regard to the input RF power. The authors’ theoretical analysis agrees with our simulations and far-field measurements which show the FSK DAM antenna topology is capable of transmit powers up to −1 dBm given a 42 dBm of input RF power.

In this paper, a latch-based energy-efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre-amplifier and latch. The latch stage is designed for the main purpose of low-power consumption and high-speed performances. The proposed speed-up technique for the latch structure controls the threshold voltage (V_th) of the cross-coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double-tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double-tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed-up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high-resolution (up to 12 bit) and high-speed low-power analogue-to-digital converter applications. Moreover, the effects of the non-ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte-Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

This work investigates the optical properties of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) using the transmittances of colour filters and the spectra of commercialised white light-emitting diodes (LEDs). The ratios of the measured photocurrents obtained using the TFTs that are covered and are not covered colour filters are related to the effective illumination from white LEDs with different colour temperatures that pass through the colour filters. A new factor that is based on these ratios of photocurrents is proposed to evaluate the output characteristics of optical sensors with our previously developed white-light photocurrent gating (WPCG) structure. The analytical results demonstrate that the proposed factor and the output voltages of the WPCG structure are highly correlated with each other, favouring the optimisation of the design parameters to realise an optical sensor that is highly reliable under diverse conditions for use in large interactive displays.

A frequency generator based on the forward coupler principle is proposed. The proposed design, intended for high-frequency applications, uses Half-Mode Substrate Integrated Waveguide structure to realise the forward coupler. It thus achieves compactness, requiring approximately half the area compared to Substrate Integrated Waveguide structures, and supports non Transverse Electromagnetic (TEM) functionality. The non-TEM environment provides the flexibility to use the frequency generator for chipless Radio Frequency Identification readers in the sub-GHz band and mm-wave range. Full-wave simulations and the subsequent measurements on a prototype developed on Rogers 3006 substrate performed for the forward coupler resonators and frequency generator validate the proposed design concept.

The trust, authenticity and integrity of Internet-of-Things (IoT) systems are heavily reliant on Physical Unclonable Functions (PUFs) and True random number generators (TRNGs). The PUF and TRNG produce device intrinsic digital signatures and random binary sequences, which are used for cryptographic key generation, key agreement/exchange, device authentication, cloning prevention etc. This article reports an efficient Field Programmable Gate Array (FPGA)-based realization of elliptic curve Menezes-Qu-Vanstone (ECMQV)-authenticated key agreement protocol using PUF and TRNG with very competitive area-throughput trade-offs. The key agreement protocols, which establish a shared secret key between two IoT devices, make use of PUF and TRNG primitives for the long- and short-term secret keys generation while the elliptic curve is employed for public key generated from the corresponding secret key. The performance of the protocol is investigated on FPGAs. The authors' implementation of the ECMQV protocol takes 1.802 ms using 18852 slices on Artix-7 FPGA.

Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three-clock cycle, divide-and-conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non-idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re-designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high-security SM algorithm which involves random points to resist side-channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state-of-the-art designs reported in the literature in terms of speed and area-time product metrics.

Severe harmonics propagation in power systems may result in increased power losses and equipment damages. In this paper, an elliptic formula is derived to analyse the harmonic spatial distribution not only at the substations but also along the power lines or cables and to give a system-wide overview of harmonic levels. It is observed that harmonic distortion along power lines can be higher than that at the busbars and the maximum amplitude of harmonic voltage and current denoted as weak positions along power lines depends on the steady-state harmonic angle difference of voltage and current at busbars, the length of power lines, and the harmonic order. All cases are modelled in detail by analytical geometry and analysed in MATLAB. In this regard, a method to identify the weak positions in terms of maximum harmonic levels in a power system is presented, and its corresponding harmonic orders are determined. The accuracy of the model is tested using time-domain simulations in PSCAD/EMTDC.

A full-wave rectifier based on a modified voltage differencing transconductance amplifier-MVDTA and four n-MOS transistors (or inverting full-wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude-waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non-ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution.

An incorrect mistake that the DC bias resistance cannot change the oscillation frequency exists for the traditional formula of the Wien-Bridge oscillator. From the rigorous hardware experiments and theoretical proofs in this study, the proposed new formula exploits the fact that the oscillation frequency of the Wien-Bridge oscillator is indeed determined by the DC bias resistance. The feedback theory and Barkhausen criterion are often utilised to address the oscillating formula of the Wien-Bridge oscillator for traditional approaches. However, the steps of the feedback theory are complicated, and its severe shortcoming is the utilisation of Kirchhoff's law. The traditional Barkhausen formula is only necessary but not sufficient for the Wien-Bridge oscillator. Hence, the oscillator with a feedback device, which fulfils the Barkhausen criterion does not necessarily oscillate at a frequency and then this fact will make the Barkhausen criterion impractical. This study applies our series research Chen's Electric Unifying Approach to overcome the serious shortcomings of the traditional Barkhausen method and yields a necessary and sufficient oscillation formula for the Wien-Bridge oscillator. Another important feature of our proposed method is that the oscillation condition is effective for a range value, and it can solve the impact caused by the change in environmental factors.

Because radiation is essential in high-frequency circuits, such as those used in metamaterials and plasmonics, the investigation of radiation loss is important. This study describes the characteristics of radiation loss, which is a radiation reaction in circuits with retarded electromagnetic couplings. The structure of wired metallic spheres is used to demonstrate metamaterial equivalent circuits, where charges and current exist on the spheres and wires, respectively. An inductance matrix and a potential coefficient matrix with retarded electromagnetic couplings are defined to address the radiation reaction. Subsequently, based on the topology of the wires and spheres, an equivalent circuit equation with retardation is formulated to discuss the losses in the resonant circuit caused by the inductive and capacitive elements. Thereafter, the relationship between the resonant frequency and radiation loss caused by the retarded couplings is demonstrated and the difference between the retarded couplings and couplings with transmission lines is clarified. Furthermore, we indicate that retarded coupling generates singularity on a dispersion curve for a one-dimensional array of resonant circuits. Thus, the circuit with retarded couplings generates novel characteristics of radiation reactions that are not represented by the circuit without retardation. This circuit analysis is expected to afford new aspects in studies on topics, such as metamaterials and plasmonics.