Iet Circuits Devices & Systems最新文献

The two key problems of the in-band ripples and out-of-band suppression are proposed in the design of the SAW yarn tension sensor and the methods of decreasing them are achieved. The unbalanced split-electrode interdigital transducers (IDT) are designed so that the total phase of the regenerated reflection wave and mass load feedback is close to 180°, leading to an effective reduction of the in-band ripples effect characterised by the sensor frequency response. The engraved bi-directional slots on the back of the substrate can block the propagation path of the bulk acoustic wave (BAW) to a certain extent, reducing the influence of BAW propagation and suppressing the out-of-band suppression of the frequency response. The experimental results show that the SAW yarn tension sensor with the unbalanced split-electrode IDT can reduce the in-band ripples from 23.34 to 0.93 dB, and the engraved bi-directional slots can suppress the out-of-band suppression from 28.03 to 7.71 dB.

A CMOS baseband-active-feedback receiver frontend with passive voltage-commutating mixers is proposed. The active feedback baseband enables in-band signal amplification and out-of-band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage-commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in-band and out-of-band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm², which is suitable for the low-power application of handheld terminals.

This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10⁻³. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.

With the development of semiconductor technology, digital pixel has received widespread attention and is applied to various electronic products. However, due to the limitation of area, it forms a challenging task to design a digital pixel with multiple modes. In this paper, a pulse width modulation based digital pixel is proposed, which is compatible with five different modes. By using the multi-purpose capacitors and static random access memory structure, it can realise multi-mode conversion in an equivalent area to that of the single mode digital pixel without performance degradation. Furthermore, a corresponding logic control method is developed, such that the integrity of the frame data is ensured during mode conversion. The simulation result of our proposed digital pixel in Tower Jazz 0.18 μm process shows that in the bright field it achieves a dynamic range of 67 dB. In the dark field, it achieves a conversion gain up to 13.91 μV/e−, with input noise of 37.89 e−per pixel after correlated double sampling.

This paper presents a new structure consisting of a silicon PIN junction with high breakdown voltage and low dark current with two Guard rings. To achieve the optimal structure, the effect of the parameters on the breakdown voltage and the dark current of the device has been investigated and simulated. The intrinsic thickness and impurity, the penetration depth of the active area and guard rings, location and number of guard rings, thickness, and distance between guard rings are the effective parameters of the device's breakdown voltage and dark current. In the proposed structure by placing two guard rings around the active area, the results show that an electric field is distributed at the edge of the active area between the guard rings, which leads to an increase of 292.62 V in breakdown voltage compared to the device without a guard ring.

This paper investigates the issue of bipartite consensus for coupled harmonic oscillators under the cooperation-competition network topology while considering measurement noise. The concept of bipartite consensus in mean square is established for networked harmonic oscillator systems. In this sense, two consensus algorithms that only use sampled velocity data on the agents in a network are given. Based on the specific structure of the Laplacian matrix related to the cooperation-competition network topology, some sufficient conditions are given to ensure the realisation of the bipartite consensus of the coupled harmonic oscillators. Finally, three examples are provided to illustrate the corresponding theoretical results.

The interactions between poly (3,4-ethylene dioxythiophene) poly (styrenesulfonate) (PEDOT:PSS) and small gas molecules are studied using non-equilibrium Green's function formalism based on the density functional theory. The proposed method is implemented in the Tran SIESTA code to benefit from the potential application of PEDOT:PSS as a gas sensor. The results show that doping with nanoparticles can drastically improve the sensitivity of polymer-based chemical gas sensors. Moreover, among various PEDOT:PSS doping materials, silver nanoparticles have an appropriate response to ammonia, while platinum shows the best response to carbon dioxide. The numerical results can be useful to design PEDOT:PSS-based gas sensors.

A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

This paper presents a high-performance processor for optimal ate pairing on Barreto–Naehrig curves over 256-bit prime field at the 128-bit security level. The proposed design exploits parallelism and pipeline at different levels of the pairing algorithm, including the prime field operation, the second extension of the prime field $��\left(F_{p^2}\right)�$ operation, and operations based on $��F_{p^2}�$. The proposed design needs 37,271 cycles to compute optimal ate pairings. The results of implementation on a 90 nm standard cell library show that the proposed design consumes 751k gates and can compute the respective pairings in 0.10 ms. This result is at least 60 percent better than related reports in terms of normalised area-time on ASIC. Moreover, the design is also implemented on Xilinx Virtex-6 platform, which consumes 25K Slices and 240 DSPs and takes 0.52 ms to calculate one optimal ate pairing operation.

A 1.2 kV 4H-SiC planar power MOSFET with a low-K dielectric in central gate (LK-MOS) is proposed in this paper. The LK-MOS features a P+ shielding region and a thick low-K dielectric layer under the central gate. The insulation layer capacitance is reduced by the thick low-K dielectric, while the depletion layer capacitance is decreased due to the reduced gate-to-drain overlap. The LK-MOS is demonstrated to have 97.8%, 70.6%, and 52.2% lower HF-FOM (R_on × C_gd), and 98.9%, 97.4%, and 69.4% lower HF-FOM (R_on × Q_gd), when compared with that of the conventional MOSFET (C-MOS), Buffered-Gate MOSFET (BG-MOS) and Thick Central Oxide MOSFET (TCOX-MOS), respectively. Besides, the LK-MOS can also have 16.8%, 5.9% lower C_gs, and 19.9%, 12.4% lower Q_gs compared with that of BG-MOS and TCOX-MOS.