A multi-string LED lamp driver is presented involving a boost converter and a multi-output CLL resonant converter as the first and second stages, respectively. The CLL resonant converter works in a fixed resonant frequency, and output currents are controlled by the boost converter regulated by the Weighting Factor control method. Also, the boost converter improves and controls its input voltage. Since CLL resonant converters operate at fixed resonant frequency, primary-side MOSFETs can achieve zero voltage switching, while secondary-side rectifier diodes achieve zero current switching. A prototype of the proposed system was constructed to verify the theoretical results by practical implementation. Also, the general features of the proposed structure were compared with some other similar works. Results confirmed the accuracy and favourable performance of the proposed system. In fact, the proposed LED driver achieved good current balancing in a wide range of input voltage and unbalanced loads making the structure potentially suitable for application in solar home systems (SHS).
{"title":"A combined capacitor current balancing method with weighting factor control for multi-string LED drivers","authors":"Hajar Sedghi, Mohammad Sarvi","doi":"10.1049/cds2.12145","DOIUrl":"https://doi.org/10.1049/cds2.12145","url":null,"abstract":"<p>A multi-string LED lamp driver is presented involving a boost converter and a multi-output CLL resonant converter as the first and second stages, respectively. The CLL resonant converter works in a fixed resonant frequency, and output currents are controlled by the boost converter regulated by the Weighting Factor control method. Also, the boost converter improves and controls its input voltage. Since CLL resonant converters operate at fixed resonant frequency, primary-side MOSFETs can achieve zero voltage switching, while secondary-side rectifier diodes achieve zero current switching. A prototype of the proposed system was constructed to verify the theoretical results by practical implementation. Also, the general features of the proposed structure were compared with some other similar works. Results confirmed the accuracy and favourable performance of the proposed system. In fact, the proposed LED driver achieved good current balancing in a wide range of input voltage and unbalanced loads making the structure potentially suitable for application in solar home systems (SHS).</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2023-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12145","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50120596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Retraction: [Xiaojian Wang, Zixuan Wang, Xiaoye Sun, Multi-mode urban rail transit and spatial coordinated development based on deep learning system, IET Circuits, Devices & Systems 2023 (https://doi.org/10.1049/cds2.12144)].
The above article from IET Circuits, Devices & Systems, published online on 10 January 2023 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.
收回:[王晓建,王梓轩,孙晓烨,基于深度学习系统的多模式城市轨道交通与空间协同发展,IET电路、设备与系统2023(https://doi.org/10.1049/cds2.12144)]。来自IET Circuits,Devices&;《系统》于2023年1月10日在威利在线图书馆(wileyonlinelibrary.com)在线出版,经主编Harry E.Ruda、工程与技术学会(IET)和John Wiley and Sons有限公司同意撤回。本文作为客座编辑特刊的一部分出版。经过调查,IET和该杂志确定,这篇文章没有按照该杂志的同行评审标准进行评审,有证据表明,该特刊的同行评审过程受到了系统的操纵。因此,我们不能保证内容的完整性或可靠性。因此,我们决定收回这篇文章。提交人已被告知撤回的决定。
{"title":"Retracted: Multi-mode urban rail transit and spatial coordinated development based on deep learning system","authors":"Xiaojian Wang, Zixuan Wang, Xiaoye Sun","doi":"10.1049/cds2.12144","DOIUrl":"https://doi.org/10.1049/cds2.12144","url":null,"abstract":"<p>Retraction: [Xiaojian Wang, Zixuan Wang, Xiaoye Sun, Multi-mode urban rail transit and spatial coordinated development based on deep learning system, <i>IET Circuits, Devices & Systems</i> 2023 (https://doi.org/10.1049/cds2.12144)].</p><p>The above article from <i>IET Circuits, Devices & Systems</i>, published online on 10 January 2023 in Wiley Online Library (wileyonlinelibrary.com), has been retracted by agreement between the Editor-in-Chief, Harry E. Ruda, the Institution of Engineering and Technology (the IET) and John Wiley and Sons Ltd. This article was published as part of a Guest Edited special issue. Following an investigation, the IET and the journal have determined that the article was not reviewed in line with the journal’s peer review standards and there is evidence that the peer revie process of the special issue underwent systematic manipulation. Accordingly, we cannot vouch for the integrity or reliability of the content. As such we have taken the decision to retract the article. The authors have been informed of the decision to retract.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50127535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.
{"title":"A PVT resilient true-time delay cell","authors":"Ahmad Yarahmadi, Abumoslem Jannesari","doi":"10.1049/cds2.12143","DOIUrl":"https://doi.org/10.1049/cds2.12143","url":null,"abstract":"<p>A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S<sub>11</sub> and S<sub>22</sub> parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12143","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50146407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose
An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.
{"title":"A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process","authors":"Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose","doi":"10.1049/cds2.12141","DOIUrl":"https://doi.org/10.1049/cds2.12141","url":null,"abstract":"<p>An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and power-delay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.3,"publicationDate":"2023-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12141","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50146406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new method for finding closed-form time-domain solutions of linear time-invariant (LTI) systems with arbitrary periodic input signals is presented. These solutions, unlike those obtained based on the conventional Fourier-phasor method, have a finite number of terms in one period. To implement the proposed method, the following steps are carried out: (1) For a given system, represented by a transfer function, an impulse response, a block diagram etc., the governing differential equation relating the output of the system,