Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115975
Nanditha Gajanur , Mohammad A. Abbaszada , Shantanu Gupta , Sudip K. Mazumder
The reliability of semiconductor switches in single-stage differential-mode solid-state transformers (DM-SSTs) has not been systematically evaluated under soft-switching operation and realistic grid conditions. This paper presents a switch-level reliability analysis for soft-switched and hard-switched DM-SST configurations by integrating converter-specific power loss modeling with empirical lifetime prediction. Analytical derivation of device current profiles specific to the DM-SST is used to characterize electrothermal stress, which is then mapped to lifetime using degradation models obtained from power cycling tests (PCTs). Applied to realistic SST load profiles and grid voltage variations, this approach provides a probabilistic prediction of switch lifetime for the DM-SST. Lifetime estimates for both SiC MOSFETs and Si IGBTs are presented, offering insight into device degradation under converter operating conditions. The results quantify the reliability benefits of soft switching in single-stage SSTs, highlighting how switching dynamics influence long-term switch degradation.
{"title":"Evaluating switch lifetime in soft-switched single-stage differential-mode SST","authors":"Nanditha Gajanur , Mohammad A. Abbaszada , Shantanu Gupta , Sudip K. Mazumder","doi":"10.1016/j.microrel.2025.115975","DOIUrl":"10.1016/j.microrel.2025.115975","url":null,"abstract":"<div><div>The reliability of semiconductor switches in single-stage differential-mode solid-state transformers (DM-SSTs) has not been systematically evaluated under soft-switching operation and realistic grid conditions. This paper presents a switch-level reliability analysis for soft-switched and hard-switched DM-SST configurations by integrating converter-specific power loss modeling with empirical lifetime prediction. Analytical derivation of device current profiles specific to the DM-SST is used to characterize electrothermal stress, which is then mapped to lifetime using degradation models obtained from power cycling tests (PCTs). Applied to realistic SST load profiles and grid voltage variations, this approach provides a probabilistic prediction of switch lifetime for the DM-SST. Lifetime estimates for both SiC MOSFETs and Si IGBTs are presented, offering insight into device degradation under converter operating conditions. The results quantify the reliability benefits of soft switching in single-stage SSTs, highlighting how switching dynamics influence long-term switch degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115975"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115981
Yan Ma , Majiaqi Wu , Lianqiao Yang
Fan-out wafer-level packaging (FO-WLP), as a breakthrough advanced packaging technology, achieves high density interconnections by embedding chips into epoxy mold compound (EMC) and forming redistribution layers outside the die area. However, die shift, which is a slight displacement of the die from its intended position, poses a significant challenge during the molding process, affecting alignment and yield. This study systematically analyzes the effects of warpage, thermal expansion/contraction, EMC curing shrinkage and fluid drag force on die shift through multi-physics coupling simulations and numerical computation. It quantifies the contributions of thermal and fluid effects to die shift under different EMC viscosities and thicknesses. The results indicate that thermal effects are the dominant factor causing die shift; fluid effects become significant only under high-viscosity conditions, with a maximum contribution of approximately 30 %. As EMC thickness increases, the peak total shift moves toward the wafer edge, while high viscosity shifts it closer to the center. Thinner EMC exacerbates warpage but reduces die shift, whereas thicker EMC has the opposite effect. This study provides critical insights for optimizing process parameters, controlling die shift, and enhancing packaging reliability.
{"title":"Multi-physics coupling simulation and numerical computation of die shift in fan-out wafer-level packaging","authors":"Yan Ma , Majiaqi Wu , Lianqiao Yang","doi":"10.1016/j.microrel.2025.115981","DOIUrl":"10.1016/j.microrel.2025.115981","url":null,"abstract":"<div><div>Fan-out wafer-level packaging (FO-WLP), as a breakthrough advanced packaging technology, achieves high density interconnections by embedding chips into epoxy mold compound (EMC) and forming redistribution layers outside the die area. However, die shift, which is a slight displacement of the die from its intended position, poses a significant challenge during the molding process, affecting alignment and yield. This study systematically analyzes the effects of warpage, thermal expansion/contraction, EMC curing shrinkage and fluid drag force on die shift through multi-physics coupling simulations and numerical computation. It quantifies the contributions of thermal and fluid effects to die shift under different EMC viscosities and thicknesses. The results indicate that thermal effects are the dominant factor causing die shift; fluid effects become significant only under high-viscosity conditions, with a maximum contribution of approximately 30 %. As EMC thickness increases, the peak total shift moves toward the wafer edge, while high viscosity shifts it closer to the center. Thinner EMC exacerbates warpage but reduces die shift, whereas thicker EMC has the opposite effect. This study provides critical insights for optimizing process parameters, controlling die shift, and enhancing packaging reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115981"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115985
Osman KAHVECİ , Muh RUSDI , Abdullah AKKAYA , Enise AYYILDIZ
Copper conductive thin films or components in microelectronic devices face significant corrosion challenges that compromise long-term reliability. This study presents a comprehensive investigation of hafnium dioxide (HfO₂) as a protective barrier layer deposited by RF magnetron sputtering at varying thicknesses (150 and 300 nm) on copper substrates for possible microelectronic applications. Multi-technique characterization methods, including SEM-EDX, AFM, XRD, FTIR, UV–Vis spectroscopy, contact angle measurements, potentiodynamic polarization, and electrochemical impedance spectroscopy (EIS), were employed to establish structure, property, and performance relationships. EDX results show that the addition of an HfO₂ layer significantly modified the surface morphology, especially on presence of 300 nm HfO₂ layer, so that the surface appears continuous and uniform. This is also supported by the FTIR analysis results, which indicate the presence of the strongest HfO and Hf-O-Hf vibrational bonds, thereby confirming the formation of an HfO₂ layer on the Cu surface. AFM results show an increase in surface topography roughness, caused by island-type growth (Volmer-Weber), as the thickness of the HfO₂ layer increases. The XRD results for un-coated sample shows sharp and clear diffraction peaks and indicates face-centered cubic (FCC) phase pattern of pure Cu nanoparticles. When the HfO2 layer added Cu layer, XRD pattern shows the formation of a broad hump in the range of 2θ ≈ 28°–35° and HfO2 layer formed is in the amorphous state. These results are correlated with the contact angle test results. UV–Vis results show that 300 nm HfO₂ coted films has the highest transmittance value across the entire wavelength range, as well as the lowest absorbance value. The 300 nm HfO₂ coating demonstrated optimal corrosion protection with 21.2 % reduction in corrosion current density (from 11.3 to 8.89 μA/cm2) and 29 % increase in polarization resistance (from 1.45 to 1.87 kΩ cm2) in artificial sweat environment. Finally, surface wettability studies revealed that increased hydrophobicity (contact angle:49.13° to 57.99°) was correlated with enhanced corrosion barrier performance. These findings establish RF-sputtered HfO₂ as a viable, scalable solution for copper protection in next-generation microelectronic and wearable biosensor applications.
{"title":"HfO₂ barrier layers: Thickness-dependent corrosion protection of copper thin films for potential microelectronic applications with sweat contact","authors":"Osman KAHVECİ , Muh RUSDI , Abdullah AKKAYA , Enise AYYILDIZ","doi":"10.1016/j.microrel.2025.115985","DOIUrl":"10.1016/j.microrel.2025.115985","url":null,"abstract":"<div><div>Copper conductive thin films or components in microelectronic devices face significant corrosion challenges that compromise long-term reliability. This study presents a comprehensive investigation of hafnium dioxide (HfO₂) as a protective barrier layer deposited by RF magnetron sputtering at varying thicknesses (150 and 300 nm) on copper substrates for possible microelectronic applications. Multi-technique characterization methods, including SEM-EDX, AFM, XRD, FTIR, UV–Vis spectroscopy, contact angle measurements, potentiodynamic polarization, and electrochemical impedance spectroscopy (EIS), were employed to establish structure, property, and performance relationships. EDX results show that the addition of an HfO₂ layer significantly modified the surface morphology, especially on presence of 300 nm HfO₂ layer, so that the surface appears continuous and uniform. This is also supported by the FTIR analysis results, which indicate the presence of the strongest Hf<img>O and Hf-O-Hf vibrational bonds, thereby confirming the formation of an HfO₂ layer on the Cu surface. AFM results show an increase in surface topography roughness, caused by island-type growth (Volmer-Weber), as the thickness of the HfO₂ layer increases. The XRD results for un-coated sample shows sharp and clear diffraction peaks and indicates face-centered cubic (FCC) phase pattern of pure Cu nanoparticles. When the HfO<sub>2</sub> layer added Cu layer, XRD pattern shows the formation of a broad hump in the range of 2θ ≈ 28°–35° and HfO<sub>2</sub> layer formed is in the amorphous state. These results are correlated with the contact angle test results. UV–Vis results show that 300 nm HfO₂ coted films has the highest transmittance value across the entire wavelength range, as well as the lowest absorbance value. The 300 nm HfO₂ coating demonstrated optimal corrosion protection with 21.2 % reduction in corrosion current density (from 11.3 to 8.89 μA/cm<sup>2</sup>) and 29 % increase in polarization resistance (from 1.45 to 1.87 kΩ cm<sup>2</sup>) in artificial sweat environment. Finally, surface wettability studies revealed that increased hydrophobicity (contact angle:49.13° to 57.99°) was correlated with enhanced corrosion barrier performance. These findings establish RF-sputtered HfO₂ as a viable, scalable solution for copper protection in next-generation microelectronic and wearable biosensor applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115985"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, machine-learning-assisted co-design framework that links high-fidelity finite-element analysis (FEA) with surrogate modeling, multi-objective optimization, and decision analysis. A 3D FEA model generates 500 Latin Hypercube design points for type of analysis (thermal and reliability), spanning geometry, materials, and thermal-path variables. Four minimized objectives are considered: junction-to-ambient thermal resistance () and cycle-averaged plastic strain-energy density at the corner flip-chip cu-pillar bump (), C4 bump (), and BGA (). Tree-based regressors (Random Forest, XGBoost) achieve high test-set fidelity and drive NSGA-II to enumerate the Pareto domain. A Net Flow multi-criteria decision method (MCDM) ranks Pareto candidates to identify a champion design with balanced thermo-mechanical performance. Re-simulation of the champion in FEA confirms surrogate accuracy for dominant responses (≈4–5 % deviation for and ) and exact agreement for , while revealing weak coupling between thermal and mechanical objectives—enabling partial decoupling of heat-path optimization from interconnect reliability.
{"title":"Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning","authors":"Mohammad Rafiee , Farough Agin , Kuldeep Kumar , Ezhilan Murali","doi":"10.1016/j.microrel.2025.115983","DOIUrl":"10.1016/j.microrel.2025.115983","url":null,"abstract":"<div><div>Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, machine-learning-assisted co-design framework that links high-fidelity finite-element analysis (FEA) with surrogate modeling, multi-objective optimization, and decision analysis. A 3D FEA model generates 500 Latin Hypercube design points for type of analysis (thermal and reliability), spanning geometry, materials, and thermal-path variables. Four minimized objectives are considered: junction-to-ambient thermal resistance (<span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>) and cycle-averaged plastic strain-energy density at the corner flip-chip cu-pillar bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub></math></span>), C4 bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>), and BGA (<span><math><mi>Δ</mi><msub><mi>W</mi><mi>BGA</mi></msub></math></span>). Tree-based regressors (Random Forest, XGBoost) achieve high test-set fidelity and drive NSGA-II to enumerate the Pareto domain. A Net Flow multi-criteria decision method (MCDM) ranks Pareto candidates to identify a champion design with balanced thermo-mechanical performance. <em>Re</em>-simulation of the champion in FEA confirms surrogate accuracy for dominant responses (≈4–5 % deviation for <span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub><mspace></mspace></math></span>and <span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>) and exact agreement for <span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>, while revealing weak coupling between thermal and mechanical objectives—enabling partial decoupling of heat-path optimization from interconnect reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115983"},"PeriodicalIF":1.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-12DOI: 10.1016/j.microrel.2025.115976
Dorottya Varga , Zsombor Olajos , Gabor Belina
Estimating solder joint lifetime often involves extrapolating crack length measurements from cross-sectional images to a defined end-of-life (EoL) criterion. The original pearl string method fits a single regression line to all data points, which can result in unrealistic predictions, such as negative slopes or failure times. To address these issues, an alternative pearl string method was proposed, incorporating a fixed crack-free time (CFT) ratio to better reflect actual damage evolution. This study compares the two methods in terms of robustness, accuracy, and statistical consistency. The alternative method fits individual crack propagation curves for each specimen, enabling lifetime estimation in destructive testing with limited measurement points. Outlier sensitivity analysis showed that the original method is highly affected by anomalous data, while the alternative method exhibited minimal change. Goodness-of-fit evaluation using the Kolmogorov–Smirnov test confirmed that the alternative method aligns more closely with the validation data (p = 0.09 and 0.22), unlike the original method (p = 3.66 × 10−6 and 1.20 × 10−8). In conclusion, the alternative pearl string method offers a more robust and physically meaningful approach for lifetime extrapolation, especially in contexts with limited or noisy data.
{"title":"Comparative study of extrapolation methods for solder joint lifetime estimation using crack length data","authors":"Dorottya Varga , Zsombor Olajos , Gabor Belina","doi":"10.1016/j.microrel.2025.115976","DOIUrl":"10.1016/j.microrel.2025.115976","url":null,"abstract":"<div><div>Estimating solder joint lifetime often involves extrapolating crack length measurements from cross-sectional images to a defined end-of-life (EoL) criterion. The original pearl string method fits a single regression line to all data points, which can result in unrealistic predictions, such as negative slopes or failure times. To address these issues, an alternative pearl string method was proposed, incorporating a fixed crack-free time (CFT) ratio to better reflect actual damage evolution. This study compares the two methods in terms of robustness, accuracy, and statistical consistency. The alternative method fits individual crack propagation curves for each specimen, enabling lifetime estimation in destructive testing with limited measurement points. Outlier sensitivity analysis showed that the original method is highly affected by anomalous data, while the alternative method exhibited minimal change. Goodness-of-fit evaluation using the Kolmogorov–Smirnov test confirmed that the alternative method aligns more closely with the validation data (<em>p</em> = 0.09 and 0.22), unlike the original method (<em>p</em> = 3.66 × 10<sup>−6</sup> and 1.20 × 10<sup>−8</sup>). In conclusion, the alternative pearl string method offers a more robust and physically meaningful approach for lifetime extrapolation, especially in contexts with limited or noisy data.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115976"},"PeriodicalIF":1.9,"publicationDate":"2025-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115973
Guozhuang Fan , Jinzhu Zhou , Qiangqiang Lin , Jiancheng Shi
This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.
{"title":"Uncertainty quantification in microelectronic packaging using feedback-enhanced adaptive polynomial chaos expansion","authors":"Guozhuang Fan , Jinzhu Zhou , Qiangqiang Lin , Jiancheng Shi","doi":"10.1016/j.microrel.2025.115973","DOIUrl":"10.1016/j.microrel.2025.115973","url":null,"abstract":"<div><div>This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115973"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115977
Yanyong Wang , Liang He , Yanfang Li , Zhenni Wang , Zhongyang Li , Hao Zhou , Kaihe Liu , Maolin Zhang
This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (VTH) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.
{"title":"Investigation of interface traps properties induced by NBTI effects at different interfaces of VDMOS","authors":"Yanyong Wang , Liang He , Yanfang Li , Zhenni Wang , Zhongyang Li , Hao Zhou , Kaihe Liu , Maolin Zhang","doi":"10.1016/j.microrel.2025.115977","DOIUrl":"10.1016/j.microrel.2025.115977","url":null,"abstract":"<div><div>This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (<em>V</em><sub><em>TH</em></sub>) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115977"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115979
Yan Liu , Yanhua Ma , Chong Pan
In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.
{"title":"Investigation of thermal contact resistance, incident depth, incident angle, drain voltage and ambient temperature on single event transient during self-heating","authors":"Yan Liu , Yanhua Ma , Chong Pan","doi":"10.1016/j.microrel.2025.115979","DOIUrl":"10.1016/j.microrel.2025.115979","url":null,"abstract":"<div><div>In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115979"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wide application of portable electronic devices in high-vibration environments puts increasing demands on accurate and efficient modeling of the dynamic behavior of printed circuit boards (PCBs). To address this challenge, this study proposes a multiscale modeling approach based on a partitioned homogenization strategy. By integrating microscale material properties extraction with macroscale structural modal analysis, a modeling framework is established that significantly improves computational efficiency while preserving the material heterogeneity of wiring layers. The proposed method is comprehensively validated through hammer impact tests and comparison with a detailed wiring model. For a four-layer PCB, the proposed model predicts the first four natural frequencies with a maximum error of 11 %, while reducing the computational time by 69.5 % compared to the detailed model containing more than 10 million elements. Furthermore, a sensitivity analysis of the partition size reveals that model accuracy improves with smaller partitions, while computational efficiency exhibits a non-monotonic trend. An optimal balance between accuracy and efficiency is achieved when the partition size is approximately 6 to 10 times the minimum copper wire width (0.5 mm). The proposed method serves as a practical modeling solution for high-performance PCB vibration analysis, enabling rapid modal evaluation for complex electronic assemblies and providing a practical tool for PCB structural optimization in engineering applications.
{"title":"A novel partitioned homogenization approach for rapid and accurate vibration analysis of printed circuit boards","authors":"Mengxuan Cheng , Yong Zhou , Guoshun Wan , Xiaohui Zhao , Zhiyan Zhao , Hao Zheng , Yuxi Jia","doi":"10.1016/j.microrel.2025.115972","DOIUrl":"10.1016/j.microrel.2025.115972","url":null,"abstract":"<div><div>The wide application of portable electronic devices in high-vibration environments puts increasing demands on accurate and efficient modeling of the dynamic behavior of printed circuit boards (PCBs). To address this challenge, this study proposes a multiscale modeling approach based on a partitioned homogenization strategy. By integrating microscale material properties extraction with macroscale structural modal analysis, a modeling framework is established that significantly improves computational efficiency while preserving the material heterogeneity of wiring layers. The proposed method is comprehensively validated through hammer impact tests and comparison with a detailed wiring model. For a four-layer PCB, the proposed model predicts the first four natural frequencies with a maximum error of 11 %, while reducing the computational time by 69.5 % compared to the detailed model containing more than 10 million elements. Furthermore, a sensitivity analysis of the partition size reveals that model accuracy improves with smaller partitions, while computational efficiency exhibits a non-monotonic trend. An optimal balance between accuracy and efficiency is achieved when the partition size is approximately 6 to 10 times the minimum copper wire width (0.5 mm). The proposed method serves as a practical modeling solution for high-performance PCB vibration analysis, enabling rapid modal evaluation for complex electronic assemblies and providing a practical tool for PCB structural optimization in engineering applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115972"},"PeriodicalIF":1.9,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.microrel.2025.115974
Haiwei Xue , Fangfa Fu , Jinxiang Wang , Xudong Huang , Menghua Zhang , Lingxiang Qu
Digital signal processors (DSPs) are increasingly being utilized in nuclear plants and instruments, and the transient dose rate effects (TDREs) they encounter due to radiation have become a significant concern. In this paper, the TDREs of DSP were investigated through experiments conducted at the Northwest Institute of Nuclear Technology in China. The DSP, designed to be radiation-hardened (Rad-Hard) and manufactured using a 0.13 μm Silicon-On-Insulator(SOI) process, was tested under four dose-rates ranging from 1.5 × 1011 Rad(Si)/s to 2.0 × 1011 Rad(Si)/s. The experimental results indicate that the disturbances in voltage and current induced by transient dose rate radiation are small, owing to radiation-hardened-by-design and the SOI process. The recovery time of the voltage in Rad-Hard DSP is shorter than that of conventional bulk silicon devices. This is attributed to the SOI MOS device having only horizontal parasitic junctions, a result of the presence of the buried oxide layer. The experimental results also demonstrate that the transient dose rate (TDR) threshold of the Rad-Hard DSP circuit can reach up to 1.6 × 1011 Rad(Si)/s without functional failures and up to 2.0 × 1011 Rad(Si)/s without latchup. In this work, the Rad-Hard DSP circuit's ability to withstand transient dose rate irradiation is shown to be one order of magnitude greater than that of bulk silicon counterparts.
{"title":"Experimental study of transient dose rate effect on radiation-hardened digital signal processor","authors":"Haiwei Xue , Fangfa Fu , Jinxiang Wang , Xudong Huang , Menghua Zhang , Lingxiang Qu","doi":"10.1016/j.microrel.2025.115974","DOIUrl":"10.1016/j.microrel.2025.115974","url":null,"abstract":"<div><div>Digital signal processors (DSPs) are increasingly being utilized in nuclear plants and instruments, and the transient dose rate effects (TDREs) they encounter due to radiation have become a significant concern. In this paper, the TDREs of DSP were investigated through experiments conducted at the Northwest Institute of Nuclear Technology in China. The DSP, designed to be radiation-hardened (Rad-Hard) and manufactured using a 0.13 μm Silicon-On-Insulator(SOI) process, was tested under four dose-rates ranging from 1.5 × 10<sup>11</sup> Rad(Si)/s to 2.0 × 10<sup>11</sup> Rad(Si)/s. The experimental results indicate that the disturbances in voltage and current induced by transient dose rate radiation are small, owing to radiation-hardened-by-design and the SOI process. The recovery time of the voltage in Rad-Hard DSP is shorter than that of conventional bulk silicon devices. This is attributed to the SOI MOS device having only horizontal parasitic junctions, a result of the presence of the buried oxide layer. The experimental results also demonstrate that the transient dose rate (TDR) threshold of the Rad-Hard DSP circuit can reach up to 1.6 × 10<sup>11</sup> Rad(Si)/s without functional failures and up to 2.0 × 10<sup>11</sup> Rad(Si)/s without latchup. In this work, the Rad-Hard DSP circuit's ability to withstand transient dose rate irradiation is shown to be one order of magnitude greater than that of bulk silicon counterparts.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115974"},"PeriodicalIF":1.9,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号