Pub Date : 2025-11-12DOI: 10.1016/j.microrel.2025.115951
Weiwei Wei , Shilin Liu , Guoqing Xu , Hongtao Liu
Junction temperature (Tj) is a key parameter to judge the reliability of power MOSFET. However, extracting the junction temperature of a power MOSFET in real-time remains a challenge. To address this challenge, this manuscript proposes an online method to extract the junction temperature of a power MOSFET using calculated turn-off time (tcoff). This manuscript makes three main contributions: 1) The influence of junction temperature on the turn-off process of power MOSFET is analyzed. The calculated turn-off time is proposed as a temperature-sensitive electrical parameter (TSEP) to extract the junction temperature. 2) The high-frequency response of the circuit parasitic parameters caused by the switching process of the power MOSFET is analyzed. An online calculated turn-off time measurement method is proposed. 3) Experiments confirm that calculated turn-off time, as TSEP, offers advantages such as high sensitivity and good linearity. Additionally, the effectiveness of the online measurement method for calculated turn-off time was verified, and an experiment was conducted to extract the junction temperature online.
{"title":"Online extraction of power MOSFET junction temperature using calculated turn-off time","authors":"Weiwei Wei , Shilin Liu , Guoqing Xu , Hongtao Liu","doi":"10.1016/j.microrel.2025.115951","DOIUrl":"10.1016/j.microrel.2025.115951","url":null,"abstract":"<div><div>Junction temperature (<em>T</em><sub>j</sub>) is a key parameter to judge the reliability of power MOSFET. However, extracting the junction temperature of a power MOSFET in real-time remains a challenge. To address this challenge, this manuscript proposes an online method to extract the junction temperature of a power MOSFET using calculated turn-off time (<em>t</em><sub>coff</sub>). This manuscript makes three main contributions: 1) The influence of junction temperature on the turn-off process of power MOSFET is analyzed. The calculated turn-off time is proposed as a temperature-sensitive electrical parameter (TSEP) to extract the junction temperature. 2) The high-frequency response of the circuit parasitic parameters caused by the switching process of the power MOSFET is analyzed. An online calculated turn-off time measurement method is proposed. 3) Experiments confirm that calculated turn-off time, as TSEP, offers advantages such as high sensitivity and good linearity. Additionally, the effectiveness of the online measurement method for calculated turn-off time was verified, and an experiment was conducted to extract the junction temperature online.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115951"},"PeriodicalIF":1.9,"publicationDate":"2025-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-08DOI: 10.1016/j.microrel.2025.115946
Danni Cao , Ping Wu , Linjie Liao , Zhen Liu , Yiou Qiu , Linzheng Fu , Wenhui Zhu , Liancheng Wang
With the rapid development of artificial intelligence, cloud computing, 5G, and new energy industries, power modules face multiple technical challenges including increasing power density, higher integration levels, and long-term reliability. To meet miniaturization requirements, industry has developed technologies such as double-sided plastic encapsulation and component-on-package (CoP) to enhance integration. Although system-in-package (SiP) technology enables compact size and high performance for power modules, it introduces interfacial reliability degradation under harsh environmental conditions (e.g., humidity and thermal cycling). To address this issue, this study combined finite element analysis (FEA) with reliability testing conducted according to JEDEC standards to systematically evaluate failure mechanisms under complex operating conditions. Testing revealed that after MSL1 moisture absorption treatment, extensive delamination occurred during three reflow soldering processes. Through establishing three physical models—85 °C/85 % RH hygrothermal diffusion model, reflow desorption model, and peak-temperature vapor pressure model—the stress distribution and crack propagation under thermo-hygro-vapor pressure coupling were elucidated. Key findings include: Moisture diffusion exhibited low concentration gradients within 100 h due to inorganic material barrier effects; Moisture loss rate during reflow demonstrated nonlinear growth with temperature, reaching maximum at peak temperature; Equivalent coefficient of thermal expansion (CTE) analysis quantified stress ratios as 1:1.07:0.84 (thermal-hygro-vapor), revealing that crack propagation is primarily driven by shear stress-dominated GII mode. Notably, the strain energy release rate (SERR) under multi-field coupling exceeded the linear superposition values of individual fields by 304 %, demonstrating that synergistic effects significantly accelerate interfacial delamination failure risks.
{"title":"Research on hygrothermal reliability of double-sided molded power modules","authors":"Danni Cao , Ping Wu , Linjie Liao , Zhen Liu , Yiou Qiu , Linzheng Fu , Wenhui Zhu , Liancheng Wang","doi":"10.1016/j.microrel.2025.115946","DOIUrl":"10.1016/j.microrel.2025.115946","url":null,"abstract":"<div><div>With the rapid development of artificial intelligence, cloud computing, 5G, and new energy industries, power modules face multiple technical challenges including increasing power density, higher integration levels, and long-term reliability. To meet miniaturization requirements, industry has developed technologies such as double-sided plastic encapsulation and component-on-package (CoP) to enhance integration. Although system-in-package (SiP) technology enables compact size and high performance for power modules, it introduces interfacial reliability degradation under harsh environmental conditions (e.g., humidity and thermal cycling). To address this issue, this study combined finite element analysis (FEA) with reliability testing conducted according to JEDEC standards to systematically evaluate failure mechanisms under complex operating conditions. Testing revealed that after MSL1 moisture absorption treatment, extensive delamination occurred during three reflow soldering processes. Through establishing three physical models—85 °C/85 % RH hygrothermal diffusion model, reflow desorption model, and peak-temperature vapor pressure model—the stress distribution and crack propagation under thermo-hygro-vapor pressure coupling were elucidated. Key findings include: Moisture diffusion exhibited low concentration gradients within 100 h due to inorganic material barrier effects; Moisture loss rate during reflow demonstrated nonlinear growth with temperature, reaching maximum at peak temperature; Equivalent coefficient of thermal expansion (CTE) analysis quantified stress ratios as 1:1.07:0.84 (thermal-hygro-vapor), revealing that crack propagation is primarily driven by shear stress-dominated G<sub>II</sub> mode. Notably, the strain energy release rate (SERR) under multi-field coupling exceeded the linear superposition values of individual fields by 304 %, demonstrating that synergistic effects significantly accelerate interfacial delamination failure risks.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115946"},"PeriodicalIF":1.9,"publicationDate":"2025-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-08DOI: 10.1016/j.microrel.2025.115950
Shweta, Sunil Jadav
In response to the growing need for flexible and wearable electronics, multifunctional sensing films have been developed. For ensuring the reliability of the sensing films on flexible substrate, the bending analysis becomes highly significant. This research presents the bending analysis of SnO2 Quantum dots (QDs) to assess their suitability as gas and strain sensors. Determining the mechanical durability and failure lifespan of flexible devices thus requires a precise assessment of bending-induced strain and the associated resistance change. The impact of various bending factors such as bending radius, substrate thickness, and film thickness on strain is examined. The findings demonstrate that thinner substrates and films may withstand greater strain without experiencing structural failure, which qualifies them for flexible gas sensing applications. The reverse design approach is also specified that will help the researchers to optimize the design structure as per performance requirement. Furthermore, the resistance changes of SnO2 QDs with strain is modeled using a calibration-based technique, utilizing reference data from carbon nanocoil (CNC) and single-walled carbon nanotube (SWCNT) film and the observed results are validated with experimental data of SnO2 QDs. With a consistent response value of 0.96 for SnO2 QDs throughout bending radii between 2 mm and 40 mm, the modeled sensor validates the feasibility of SnO2 QDs for flexible and wearable gas sensor applications and demonstrates that gas sensing performance is strain-insensitive.
{"title":"SnO2 quantum dots under mechanical bending: Modeling and application in flexible sensors","authors":"Shweta, Sunil Jadav","doi":"10.1016/j.microrel.2025.115950","DOIUrl":"10.1016/j.microrel.2025.115950","url":null,"abstract":"<div><div>In response to the growing need for flexible and wearable electronics, multifunctional sensing films have been developed. For ensuring the reliability of the sensing films on flexible substrate, the bending analysis becomes highly significant. This research presents the bending analysis of SnO<sub>2</sub> Quantum dots (QDs) to assess their suitability as gas and strain sensors. Determining the mechanical durability and failure lifespan of flexible devices thus requires a precise assessment of bending-induced strain and the associated resistance change. The impact of various bending factors such as bending radius, substrate thickness, and film thickness on strain is examined. The findings demonstrate that thinner substrates and films may withstand greater strain without experiencing structural failure, which qualifies them for flexible gas sensing applications. The reverse design approach is also specified that will help the researchers to optimize the design structure as per performance requirement. Furthermore, the resistance changes of SnO<sub>2</sub> QDs with strain is modeled using a calibration-based technique, utilizing reference data from carbon nanocoil (CNC) and single-walled carbon nanotube (SWCNT) film and the observed results are validated with experimental data of SnO<sub>2</sub> QDs. With a consistent response value of 0.96 for SnO<sub>2</sub> QDs throughout bending radii between 2 mm and 40 mm, the modeled sensor validates the feasibility of SnO<sub>2</sub> QDs for flexible and wearable gas sensor applications and demonstrates that gas sensing performance is strain-insensitive.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115950"},"PeriodicalIF":1.9,"publicationDate":"2025-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.microrel.2025.115945
Zhen Xu , Man Luo , Jining Li , Kai Chen , Longhai Liu , Chao Yan , Degang Xu , Jianquan Yao
With the advancement of technology, integrated circuit technology is developing towards smaller feature sizes, higher integration levels, and lower power consumption. The issue of wire voids has become increasingly prominent, and traditional detection methods can no longer meet the growing demand for accurate detection. This study utilizes the time-domain pulse reflection technology combined with experimental testing, theoretical calculations, and simulations to locate and detect wire voids of different sizes and positions in integrated circuit wires with different parameters. The research results show that with the size of the void increasing, the reflected signal lags slightly behind compared to that of a smaller void. When the size of the wire void is 100 μm, the test error for a substrate dielectric constant of 2.2 is greater than that for a dielectric constant of 3. When the void size is 150 μm, the test error for a substrate dielectric constant of 2.2 is smaller than that for a dielectric constant of 3. When the dielectric constant of the substrate is 2.2 and the void size is 150 μm, the minimum distance test deviation is only 34.819 μm, and the position error is only 0.35 %. The farther the void position is from the test point, the greater the error. This study utilizes terahertz pulse time - domain reflection technology to detect tiny voids and fault locations in integrated circuits, which is of great significance for ensuring the quality of integrated circuits and promoting the sustainable development of electronic technology.
{"title":"Terahertz pulse time-domain reflection for accurate detection of wire voids in integrated circuits: A simulation and experimental validation","authors":"Zhen Xu , Man Luo , Jining Li , Kai Chen , Longhai Liu , Chao Yan , Degang Xu , Jianquan Yao","doi":"10.1016/j.microrel.2025.115945","DOIUrl":"10.1016/j.microrel.2025.115945","url":null,"abstract":"<div><div>With the advancement of technology, integrated circuit technology is developing towards smaller feature sizes, higher integration levels, and lower power consumption. The issue of wire voids has become increasingly prominent, and traditional detection methods can no longer meet the growing demand for accurate detection. This study utilizes the time-domain pulse reflection technology combined with experimental testing, theoretical calculations, and simulations to locate and detect wire voids of different sizes and positions in integrated circuit wires with different parameters. The research results show that with the size of the void increasing, the reflected signal lags slightly behind compared to that of a smaller void. When the size of the wire void is 100 μm, the test error for a substrate dielectric constant of 2.2 is greater than that for a dielectric constant of 3. When the void size is 150 μm, the test error for a substrate dielectric constant of 2.2 is smaller than that for a dielectric constant of 3. When the dielectric constant of the substrate is 2.2 and the void size is 150 μm, the minimum distance test deviation is only 34.819 μm, and the position error is only 0.35 %. The farther the void position is from the test point, the greater the error. This study utilizes terahertz pulse time - domain reflection technology to detect tiny voids and fault locations in integrated circuits, which is of great significance for ensuring the quality of integrated circuits and promoting the sustainable development of electronic technology.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115945"},"PeriodicalIF":1.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1016/j.microrel.2025.115942
Shi-Jin Liu , Ying Wang , Cheng-Hao Yu , Hao-Min Guo
This article investigates the influence mechanism of substrate bias on the electrical characteristics of p-GaN HEMT devices, and uses the Sentaurus Technology Computer Aided Design (Sentaurus TCAD) and Stopping and Range of Ions in Matter (SRIM) joint simulation method to simulate the single-event effects (SEE) of devices under different substrate biases. Research has found that the device's threshold voltage is more stable under a positive substrate bias, and the vertical leakage current is lower. Furthermore, based on experimental testing, a Sentaurus TCAD and SRIM joint simulation was conducted to analyze the impact mechanism of different substrate biases on the device's SEE. Compared with the substrate-free electrode structure, the gate and drain currents are significantly reduced, reducing the possibility of device burnout at the drain and gate. In addition, the increase in source current and substrate current accelerates charge collection. Therefore, by designing and applying substrate bias reasonably, the stability and reliability of the device in both radiation and non-radiation environments can be effectively improved.
{"title":"Mechanism analysis and single event effect simulation of p-GaN HEMT devices under substrate bias conditions","authors":"Shi-Jin Liu , Ying Wang , Cheng-Hao Yu , Hao-Min Guo","doi":"10.1016/j.microrel.2025.115942","DOIUrl":"10.1016/j.microrel.2025.115942","url":null,"abstract":"<div><div>This article investigates the influence mechanism of substrate bias on the electrical characteristics of p-GaN HEMT devices, and uses the Sentaurus Technology Computer Aided Design (Sentaurus TCAD) and Stopping and Range of Ions in Matter (SRIM) joint simulation method to simulate the single-event effects (SEE) of devices under different substrate biases. Research has found that the device's threshold voltage is more stable under a positive substrate bias, and the vertical leakage current is lower. Furthermore, based on experimental testing, a Sentaurus TCAD and SRIM joint simulation was conducted to analyze the impact mechanism of different substrate biases on the device's SEE. Compared with the substrate-free electrode structure, the gate and drain currents are significantly reduced, reducing the possibility of device burnout at the drain and gate. In addition, the increase in source current and substrate current accelerates charge collection. Therefore, by designing and applying substrate bias reasonably, the stability and reliability of the device in both radiation and non-radiation environments can be effectively improved.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115942"},"PeriodicalIF":1.9,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1016/j.microrel.2025.115947
Vaidehi Vijay Painter , Raphael Sommet , Jean-Christophe Nallatamby , P. Vigneshwara Raja
A comprehensive investigation into the electrothermal behaviour of AlGaN/GaN high-electron mobility transistor (HEMT) is presented in this work, by means of validated physics-based TCAD simulations. The focus is on the impact of different field-plate (FP) architectures, including source-connected field-plate (SC-FP), gate-connected field-plate (GC-FP), and without FP structures, on the thermal resistance (RTH) of the HEMT. A key finding is the identification of multiple RTH regions in the field-plated HEMT, a direct consequence of the primary hotspot dynamically evolving from the gate-edge, to a dual-hotspot configuration, and finally migrating to the FP edge with increasing power levels; in contrast to the single RTH of the HEMT without FP. This multi-RTH characteristic is consistent in both SC-FP and GC-FP structures. Moreover, the channel temperature profile is nearly identical in both FPs. The influence of passivation thickness (tSiN) and field-plate length (LFP), on RTH is systematically investigated. The results reveal a critical design trade-off; thicker passivation improves electrical insulation but thermally decouples the FP effect, while thinner tSiN increases the electric field at the FP edge. The increased LFP leads to a corresponding reduction in the RTH. Hence, integrated electrothermal co-design is a fundamental prerequisite for optimizing the performance and reliability of the HEMTs.
{"title":"Source-connected and gate-connected field-plate influence on thermal resistance of AlGaN/GaN HEMT with varying passivation thickness and field-plate length","authors":"Vaidehi Vijay Painter , Raphael Sommet , Jean-Christophe Nallatamby , P. Vigneshwara Raja","doi":"10.1016/j.microrel.2025.115947","DOIUrl":"10.1016/j.microrel.2025.115947","url":null,"abstract":"<div><div>A comprehensive investigation into the electrothermal behaviour of AlGaN/GaN high-electron mobility transistor (HEMT) is presented in this work, by means of validated physics-based TCAD simulations. The focus is on the impact of different field-plate (FP) architectures, including source-connected field-plate (SC-FP), gate-connected field-plate (GC-FP), and without FP structures, on the thermal resistance (<em>R</em><sub><em>TH</em></sub>) of the HEMT. A key finding is the identification of multiple <em>R</em><sub><em>TH</em></sub> regions in the field-plated HEMT, a direct consequence of the primary hotspot dynamically evolving from the gate-edge, to a dual-hotspot configuration, and finally migrating to the FP edge with increasing power levels; in contrast to the single <em>R</em><sub><em>TH</em></sub> of the HEMT without FP. This multi-<em>R</em><sub><em>TH</em></sub> characteristic is consistent in both SC-FP and GC-FP structures. Moreover, the channel temperature profile is nearly identical in both FPs. The influence of passivation thickness (<em>t</em><sub><em>SiN</em></sub>) and field-plate length (<em>L</em><sub><em>FP</em></sub>), on <em>R</em><sub><em>TH</em></sub> is systematically investigated. The results reveal a critical design trade-off; thicker passivation improves electrical insulation but thermally decouples the FP effect, while thinner <em>t</em><sub><em>SiN</em></sub> increases the electric field at the FP edge. The increased <em>L</em><sub><em>FP</em></sub> leads to a corresponding reduction in the <em>R</em><sub><em>TH</em></sub>. Hence, integrated electrothermal co-design is a fundamental prerequisite for optimizing the performance and reliability of the HEMTs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115947"},"PeriodicalIF":1.9,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-04DOI: 10.1016/j.microrel.2025.115944
Shweta , Sunil Jadav
Microheaters are necessary for a variety of applications, including biomedical implants, wearable sensor systems, and portable electronics that require low-power, quick thermal actuation. This research compares three widely used microheater materials namely silver, copper, and platinum placed on a polyimide (PI) substrate using a thorough electro-thermo-mechanical simulation performed using COMSOL Multiphysics. Thermo-mechanical analysis confirmed that the microheater's structural integrity is maintained since the generated stresses are less than the yield strength of the component materials. The paper also examines the effect of various parameters such as heater width, thickness, voltage, and number of turns on temperature distribution, power dissipation, and resistance. The results of various statistical indicators such as normalized uniformity index and coefficient of variation as well as graph of voltage vs ΔT revealed that platinum provides excellent thermal uniformity as compared to other two materials. The simulation results are validated against analytical calculations, showing good agreement with an average deviation of approximately 7 % across all materials, thereby confirming the accuracy of the modelling approach. With its useful design insights and material-specific trade-offs, this research offers designers creating next-generation flexible heating elements for gas sensors, wearable sensors, and biomedical systems.
{"title":"Thermal and electrical characterization of flexible microheaters: Influence of material choice and geometry","authors":"Shweta , Sunil Jadav","doi":"10.1016/j.microrel.2025.115944","DOIUrl":"10.1016/j.microrel.2025.115944","url":null,"abstract":"<div><div>Microheaters are necessary for a variety of applications, including biomedical implants, wearable sensor systems, and portable electronics that require low-power, quick thermal actuation. This research compares three widely used microheater materials namely silver, copper, and platinum placed on a polyimide (PI) substrate using a thorough electro-thermo-mechanical simulation performed using COMSOL Multiphysics. Thermo-mechanical analysis confirmed that the microheater's structural integrity is maintained since the generated stresses are less than the yield strength of the component materials. The paper also examines the effect of various parameters such as heater width, thickness, voltage, and number of turns on temperature distribution, power dissipation, and resistance. The results of various statistical indicators such as normalized uniformity index and coefficient of variation as well as graph of voltage vs ΔT revealed that platinum provides excellent thermal uniformity as compared to other two materials. The simulation results are validated against analytical calculations, showing good agreement with an average deviation of approximately 7 % across all materials, thereby confirming the accuracy of the modelling approach. With its useful design insights and material-specific trade-offs, this research offers designers creating next-generation flexible heating elements for gas sensors, wearable sensors, and biomedical systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115944"},"PeriodicalIF":1.9,"publicationDate":"2025-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145473544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-31DOI: 10.1016/j.microrel.2025.115943
Vanshika Ghai , Sidhartha Dash , Guru Prasad Mishra
This paper proposes a graphene channel-based Vertical Tunnel Field Effect Transistor (V-TFET) and analyzes its reliability using Trap-Assisted Tunneling (TAT). The Graphene Channel V-TFET (GC V-TFET) improves device performance because of graphene's two-dimensional honeycomb structure enhancing electron tunneling. Compared to ordinary V-TFETs, this GC V-TFET offers over one decade of improvement in drain current, a two-decade increase in the ION/IOFF ratio, a higher electric field, a lower energy bandgap width, and a one-fold improvement in transconductance. The Silvaco ATLAS TCAD tool compares the simulations of V-TFET and GC V-TFET. To assess reliability, the impact of TAT on the GC V-TFET has been investigated. The results showed an increase of about one decade in the IOFF value, increase in electric field of approximately 3.0 × 104 V/cm, decrease in potential of about 0.04 V, an upward shift in energy bands of about 0.02 eV, increased transconductance of 1.5 × 10−6 S, electron concentration at source side is reduced by 4 × 1016 cm−3, hole concentration at channel region decreases by approximately 20 %, electron current density is increased by three and two orders at channel and drain region respectively, hole current density is increased by approximately four orders at source region and decrease in the recombination rate of 4.2 × 104 cm−1 s−1.
{"title":"Reliability assessment of graphene channel vertical TFET: Role of trap-assisted tunneling","authors":"Vanshika Ghai , Sidhartha Dash , Guru Prasad Mishra","doi":"10.1016/j.microrel.2025.115943","DOIUrl":"10.1016/j.microrel.2025.115943","url":null,"abstract":"<div><div>This paper proposes a graphene channel-based Vertical Tunnel Field Effect Transistor (V-TFET) and analyzes its reliability using Trap-Assisted Tunneling (TAT). The Graphene Channel V-TFET (GC V-TFET) improves device performance because of graphene's two-dimensional honeycomb structure enhancing electron tunneling. Compared to ordinary V-TFETs, this GC V-TFET offers over one decade of improvement in drain current, a two-decade increase in the I<sub>ON</sub>/I<sub>OFF</sub> ratio, a higher electric field, a lower energy bandgap width, and a one-fold improvement in transconductance. The Silvaco ATLAS TCAD tool compares the simulations of V-TFET and GC V-TFET. To assess reliability, the impact of TAT on the GC V-TFET has been investigated. The results showed an increase of about one decade in the I<sub>OFF</sub> value, increase in electric field of approximately 3.0 × 10<sup>4</sup> V/cm, decrease in potential of about 0.04 V, an upward shift in energy bands of about 0.02 eV, increased transconductance of 1.5 × 10<sup>−6</sup> S, electron concentration at source side is reduced by 4 × 10<sup>16</sup> cm<sup>−3</sup>, hole concentration at channel region decreases by approximately 20 %, electron current density is increased by three and two orders at channel and drain region respectively, hole current density is increased by approximately four orders at source region and decrease in the recombination rate of 4.2 × 10<sup>4</sup> cm<sup>−1</sup> s<sup>−1</sup>.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115943"},"PeriodicalIF":1.9,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145424713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Physically Unclonable Functions (PUFs) represent a modern hardware approach for achieving authentication and secure key generation. The PUF uses the intrinsic, numerous, unpredictable, and unavoidable variances in the semiconductor manufacturing process to enhance hardware and software security. The inherent process variations in semiconductor technology are exploited in PUF circuits to generate unique and unclonable device identifiers. In the proposed design, integrating a Current-Starved (CS) inverter, metastable circuit, and LFSR enhances reliability from 91.06% to 98.96%. The design achieves 49.24% uniqueness, 50.27% uniformity, and 49.87% bit aliasing across a wide temperature range (−40 °C to 120 °C). Power consumption is reduced by about 2.14 compared to a conventional RO PUF. Prelayout and postlayout simulations report delays of 1.11 ns and 2.3 ns, respectively, while NIST tests confirm randomness. FPGA implementation on a Basys-3 Artix-7 using Vivado requires minimal hardware and achieves an 80 Mb/s bit generation rate. Furthermore, the design resists ML-based modeling attacks, limiting prediction accuracy to 45%–65%.
{"title":"A temperature-invariant and ML-resilient, RO PUF design with improved security and performance metrics","authors":"Nitish Kumar , Aditya Antil , Himanshu Kesarwani , Dhirendra Kumar , Kavindra Kandpal , Manish Goswami","doi":"10.1016/j.microrel.2025.115941","DOIUrl":"10.1016/j.microrel.2025.115941","url":null,"abstract":"<div><div>Physically Unclonable Functions (PUFs) represent a modern hardware approach for achieving authentication and secure key generation. The PUF uses the intrinsic, numerous, unpredictable, and unavoidable variances in the semiconductor manufacturing process to enhance hardware and software security. The inherent process variations in semiconductor technology are exploited in PUF circuits to generate unique and unclonable device identifiers. In the proposed design, integrating a Current-Starved (CS) inverter, metastable circuit, and LFSR enhances reliability from 91.06% to 98.96%. The design achieves 49.24% uniqueness, 50.27% uniformity, and 49.87% bit aliasing across a wide temperature range (−40 °C to 120 °C). Power consumption is reduced by about 2.14<span><math><mo>×</mo></math></span> compared to a conventional RO PUF. Prelayout and postlayout simulations report delays of 1.11 ns and 2.3 ns, respectively, while NIST tests confirm randomness. FPGA implementation on a Basys-3 Artix-7 using Vivado requires minimal hardware and achieves an 80 Mb/s bit generation rate. Furthermore, the design resists ML-based modeling attacks, limiting prediction accuracy to 45%–65%.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115941"},"PeriodicalIF":1.9,"publicationDate":"2025-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145424714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1016/j.microrel.2025.115940
Danting Li , Kai Zhao , Ruiwang Yu , Hao Wei , Yudi Zhao , Shuying Ma
Thermo-mechanical stress at ultra-low-k (ULK) dielectric interfaces has emerged as a critical challenge for flip-chip package reliability, stemming from the inherent brittleness of ULK materials, significant coefficient of thermal expansion (CTE) mismatch in chip-package systems, and the high modulus of copper interconnects. This study develops a multiscale finite element analysis framework that integrates global-submodel coupling methodology with temperature-dependent material properties to systematically investigate stress evolution during 25-260-25 °C reflow processes. Simulation results demonstrate that geometric optimization of copper pillar bumps can effectively reduce interfacial stresses across the solder/Ni/ULK multilayer interfaces while establishing design guidelines, including adopting passivation-covered PI openings, decreasing the PI opening-to-pillar diameter ratio for ULK interfacial stress redistribution, and reducing bump height while increasing PI thickness to ensure effective stress buffering. This research breaks through the limitations of traditional single-parameter optimization approaches, providing critical design insights for minimizing chip-package interfacial fracture failures.
{"title":"Thermomechanical stress optimization in flip-chip packages: Impacts of copper pillar geometry on ultra-low-k layer reliability","authors":"Danting Li , Kai Zhao , Ruiwang Yu , Hao Wei , Yudi Zhao , Shuying Ma","doi":"10.1016/j.microrel.2025.115940","DOIUrl":"10.1016/j.microrel.2025.115940","url":null,"abstract":"<div><div>Thermo-mechanical stress at ultra-low-k (ULK) dielectric interfaces has emerged as a critical challenge for flip-chip package reliability, stemming from the inherent brittleness of ULK materials, significant coefficient of thermal expansion (CTE) mismatch in chip-package systems, and the high modulus of copper interconnects. This study develops a multiscale finite element analysis framework that integrates global-submodel coupling methodology with temperature-dependent material properties to systematically investigate stress evolution during 25-260-25 °C reflow processes. Simulation results demonstrate that geometric optimization of copper pillar bumps can effectively reduce interfacial stresses across the solder/Ni/ULK multilayer interfaces while establishing design guidelines, including adopting passivation-covered PI openings, decreasing the PI opening-to-pillar diameter ratio for ULK interfacial stress redistribution, and reducing bump height while increasing PI thickness to ensure effective stress buffering. This research breaks through the limitations of traditional single-parameter optimization approaches, providing critical design insights for minimizing chip-package interfacial fracture failures.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115940"},"PeriodicalIF":1.9,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145424789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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