Microelectronics Reliability最新文献_第3页

Correlation of trap generation in SiC MOSFETs under γ-ray irradiation and bias temperature stress γ射线辐照下SiC mosfet中陷阱生成与偏置温度应力的关系

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-15 DOI: 10.1016/j.microrel.2026.116007

Xiaowen Liang , Dan Zhang , Ying Wei , Jie Feng , Qiwen Zheng , Lin Wen , Xuefeng Yu , Qi Guo , Teng Zhang , Yudong Li

Both Bias Temperature stress (BTS) and γ-ray irradiation can break SiSi bonds in the oxide of SiC MOSFETs, generating traps and consequently causing a variation of threshold voltage (V_TH). This study investigates the correlation between the defects induced by γ-ray irradiation and BTS. Commercial SiC MOSFETs rated at 1200 V / 80 mΩ from three manufacturers were subjected to 1 Mrad(Si) ⁶⁰Co-γ irradiation, followed by 168 h of annealing. Devices from the same batch were also tested under negative bias temperature stress (NBTS), positive bias temperature stress (PBTS), and long-term HTGB stress (V_GS = 20 V, T = 150 °C for 3200 h) experiment. Results show that the trends of threshold voltage shift (ΔV_TH) caused by γ-ray irradiation and BTS stress are consistent across all three devices. The changes follow the order of C > > A > B by extracting the ΔV_TH and the density of oxide trapped charges.

γ-ray irradiation and NBTS stress induced a negative shift of the V_TH. By separating the changes in oxide trapped charges during the two processes, it was found that the ratio of parameters related to the oxide trapped charge generation rate is around 50, demonstrating a correlation between γ-ray irradiation and NBTS. Furthermore, it was found that the ratio of ΔV_TH after 1 Mrad(Si) irradiation and 120 h annealing(ΔV_TH-An120h) to that after 2000 h of HTGB stress(ΔV_TH-2000h) is around 0.5 for all three devices. This indicates that the TID and PBTS may share a similar correlation. Analysis indicates that ΔV_TH induced by γ-ray irradiation and BTS is correlated with oxygen vacancy defects in the gate oxide. Specifically, radiation and NBTS are associated with puckered structures, while PBTS relates to Si⁵–Si⁴ structures. Among the three devices, the correlation between the generation rate of trapped charges under radiation and BTS in the three devices can establish the basis for the equivalence between the two methods.

偏置温度应力（BTS）和γ射线辐照都可以破坏SiC mosfet氧化物中的SiSi键，产生陷阱，从而引起阈值电压（VTH）的变化。本文研究了γ射线辐照引起的缺陷与BTS之间的关系。来自三个制造商的额定电压为1200 V / 80 mΩ的商用SiC mosfet进行了1 Mrad(Si) 60Co-γ辐照，然后进行了168 h的退火。同一批次的器件还分别在负偏置温度应力（NBTS）、正偏置温度应力（PBTS）和长期HTGB应力（VGS = 20 V, T = 150°C, 3200 h）下进行了测试。结果表明，γ射线辐照和BTS应力引起的阈值电压位移（ΔVTH）趋势在三种器件上是一致的。通过提取ΔVTH和氧化物捕获电荷的密度，其变化顺序为C >； > A >； B。γ射线辐照和NBTS应力引起了VTH的负移。通过分离两个过程中氧化物捕获电荷的变化，发现与氧化物捕获电荷产生率相关的参数之比约为50，表明γ射线辐照与NBTS之间存在相关性。此外，我们发现，对于这三种器件，1 Mrad（Si）辐照和120h退火后的ΔVTH （ΔVTH-An120h）与2000h HTGB应力后的ΔVTH （ΔVTH-2000h）之比约为0.5。这表明TID和PBTS可能具有相似的相关性。分析表明，γ射线辐照和BTS诱导的ΔVTH与栅极氧化物中的氧空位缺陷有关。具体来说，辐射和NBTS与皱化结构有关，而PBTS与Si5-Si4结构有关。在三种器件中，辐射下捕获电荷的产生速率与三种器件中BTS的相关性可以为两种方法之间的等效性奠定基础。

{"title":"Correlation of trap generation in SiC MOSFETs under γ-ray irradiation and bias temperature stress","authors":"Xiaowen Liang , Dan Zhang , Ying Wei , Jie Feng , Qiwen Zheng , Lin Wen , Xuefeng Yu , Qi Guo , Teng Zhang , Yudong Li","doi":"10.1016/j.microrel.2026.116007","DOIUrl":"10.1016/j.microrel.2026.116007","url":null,"abstract":"<div><div>Both Bias Temperature stress (BTS) and γ-ray irradiation can break Si<img>Si bonds in the oxide of SiC MOSFETs, generating traps and consequently causing a variation of threshold voltage (<em>V</em><sub>TH</sub>). This study investigates the correlation between the defects induced by γ-ray irradiation and BTS. Commercial SiC MOSFETs rated at 1200 V / 80 mΩ from three manufacturers were subjected to 1 Mrad(Si) <sup>60</sup>Co-γ irradiation, followed by 168 h of annealing. Devices from the same batch were also tested under negative bias temperature stress (NBTS), positive bias temperature stress (PBTS), and long-term HTGB stress (<em>V</em><sub>GS</sub> = 20 V, <em>T</em> = 150 °C for 3200 h) experiment. Results show that the trends of threshold voltage shift (Δ<em>V</em><sub>TH</sub>) caused by γ-ray irradiation and BTS stress are consistent across all three devices. The changes follow the order of C > > A > B by extracting the Δ<em>V</em><sub>TH</sub> and the density of oxide trapped charges.</div><div>γ-ray irradiation and NBTS stress induced a negative shift of the <em>V</em><sub>TH</sub>. By separating the changes in oxide trapped charges during the two processes, it was found that the ratio of parameters related to the oxide trapped charge generation rate is around 50, demonstrating a correlation between γ-ray irradiation and NBTS. Furthermore, it was found that the ratio of Δ<em>V</em><sub>TH</sub> after 1 Mrad(Si) irradiation and 120 h annealing(Δ<em>V</em><sub>TH-An120h</sub>) to that after 2000 h of HTGB stress(Δ<em>V</em><sub>TH-2000h</sub>) is around 0.5 for all three devices. This indicates that the TID and PBTS may share a similar correlation. Analysis indicates that Δ<em>V</em><sub>TH</sub> induced by γ-ray irradiation and BTS is correlated with oxygen vacancy defects in the gate oxide. Specifically, radiation and NBTS are associated with puckered structures, while PBTS relates to Si<sup>5</sup>–Si<sup>4</sup> structures. Among the three devices, the correlation between the generation rate of trapped charges under radiation and BTS in the three devices can establish the basis for the equivalence between the two methods.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116007"},"PeriodicalIF":1.9,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Online measurement of differential drain to source voltage for SiC MOSFETS power module SiC mosfet功率模块漏源差电压的在线测量

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-15 DOI: 10.1016/j.microrel.2026.116008

Antoine Laspeyres , Anne-Sophie Bacquet Descamps , Louison Gouy , Nicolas Ginot , Christophe Batard , Thanh-Long Le

The on-state resistance R_{DS_ON} is a key aging indicator of silicon carbide MOSFETs power module. It can provide information on both chip and packaging degradation allowing more reliable power electronic converter. This on-state resistance can be determined using both the on-state current and voltage of the power semiconductor. This paper focuses on an on-state voltage measurement circuit for SiC MOSFET power module. In the literature, power module bondwires resistance cannot be measured due to high switching voltage oscillations. An on-state voltage measurement circuit that can withstand such oscillations is proposed. The proposed circuit is characterized using the ISO 5725 standard over a wide temperature range. Finally, the circuit is successfully tested on a double pulse bench for various module base plate temperatures and compared to data obtained with a static curve tracer Keysight B1505.

导通电阻RDSON是碳化硅mosfet功率模块老化的关键指标。它可以提供有关芯片和封装退化的信息，从而实现更可靠的电力电子转换器。这个导通电阻可以用功率半导体的导通电流和电压来确定。本文研究了一种用于SiC MOSFET功率模块的导通电压测量电路。在文献中，由于高开关电压振荡，功率模块键合线电阻无法测量。提出了一种能承受这种振荡的导通电压测量电路。所提出的电路在宽温度范围内使用ISO 5725标准进行表征。最后，该电路在双脉冲台上成功测试了各种模块底板温度，并与Keysight B1505静态曲线示踪器获得的数据进行了比较。

引用次数: 0

Neutron irradiation assessment of an Inertial Measurement Unit 惯性测量装置的中子辐照评估

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-15 DOI: 10.1016/j.microrel.2026.116010

V. Pietrosanti , T. Minniti , M. Buffardo , S. Francola , C. Cazzaniga , C.D. Frost , M. Kastriotou , P. Peliti , F. Berton , U. Zuccari , G. Romanelli , R. Senesi , T.F. Catalano , C. Andreani , G. Campolo

The experiment presented in this paper involves the irradiation of an enhanced Inertial Measurement Unit developed by Northrop Grumman Italia and designed for avionics and space applications. The employment of this device at avionic altitudes prompted a necessary evaluation of its suitability and operation in a radiation environment characterized by atmospheric neutrons, particles that can lead to malfunctioning in microelectronics operation through single event effects. The results indicate that atmospheric neutron exposure does not significantly impact the long-term performance of the device, whose functionality remains recoverable. Reliability metrics such as cross-sections and failure in time are derived to assess error frequency and support mitigation strategies for avionics and space applications. The results indicate that velocity measurements are the most susceptible parameter, with a FIT of 209, whereas rotation angles and accelerations are more resilient, exhibiting FIT values of 182 and 173, respectively.

本文介绍的实验涉及诺斯罗普·格鲁曼意大利公司开发的用于航空电子和空间应用的增强型惯性测量单元的辐照。该装置在航空电子高度的使用促使对其适用性和在以大气中子为特征的辐射环境中的操作进行必要的评估，大气中子是通过单事件效应导致微电子操作故障的粒子。结果表明，大气中子暴露对装置的长期性能没有显著影响，其功能仍然可以恢复。导出了诸如横截面和及时失效等可靠性指标，以评估航空电子设备和空间应用的错误频率并支持缓解策略。结果表明，速度测量是最易受影响的参数，FIT值为209，而旋转角度和加速度更具弹性，分别为182和173。

{"title":"Neutron irradiation assessment of an Inertial Measurement Unit","authors":"V. Pietrosanti , T. Minniti , M. Buffardo , S. Francola , C. Cazzaniga , C.D. Frost , M. Kastriotou , P. Peliti , F. Berton , U. Zuccari , G. Romanelli , R. Senesi , T.F. Catalano , C. Andreani , G. Campolo","doi":"10.1016/j.microrel.2026.116010","DOIUrl":"10.1016/j.microrel.2026.116010","url":null,"abstract":"<div><div>The experiment presented in this paper involves the irradiation of an enhanced Inertial Measurement Unit developed by Northrop Grumman Italia and designed for avionics and space applications. The employment of this device at avionic altitudes prompted a necessary evaluation of its suitability and operation in a radiation environment characterized by atmospheric neutrons, particles that can lead to malfunctioning in microelectronics operation through single event effects. The results indicate that atmospheric neutron exposure does not significantly impact the long-term performance of the device, whose functionality remains recoverable. Reliability metrics such as cross-sections and failure in time are derived to assess error frequency and support mitigation strategies for avionics and space applications. The results indicate that velocity measurements are the most susceptible parameter, with a FIT of 209, whereas rotation angles and accelerations are more resilient, exhibiting FIT values of 182 and 173, respectively.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116010"},"PeriodicalIF":1.9,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A data-driven self-terminating write circuit with enhanced reliability for STT-MRAM using MUX logic 采用MUX逻辑的STT-MRAM数据驱动自终止写入电路，具有增强的可靠性

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-14 DOI: 10.1016/j.microrel.2026.116006

Ravi S. Siddanath, Mohit Gupta, Souvik Kumar Das, G.K. Prasad, Manish Goswami, Kavindra Kandpal

The rise of artificial intelligence (AI) and edge computing demands memory solutions that are high-speed, low-latency, nonvolatile, and low-power. Conventional options such as SRAM, DRAM, flash, and EEPROM often face limitations in scalability and efficiency. Magnetic tunnel junction (MTJ) based spin-transfer torque magnetoresistive RAM (STT-MRAM) emerges as a strong candidate due to zero standby power and CMOS compatibility. STT-MRAM combines SRAM-like speed, DRAM-like density, and flash-like non-volatility. Still, its one-transistor one-MTJ (1 T-1MTJ) cell suffers from asymmetrical, stochastic write operations with high energy and reliability challenges. Narrow write margins, process variability, and thermal fluctuations can cause errors, while repeated high-current writes degrade endurance. A data-driven self-termination write circuit (DDSTWC) with enhanced reliability using mux logic in 28 nm CMOS is proposed to address this. It achieves 85% power savings over non-self-terminating schemes. The layout, implemented in 28 nm UMC PDK, occupies 25.32 μm × 27.36 μm and ensures symmetry, scalability, and minimal edge variations, meeting industry-standard design requirements.

人工智能（AI）和边缘计算的兴起需要高速、低延迟、非易失性和低功耗的内存解决方案。SRAM、DRAM、闪存和EEPROM等传统选项通常面临可扩展性和效率方面的限制。基于磁隧道结（MTJ）的自旋转移转矩磁阻RAM （STT-MRAM）由于零待机功率和CMOS兼容性而成为强有力的候选者。STT-MRAM结合了类似sram的速度、类似dram的密度和类似闪存的非易失性。尽管如此，它的单晶体管一mtj （1 T-1MTJ）电池仍然面临着不对称、随机的高能量写入操作和可靠性挑战。狭窄的写入空间、进程可变性和热波动可能导致错误，而重复的大电流写入会降低持久性。针对这一问题，提出了一种基于多路复用逻辑的数据驱动自终止写入电路（DDSTWC）。它比非自终止方案节省85%的电力。该布局采用28纳米UMC PDK实现，尺寸为25.32 μm × 27.36 μm，确保了对称性、可扩展性和最小边缘变化，符合行业标准设计要求。

{"title":"A data-driven self-terminating write circuit with enhanced reliability for STT-MRAM using MUX logic","authors":"Ravi S. Siddanath, Mohit Gupta, Souvik Kumar Das, G.K. Prasad, Manish Goswami, Kavindra Kandpal","doi":"10.1016/j.microrel.2026.116006","DOIUrl":"10.1016/j.microrel.2026.116006","url":null,"abstract":"<div><div>The rise of artificial intelligence (AI) and edge computing demands memory solutions that are high-speed, low-latency, nonvolatile, and low-power. Conventional options such as SRAM, DRAM, flash, and EEPROM often face limitations in scalability and efficiency. Magnetic tunnel junction (MTJ) based spin-transfer torque magnetoresistive RAM (STT-MRAM) emerges as a strong candidate due to zero standby power and CMOS compatibility. STT-MRAM combines SRAM-like speed, DRAM-like density, and flash-like non-volatility. Still, its one-transistor one-MTJ (1 T-1MTJ) cell suffers from asymmetrical, stochastic write operations with high energy and reliability challenges. Narrow write margins, process variability, and thermal fluctuations can cause errors, while repeated high-current writes degrade endurance. A data-driven self-termination write circuit (DDSTWC) with enhanced reliability using mux logic in 28 nm CMOS is proposed to address this. It achieves 85% power savings over non-self-terminating schemes. The layout, implemented in 28 nm UMC PDK, occupies 25.32 μm × 27.36 μm and ensures symmetry, scalability, and minimal edge variations, meeting industry-standard design requirements.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116006"},"PeriodicalIF":1.9,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Neural network approach to NBTI/HCD coupled failure analysis of MOS ICs 基于神经网络的MOS集成电路NBTI/HCD耦合失效分析

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-13 DOI: 10.1016/j.microrel.2025.115996

Zhenyu Wu, Zhen Chai, Binyang Liu, Menglong Liu

In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D {V_G, V_D} voltage plane with neural network. The voltage explicit models of NBTI and HCD are revised by reaction-diffusion (R-D) and energy-driven models, respectively. NBTI/HCD coupling model describing threshold voltage shift (ΔV_th) is constructed based on the physics-informed neural network (PINN)-long short-term memory (LSTM) neural network model in the form of a voltage weight factor on the 2-D voltage plane, which is used to predict the degradation of the performance of ring oscillator (RO) and low-noise amplifier (LNA). In comparison to experimental data throughout the bias space, the predicted ΔV_th has an average relative error of 11.92% under various stress conditions. The circuit simulation shows that the average frequency degradation error of RO is 8.6%. When predicting the noise figure (NF) and S-parameters of LNA, it is consistent with the experimental degradation trend. This work provides a lesson in combining the reliability of neural networks with integrated circuits.

本文利用神经网络在二维{VG， VD}电压平面上建立了负偏置温度不稳定性(NBTI)/热载流子退化（HCD）耦合失效模型。分别采用反应扩散模型和能量驱动模型对NBTI和HCD的电压显式模型进行了修正。基于物理信息神经网络（PINN）长短期记忆（LSTM）神经网络模型，在二维电压平面上以电压权重因子的形式建立了描述阈值电压漂移的NBTI/HCD耦合模型（ΔVth），用于预测环形振荡器（RO）和低噪声放大器（LNA）的性能退化。与整个偏置空间的实验数据比较，预测的ΔVth在各种应力条件下的平均相对误差为11.92%。电路仿真结果表明，RO的平均频率衰减误差为8.6%。在预测LNA的噪声系数（NF）和s参数时，与实验退化趋势一致。这项工作为将神经网络的可靠性与集成电路相结合提供了一个教训。

{"title":"Neural network approach to NBTI/HCD coupled failure analysis of MOS ICs","authors":"Zhenyu Wu, Zhen Chai, Binyang Liu, Menglong Liu","doi":"10.1016/j.microrel.2025.115996","DOIUrl":"10.1016/j.microrel.2025.115996","url":null,"abstract":"<div><div>In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D {V<sub>G</sub>, V<sub>D</sub>} voltage plane with neural network. The voltage explicit models of NBTI and HCD are revised by reaction-diffusion (R-D) and energy-driven models, respectively. NBTI/HCD coupling model describing threshold voltage shift (ΔV<sub>th</sub>) is constructed based on the physics-informed neural network (PINN)-long short-term memory (LSTM) neural network model in the form of a voltage weight factor on the 2-D voltage plane, which is used to predict the degradation of the performance of ring oscillator (RO) and low-noise amplifier (LNA). In comparison to experimental data throughout the bias space, the predicted ΔV<sub>th</sub> has an average relative error of 11.92% under various stress conditions. The circuit simulation shows that the average frequency degradation error of RO is 8.6%. When predicting the noise figure (NF) and S-parameters of LNA, it is consistent with the experimental degradation trend. This work provides a lesson in combining the reliability of neural networks with integrated circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115996"},"PeriodicalIF":1.9,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-volatile SRAM based on emerging memory: A comprehensive review and reliability challenges 基于新兴存储器的非易失性SRAM：全面回顾和可靠性挑战

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-08 DOI: 10.1016/j.microrel.2025.115995

Huimeng Guo , Yujia Li , Tingrui Ren , Yiqing Li , Liang Wang , Yuanfu Zhao

With the rapid advancement of information technology, the demand for high-reliability and energy-efficient data processing and storage systems has grown significantly. Emerging memory technologies offer promising solutions due to their high access speeds, low power consumption, nanoscale dimensions, and CMOS compatibility. Non-volatile SRAM (NVSRAM) has attracted attention for combining SRAM with emerging memory technologies, enabling nanosecond-scale data backup and recovery with energy consumption reduced to the picojoule-per-bit level. This review identifies key reliability challenges associated with NVSRAM based on emerging memory devices, with a focus on cell design and optimization strategies, system-level architectures and control schemes, and extended applications in computing-in-memory. Moreover, reliability challenges at the device, system, and extreme-environment levels are discussed. This work aims to provide a theoretical and technological foundation for future high-reliability, energy-efficient memory solutions, while highlighting open challenges and the envisioned development of dedicated simulation frameworks for NVSRAM design and evaluation.

随着信息技术的飞速发展，人们对高可靠性、高能效的数据处理和存储系统的需求日益增长。新兴存储技术由于其高访问速度、低功耗、纳米级尺寸和CMOS兼容性而提供了有前途的解决方案。非易失性SRAM （NVSRAM）由于将SRAM与新兴存储技术相结合，能够实现纳秒级的数据备份和恢复，同时将能耗降低到每比特皮焦耳水平而引起了人们的关注。本综述确定了基于新兴存储设备的NVSRAM相关的关键可靠性挑战，重点关注单元设计和优化策略、系统级架构和控制方案，以及在内存计算中的扩展应用。此外，还讨论了设备、系统和极端环境级别的可靠性挑战。这项工作旨在为未来的高可靠性、节能存储器解决方案提供理论和技术基础，同时强调开放的挑战和NVSRAM设计和评估专用仿真框架的设想发展。

{"title":"Non-volatile SRAM based on emerging memory: A comprehensive review and reliability challenges","authors":"Huimeng Guo , Yujia Li , Tingrui Ren , Yiqing Li , Liang Wang , Yuanfu Zhao","doi":"10.1016/j.microrel.2025.115995","DOIUrl":"10.1016/j.microrel.2025.115995","url":null,"abstract":"<div><div>With the rapid advancement of information technology, the demand for high-reliability and energy-efficient data processing and storage systems has grown significantly. Emerging memory technologies offer promising solutions due to their high access speeds, low power consumption, nanoscale dimensions, and CMOS compatibility. Non-volatile SRAM (NVSRAM) has attracted attention for combining SRAM with emerging memory technologies, enabling nanosecond-scale data backup and recovery with energy consumption reduced to the picojoule-per-bit level. This review identifies key reliability challenges associated with NVSRAM based on emerging memory devices, with a focus on cell design and optimization strategies, system-level architectures and control schemes, and extended applications in computing-in-memory. Moreover, reliability challenges at the device, system, and extreme-environment levels are discussed. This work aims to provide a theoretical and technological foundation for future high-reliability, energy-efficient memory solutions, while highlighting open challenges and the envisioned development of dedicated simulation frameworks for NVSRAM design and evaluation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115995"},"PeriodicalIF":1.9,"publicationDate":"2026-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on the mechanism and growth behavior of copper micro-bump array interconnection via electroplating based on an accelerator–suppressor-leveler system 基于加速-抑制-调平系统的电镀铜微凹凸阵列互连机理及生长行为研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-07 DOI: 10.1016/j.microrel.2025.115994

Yixin Pan, Haoze Yang, Xiaokang Liu, Yuting Zhong, Junhui Li

With the advancement of packaging technology, CuCu direct interconnection has become a major research focus. Electroplating bonding enables CuCu interconnection at room temperature without applied pressure, offering lower bonding temperatures compared to other low-temperature CuCu bonding techniques. However, achieving uniform and dense plating growth remains the core challenge of this technology. This study proposes an electroplating bonding process for micro copper pillar array interconnections and conducts finite element simulations and electroplating bonding experiments using an accelerator-suppressor-leveler (ASL) system. The results show that the ASL system produces conformal deposition characteristics due to the high coverage and uniform distribution of levelers and suppressors in the bonding area. The Janus Green B (JGB) system produces rough plating contours with poor bonding quality, while both Dodecyl trimethyl ammonium chloride (DTAC) and 4,6-dimethyl-2-mercaptopyrimidine (DMP) systems yield well-defined plating profiles with superior bonding performance. However, due to the excessive plating thickness in the DMP system, the DTAC system was selected for the temperature cycling test. The results showed that after 100 thermal cycles, the average shear strength of the samples decreased by only 8.35 MPa, and the fracture location remained unchanged, still located at the interface between the plating layer and the lower bump. This indicates that the samples bonded using the DTAC system exhibit good thermomechanical reliability under the given process conditions.

随着封装技术的进步，CuCu直接互连已成为一个重要的研究热点。电镀键合使CuCu在室温下无需施加压力即可互连，与其他低温CuCu键合技术相比，提供更低的键合温度。然而，实现均匀和致密的镀层生长仍然是该技术的核心挑战。本研究提出了一种微细铜柱阵列互连的电镀键合工艺，并利用加速-抑制-调平（ASL）系统进行了有限元模拟和电镀键合实验。结果表明，由于均匀分布的调平剂和抑制剂在键合区域的高覆盖率和均匀分布，ASL系统产生了保形沉积特性。Janus Green B （JGB）体系的镀层轮廓粗糙，键合质量差，而十二烷基三甲基氯化铵（DTAC）和4,6-二甲基-2-巯基嘧啶（DMP）体系的镀层轮廓轮廓清晰，键合性能优异。但由于DMP体系中镀层厚度过大，所以选择DTAC体系进行温度循环试验。结果表明：经过100次热循环后，试样的平均抗剪强度仅下降8.35 MPa，断口位置保持不变，仍位于镀层与下凸块的交界面；这表明，在给定的工艺条件下，使用DTAC体系粘合的样品具有良好的热机械可靠性。

{"title":"Study on the mechanism and growth behavior of copper micro-bump array interconnection via electroplating based on an accelerator–suppressor-leveler system","authors":"Yixin Pan, Haoze Yang, Xiaokang Liu, Yuting Zhong, Junhui Li","doi":"10.1016/j.microrel.2025.115994","DOIUrl":"10.1016/j.microrel.2025.115994","url":null,"abstract":"<div><div>With the advancement of packaging technology, Cu<img>Cu direct interconnection has become a major research focus. Electroplating bonding enables Cu<img>Cu interconnection at room temperature without applied pressure, offering lower bonding temperatures compared to other low-temperature Cu<img>Cu bonding techniques. However, achieving uniform and dense plating growth remains the core challenge of this technology. This study proposes an electroplating bonding process for micro copper pillar array interconnections and conducts finite element simulations and electroplating bonding experiments using an accelerator-suppressor-leveler (ASL) system. The results show that the ASL system produces conformal deposition characteristics due to the high coverage and uniform distribution of levelers and suppressors in the bonding area. The Janus Green B (JGB) system produces rough plating contours with poor bonding quality, while both Dodecyl trimethyl ammonium chloride (DTAC) and 4,6-dimethyl-2-mercaptopyrimidine (DMP) systems yield well-defined plating profiles with superior bonding performance. However, due to the excessive plating thickness in the DMP system, the DTAC system was selected for the temperature cycling test. The results showed that after 100 thermal cycles, the average shear strength of the samples decreased by only 8.35 MPa, and the fracture location remained unchanged, still located at the interface between the plating layer and the lower bump. This indicates that the samples bonded using the DTAC system exhibit good thermomechanical reliability under the given process conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115994"},"PeriodicalIF":1.9,"publicationDate":"2026-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Trap charges reliability in a heterojunction double gate ferroelectric p-n-i-n tunnel FET (HJ-DG-Fe p-n-i-n TFET): A simulation study 异质结双栅铁电p-n-i-n隧道FET （HJ-DG-Fe p-n-i-n FET）陷阱电荷可靠性的模拟研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-07 DOI: 10.1016/j.microrel.2025.115987

Shib Sankar Das , Subir Kumar Sarkar

The present research explores the uniform interface trap charges (ITCs) impact on the electrical characteristics of a heterojunction double-gate ferroelectric p-n-i-n tunnel field-effect transistor (HJ DG Fe p-n-i-n TFET). The conventional tunnel field effect transistor (TFET) is modified to minimize ambipolarity and increase ON state current by employing a heterojunction, a heavily doped n⁺ pocket at the source-channel junction, and a 4nm non-perovskite ferroelectric layer in the gate stack, thereby improving device performance with hysteresis-free drive current. The impact of both positive and negative interface trap charges on DC, RF/Analog characteristics are analyzed using the Silvaco ATLAS device simulator. Numerous performance metrics, including as ON current, switching ratio, subthreshold swing, transconductance, gain, cutoff frequency, power consumption etc. are enhanced by positive ITCs and diminished by negative ITCs. Additionally, linearity characteristics such as transconductance coefficients (gm₂ and gm₃), VIP2, VIP3, IIP3 and IMD3 are compared for both traps. A comparison table highlighting major electrical parameters for the proposed device alongside existing structures has been presented. The proposed device exhibits reduced susceptibility to ITCs and has enhanced performance and reliability, making it an enduring candidate for low-power analog and digital applications.

本研究探讨了均匀界面陷阱电荷（ITCs）对异质结双栅铁电p-n-i-n隧道场效应晶体管（HJ DG Fe p-n-i-n TFET）电学特性的影响。对传统的隧道场效应晶体管（ttfet）进行了改进，通过采用异质结、源沟道结处的高掺杂n+口袋和栅极堆中的4nm非钙钛矿铁电层来减小双极性和增加ON状态电流，从而提高了器件的性能和无迟滞驱动电流。利用Silvaco ATLAS器件模拟器分析了正负界面陷阱电荷对直流、射频/模拟特性的影响。许多性能指标，包括导通电流、开关比、亚阈值摆幅、跨导、增益、截止频率、功耗等，都因正ITCs而增强，因负ITCs而减弱。此外，还比较了两种陷阱的线性特性，如跨导系数（gm2和gm3）、VIP2、VIP3、IIP3和IMD3。提出了一个比较表，突出了拟议装置与现有结构的主要电气参数。所提出的器件对ITCs的敏感性降低，性能和可靠性增强，使其成为低功耗模拟和数字应用的持久候选者。

{"title":"Trap charges reliability in a heterojunction double gate ferroelectric p-n-i-n tunnel FET (HJ-DG-Fe p-n-i-n TFET): A simulation study","authors":"Shib Sankar Das , Subir Kumar Sarkar","doi":"10.1016/j.microrel.2025.115987","DOIUrl":"10.1016/j.microrel.2025.115987","url":null,"abstract":"<div><div>The present research explores the uniform interface trap charges (ITCs) impact on the electrical characteristics of a heterojunction double-gate ferroelectric p-n-i-n tunnel field-effect transistor (HJ DG Fe p-n-i-n TFET). The conventional tunnel field effect transistor (TFET) is modified to minimize ambipolarity and increase ON state current by employing a heterojunction, a heavily doped n<sup>+</sup> pocket at the source-channel junction, and a 4nm non-perovskite ferroelectric layer in the gate stack, thereby improving device performance with hysteresis-free drive current. The impact of both positive and negative interface trap charges on DC, RF/Analog characteristics are analyzed using the Silvaco ATLAS device simulator. Numerous performance metrics, including as ON current, switching ratio, subthreshold swing, transconductance, gain, cutoff frequency, power consumption etc. are enhanced by positive ITCs and diminished by negative ITCs. Additionally, linearity characteristics such as transconductance coefficients (gm<sub>2</sub> and gm<sub>3</sub>), VIP2, VIP3, IIP3 and IMD3 are compared for both traps. A comparison table highlighting major electrical parameters for the proposed device alongside existing structures has been presented. The proposed device exhibits reduced susceptibility to ITCs and has enhanced performance and reliability, making it an enduring candidate for low-power analog and digital applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115987"},"PeriodicalIF":1.9,"publicationDate":"2026-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Application-representative high-frequency power cycling of SiC power modules used in inverters and rectifiers 用于逆变器和整流器的SiC功率模块的应用代表性高频功率循环

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-06 DOI: 10.1016/j.microrel.2026.115997

Rodrigo Drummond, Bernardo Cougo, Duc-Hoan Tran

Significant temperature variation in frequencies from 10 to 100 Hz was observed in SiC dies used in inverter and rectifier applications. These fast thermal cycles can significantly reduce SiC power module lifetimes. This paper presents an approach and testbench to investigate module aging due to these cycles. The testbench creates die temperature variations up to 40 K at 10 to 100 Hz. The power module is stressed as in a real inverter or rectifier, maintaining the same average temperature and power cycles at the frequency of sinusoidal current. Thermal cycle amplitudes are selected using accurate thermoelectrical model of the dies. This model is obtained via Modified Opposition Method for switching and conduction losses of SiC dies and a fast thermal camera for dynamic temperature measurements and estimation of self and mutual thermal impedance of the dies. Experimental results demonstrate that the algorithm accurately imposes the desired high-frequency power cycles in SiC inside power module.

在逆变器和整流器应用中使用的SiC模具中，观察到频率从10到100 Hz的显著温度变化。这些快速的热循环可以显著降低SiC功率模块的使用寿命。本文提出了一种研究这些循环引起的模块老化的方法和试验台。测试台架在10至100 Hz下产生高达40 K的模具温度变化。功率模块的受力与真正的逆变器或整流器一样，在正弦电流频率下保持相同的平均温度和功率周期。利用模具的精确热电模型选择热循环幅值。该模型是通过SiC芯片开关损耗和导通损耗的修正对立法和快速热成像仪进行动态测温和估计芯片的自热阻抗和互热阻抗得到的。实验结果表明，该算法能准确地在功率模块内部施加所需的高频功率周期。

引用次数: 0

Structural optimization design of LTCC substrate and their impacts on thermal performances of system-in-package LTCC基板结构优化设计及其对系统级封装热性能的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-05 DOI: 10.1016/j.microrel.2025.115992

Ge Shi , Zhong Jun Yu , Zheng Xu , Xing Yao Zeng , Yan Wei Dai , Fei Qin , Hai Bo Zhang

System-in-package (SiP) technology utilizing low temperature cofired ceramic substrates (LTCC-SiP) offer millimeter-wave components higher integration density and superior radio frequency (RF) performance. However, the thermal management challenges of LTCC-SiP require urgent resolution due to the low thermal conductivity of LTCC materials and the increasingly high thermal dissipation demands of power amplifier (PA) chips. To better address this situation, this study investigates the thermal performance of LTCC-SiP through heat transfer and computational fluid dynamics (CFD) analyses. The research focuses on: (1) determining the equivalent thermal conductivity of LTCC substrates with varying filler diameters, pitches, aspect ratios, as well as different conductor and ground grid distributions; (2) evaluating the junction temperature and thermal resistance of SiP structures incorporating LTCC substrates, considering factors such as chip area ratio, chip thickness, frame and LTCC cavity/substrate heights, frame width, frame material, cavity potting material, and the presence of liquid-cooled channels in the cover; and (3) assessing the junction temperature and thermal resistance in three-dimensional stacking configurations with LTCC substrates. Research findings indicate that the thermal performance of LTCC-SiP can be enhanced through multiple methodologies. Furthermore, the findings are synthesized into practical design charts and guidelines to facilitate engineering applications.

采用低温共烧陶瓷基板（LTCC-SiP）的系统级封装（SiP）技术可为毫米波组件提供更高的集成密度和卓越的射频（RF）性能。然而，由于LTCC材料的低导热性和功率放大器（PA）芯片越来越高的散热要求，LTCC- sip的热管理挑战急需解决。为了更好地解决这一问题，本研究通过传热和计算流体动力学（CFD）分析来研究LTCC-SiP的热性能。研究的重点是：(1)确定不同填充物直径、间距、长径比以及不同导体和地网分布的LTCC衬底的等效导热系数；(2)考虑芯片面积比、芯片厚度、框架和LTCC空腔/衬底高度、框架宽度、框架材料、空腔灌封材料以及覆盖层中液冷通道的存在等因素，评估包含LTCC衬底的SiP结构的结温和热阻；(3)评估LTCC基板三维堆叠结构的结温和热阻。研究结果表明，LTCC-SiP的热性能可以通过多种方法得到提高。此外，研究结果被综合成实用的设计图表和指南，以促进工程应用。

{"title":"Structural optimization design of LTCC substrate and their impacts on thermal performances of system-in-package","authors":"Ge Shi , Zhong Jun Yu , Zheng Xu , Xing Yao Zeng , Yan Wei Dai , Fei Qin , Hai Bo Zhang","doi":"10.1016/j.microrel.2025.115992","DOIUrl":"10.1016/j.microrel.2025.115992","url":null,"abstract":"<div><div>System-in-package (SiP) technology utilizing low temperature cofired ceramic substrates (LTCC-SiP) offer millimeter-wave components higher integration density and superior radio frequency (RF) performance. However, the thermal management challenges of LTCC-SiP require urgent resolution due to the low thermal conductivity of LTCC materials and the increasingly high thermal dissipation demands of power amplifier (PA) chips. To better address this situation, this study investigates the thermal performance of LTCC-SiP through heat transfer and computational fluid dynamics (CFD) analyses. The research focuses on: (1) determining the equivalent thermal conductivity of LTCC substrates with varying filler diameters, pitches, aspect ratios, as well as different conductor and ground grid distributions; (2) evaluating the junction temperature and thermal resistance of SiP structures incorporating LTCC substrates, considering factors such as chip area ratio, chip thickness, frame and LTCC cavity/substrate heights, frame width, frame material, cavity potting material, and the presence of liquid-cooled channels in the cover; and (3) assessing the junction temperature and thermal resistance in three-dimensional stacking configurations with LTCC substrates. Research findings indicate that the thermal performance of LTCC-SiP can be enhanced through multiple methodologies. Furthermore, the findings are synthesized into practical design charts and guidelines to facilitate engineering applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115992"},"PeriodicalIF":1.9,"publicationDate":"2026-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0