Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115973
Guozhuang Fan , Jinzhu Zhou , Qiangqiang Lin , Jiancheng Shi
This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.
{"title":"Uncertainty quantification in microelectronic packaging using feedback-enhanced adaptive polynomial chaos expansion","authors":"Guozhuang Fan , Jinzhu Zhou , Qiangqiang Lin , Jiancheng Shi","doi":"10.1016/j.microrel.2025.115973","DOIUrl":"10.1016/j.microrel.2025.115973","url":null,"abstract":"<div><div>This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115973"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115977
Yanyong Wang , Liang He , Yanfang Li , Zhenni Wang , Zhongyang Li , Hao Zhou , Kaihe Liu , Maolin Zhang
This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (VTH) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.
{"title":"Investigation of interface traps properties induced by NBTI effects at different interfaces of VDMOS","authors":"Yanyong Wang , Liang He , Yanfang Li , Zhenni Wang , Zhongyang Li , Hao Zhou , Kaihe Liu , Maolin Zhang","doi":"10.1016/j.microrel.2025.115977","DOIUrl":"10.1016/j.microrel.2025.115977","url":null,"abstract":"<div><div>This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (<em>V</em><sub><em>TH</em></sub>) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115977"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-08DOI: 10.1016/j.microrel.2025.115979
Yan Liu , Yanhua Ma , Chong Pan
In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.
{"title":"Investigation of thermal contact resistance, incident depth, incident angle, drain voltage and ambient temperature on single event transient during self-heating","authors":"Yan Liu , Yanhua Ma , Chong Pan","doi":"10.1016/j.microrel.2025.115979","DOIUrl":"10.1016/j.microrel.2025.115979","url":null,"abstract":"<div><div>In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115979"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The wide application of portable electronic devices in high-vibration environments puts increasing demands on accurate and efficient modeling of the dynamic behavior of printed circuit boards (PCBs). To address this challenge, this study proposes a multiscale modeling approach based on a partitioned homogenization strategy. By integrating microscale material properties extraction with macroscale structural modal analysis, a modeling framework is established that significantly improves computational efficiency while preserving the material heterogeneity of wiring layers. The proposed method is comprehensively validated through hammer impact tests and comparison with a detailed wiring model. For a four-layer PCB, the proposed model predicts the first four natural frequencies with a maximum error of 11 %, while reducing the computational time by 69.5 % compared to the detailed model containing more than 10 million elements. Furthermore, a sensitivity analysis of the partition size reveals that model accuracy improves with smaller partitions, while computational efficiency exhibits a non-monotonic trend. An optimal balance between accuracy and efficiency is achieved when the partition size is approximately 6 to 10 times the minimum copper wire width (0.5 mm). The proposed method serves as a practical modeling solution for high-performance PCB vibration analysis, enabling rapid modal evaluation for complex electronic assemblies and providing a practical tool for PCB structural optimization in engineering applications.
{"title":"A novel partitioned homogenization approach for rapid and accurate vibration analysis of printed circuit boards","authors":"Mengxuan Cheng , Yong Zhou , Guoshun Wan , Xiaohui Zhao , Zhiyan Zhao , Hao Zheng , Yuxi Jia","doi":"10.1016/j.microrel.2025.115972","DOIUrl":"10.1016/j.microrel.2025.115972","url":null,"abstract":"<div><div>The wide application of portable electronic devices in high-vibration environments puts increasing demands on accurate and efficient modeling of the dynamic behavior of printed circuit boards (PCBs). To address this challenge, this study proposes a multiscale modeling approach based on a partitioned homogenization strategy. By integrating microscale material properties extraction with macroscale structural modal analysis, a modeling framework is established that significantly improves computational efficiency while preserving the material heterogeneity of wiring layers. The proposed method is comprehensively validated through hammer impact tests and comparison with a detailed wiring model. For a four-layer PCB, the proposed model predicts the first four natural frequencies with a maximum error of 11 %, while reducing the computational time by 69.5 % compared to the detailed model containing more than 10 million elements. Furthermore, a sensitivity analysis of the partition size reveals that model accuracy improves with smaller partitions, while computational efficiency exhibits a non-monotonic trend. An optimal balance between accuracy and efficiency is achieved when the partition size is approximately 6 to 10 times the minimum copper wire width (0.5 mm). The proposed method serves as a practical modeling solution for high-performance PCB vibration analysis, enabling rapid modal evaluation for complex electronic assemblies and providing a practical tool for PCB structural optimization in engineering applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115972"},"PeriodicalIF":1.9,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.microrel.2025.115974
Haiwei Xue , Fangfa Fu , Jinxiang Wang , Xudong Huang , Menghua Zhang , Lingxiang Qu
Digital signal processors (DSPs) are increasingly being utilized in nuclear plants and instruments, and the transient dose rate effects (TDREs) they encounter due to radiation have become a significant concern. In this paper, the TDREs of DSP were investigated through experiments conducted at the Northwest Institute of Nuclear Technology in China. The DSP, designed to be radiation-hardened (Rad-Hard) and manufactured using a 0.13 μm Silicon-On-Insulator(SOI) process, was tested under four dose-rates ranging from 1.5 × 1011 Rad(Si)/s to 2.0 × 1011 Rad(Si)/s. The experimental results indicate that the disturbances in voltage and current induced by transient dose rate radiation are small, owing to radiation-hardened-by-design and the SOI process. The recovery time of the voltage in Rad-Hard DSP is shorter than that of conventional bulk silicon devices. This is attributed to the SOI MOS device having only horizontal parasitic junctions, a result of the presence of the buried oxide layer. The experimental results also demonstrate that the transient dose rate (TDR) threshold of the Rad-Hard DSP circuit can reach up to 1.6 × 1011 Rad(Si)/s without functional failures and up to 2.0 × 1011 Rad(Si)/s without latchup. In this work, the Rad-Hard DSP circuit's ability to withstand transient dose rate irradiation is shown to be one order of magnitude greater than that of bulk silicon counterparts.
{"title":"Experimental study of transient dose rate effect on radiation-hardened digital signal processor","authors":"Haiwei Xue , Fangfa Fu , Jinxiang Wang , Xudong Huang , Menghua Zhang , Lingxiang Qu","doi":"10.1016/j.microrel.2025.115974","DOIUrl":"10.1016/j.microrel.2025.115974","url":null,"abstract":"<div><div>Digital signal processors (DSPs) are increasingly being utilized in nuclear plants and instruments, and the transient dose rate effects (TDREs) they encounter due to radiation have become a significant concern. In this paper, the TDREs of DSP were investigated through experiments conducted at the Northwest Institute of Nuclear Technology in China. The DSP, designed to be radiation-hardened (Rad-Hard) and manufactured using a 0.13 μm Silicon-On-Insulator(SOI) process, was tested under four dose-rates ranging from 1.5 × 10<sup>11</sup> Rad(Si)/s to 2.0 × 10<sup>11</sup> Rad(Si)/s. The experimental results indicate that the disturbances in voltage and current induced by transient dose rate radiation are small, owing to radiation-hardened-by-design and the SOI process. The recovery time of the voltage in Rad-Hard DSP is shorter than that of conventional bulk silicon devices. This is attributed to the SOI MOS device having only horizontal parasitic junctions, a result of the presence of the buried oxide layer. The experimental results also demonstrate that the transient dose rate (TDR) threshold of the Rad-Hard DSP circuit can reach up to 1.6 × 10<sup>11</sup> Rad(Si)/s without functional failures and up to 2.0 × 10<sup>11</sup> Rad(Si)/s without latchup. In this work, the Rad-Hard DSP circuit's ability to withstand transient dose rate irradiation is shown to be one order of magnitude greater than that of bulk silicon counterparts.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115974"},"PeriodicalIF":1.9,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1016/j.microrel.2025.115971
Zikang Luo , Xiuqi Wang , Yifan Li , Pengjie Zhou , Liang Chen , Chengdong Bai , Mingyu Li , Hongjun Ji
This work focuses on optimizing the bonding performance and enhancing the reliability of copper (Cu) wires on gold (Au) pads for MEMS devices, aiming to address the critical role of bonding wire reliability in ensuring overall device performance. Through orthogonal experiments combined with response surface regression analysis, the effects of four key process parameters (bonding force, ultrasonic power, ultrasonic time, and bonding temperature) on bonding quality were systematically investigated, with a specific focus on their coupling mechanisms. The results revealed that bonding force and ultrasonic power are the dominant factors determining the bonding pull force. A medium parameter combination (bonding force of 25 gf, ultrasonic power of 0.85 W, ultrasonic time of 180 ms, and bonding temperature of 50 °C) achieved the optimal bonding quality. This superiority arises from the balanced interplay between ultrasonic softening and grain refinement during bonding. Moderate plastic deformation of the Cu wire promotes uniform dislocation activation and annihilation at grain boundaries, avoids excessive stress concentration or material damage, and facilitates the formation of uniform (111) and (001) textures at the interface. Notably, CuAu intermetallic compounds (IMCs) were scarcely observed, eliminating the risk of brittleness caused by abnormal IMCs growth. Reliability tests, including high-temperature aging and thermal cycling, demonstrated that long-term thermal stress leads to performance degradation of bonding joints, primarily driven by interface cracks. After 25 days of aging at 150 °C, the bond pull force dropped below 6 gf. After 800 cycles, the pull force decreased to approximately 7.5 gf. This work clarifies the parameter coupling mechanisms and reliability rules of ultrasonic wire bonding of Cu wires on Au pads, practical theoretical and experimental support for improving the bonding reliability of MEMS devices.
{"title":"Optimization and reliability of ultrasonic wedge bonding performance of copper wires on gold pads for MEMS devices","authors":"Zikang Luo , Xiuqi Wang , Yifan Li , Pengjie Zhou , Liang Chen , Chengdong Bai , Mingyu Li , Hongjun Ji","doi":"10.1016/j.microrel.2025.115971","DOIUrl":"10.1016/j.microrel.2025.115971","url":null,"abstract":"<div><div>This work focuses on optimizing the bonding performance and enhancing the reliability of copper (Cu) wires on gold (Au) pads for MEMS devices, aiming to address the critical role of bonding wire reliability in ensuring overall device performance. Through orthogonal experiments combined with response surface regression analysis, the effects of four key process parameters (bonding force, ultrasonic power, ultrasonic time, and bonding temperature) on bonding quality were systematically investigated, with a specific focus on their coupling mechanisms. The results revealed that bonding force and ultrasonic power are the dominant factors determining the bonding pull force. A medium parameter combination (bonding force of 25 gf, ultrasonic power of 0.85 W, ultrasonic time of 180 ms, and bonding temperature of 50 °C) achieved the optimal bonding quality. This superiority arises from the balanced interplay between ultrasonic softening and grain refinement during bonding. Moderate plastic deformation of the Cu wire promotes uniform dislocation activation and annihilation at grain boundaries, avoids excessive stress concentration or material damage, and facilitates the formation of uniform (111) and (001) textures at the interface. Notably, Cu<img>Au intermetallic compounds (IMCs) were scarcely observed, eliminating the risk of brittleness caused by abnormal IMCs growth. Reliability tests, including high-temperature aging and thermal cycling, demonstrated that long-term thermal stress leads to performance degradation of bonding joints, primarily driven by interface cracks. After 25 days of aging at 150 °C, the bond pull force dropped below 6 gf. After 800 cycles, the pull force decreased to approximately 7.5 gf. This work clarifies the parameter coupling mechanisms and reliability rules of ultrasonic wire bonding of Cu wires on Au pads, practical theoretical and experimental support for improving the bonding reliability of MEMS devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115971"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1016/j.microrel.2025.115927
Francesco Iannuzzo, Matteo Meneghini, Giovanna Mura, Paolo Cova, Nicola Delmonte
{"title":"Editorial on the Special Issue related to the ESREF 2024 conference","authors":"Francesco Iannuzzo, Matteo Meneghini, Giovanna Mura, Paolo Cova, Nicola Delmonte","doi":"10.1016/j.microrel.2025.115927","DOIUrl":"10.1016/j.microrel.2025.115927","url":null,"abstract":"","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115927"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145693012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-01DOI: 10.1016/j.microrel.2025.115926
Mohammad M. Hamasha , Sa'd Hamasha , Khalid Alzoubi , Raghad Massadeh , Khozima Hamasha
{"title":"Corrigendum to “comparative analysis of mechanical and thermal stresses in ITO and AZO thin films on flexible PET substrates for flexible electronic applications” [microelectronics reliability volume 175, December 2025, 115921]","authors":"Mohammad M. Hamasha , Sa'd Hamasha , Khalid Alzoubi , Raghad Massadeh , Khozima Hamasha","doi":"10.1016/j.microrel.2025.115926","DOIUrl":"10.1016/j.microrel.2025.115926","url":null,"abstract":"","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115926"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145693005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-30DOI: 10.1016/j.microrel.2025.115970
Mingxing Du, Guosheng Hong, Jianxiong Yang
This paper proposes a dual-parameter decoupling-based method for precise monitoring of bonding wire lift-off in both the IGBT and freewheeling diode (FWD) of half-bridge modules. Through analysis of the controlled IGBT turn-off transient, it is found that the complementary IGBT collector-emitter voltage undershoot VCE2(np) contains aging information from both IGBT and FWD bonding wires, while the Kelvin emitter voltage undershoot VeE2(np) primarily reflects IGBT bonding wire aging. The decoupling algorithm first utilizes VeE2(np) to isolate the IGBT aging component and then extracts the standalone FWD aging signature from VCE2(np). Experimental results confirm the method's robustness under varying load current and junction temperature, with interference compensated by a linear calibration model. The approach is particularly advantageous in systems with stable bus voltage, where this major interference is inherently minimized. Since the method leverages inherent electrical characteristics, it provides a practical solution for preventive maintenance in power electronic systems.
{"title":"Bonding wire aging monitoring method for IGBT and FWD based on dual-parameter decoupling","authors":"Mingxing Du, Guosheng Hong, Jianxiong Yang","doi":"10.1016/j.microrel.2025.115970","DOIUrl":"10.1016/j.microrel.2025.115970","url":null,"abstract":"<div><div>This paper proposes a dual-parameter decoupling-based method for precise monitoring of bonding wire lift-off in both the IGBT and freewheeling diode (FWD) of half-bridge modules. Through analysis of the controlled IGBT turn-off transient, it is found that the complementary IGBT collector-emitter voltage undershoot <em>V</em><sub>CE2(np)</sub> contains aging information from both IGBT and FWD bonding wires, while the Kelvin emitter voltage undershoot <em>V</em><sub>eE2(np)</sub> primarily reflects IGBT bonding wire aging. The decoupling algorithm first utilizes <em>V</em><sub>eE2(np)</sub> to isolate the IGBT aging component and then extracts the standalone FWD aging signature from <em>V</em><sub>CE2(np)</sub>. Experimental results confirm the method's robustness under varying load current and junction temperature, with interference compensated by a linear calibration model. The approach is particularly advantageous in systems with stable bus voltage, where this major interference is inherently minimized. Since the method leverages inherent electrical characteristics, it provides a practical solution for preventive maintenance in power electronic systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115970"},"PeriodicalIF":1.9,"publicationDate":"2025-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.microrel.2025.115956
Cadmus Yuan, Jian-Cheng Hong, Pin-Sian Li
Solder joint reliability is a critical concern in advanced electronic packaging, especially as heterogeneous integration and chiplet-based architectures increase interconnect density and stricter reliability demands. This study introduces an artificial intelligence (AI)–finite element modeling (FEM) co-design framework for assessing solder fatigue failures, utilizing AI surrogate models for quick conceptual design exploration while preserving the accuracy of FEM validation. The research emphasizes developing training strategies that create AI surrogate models with strong generalization capabilities and investigates their use in conceptual design optimization using a database generated from an experimentally validated FEM.
To achieve robust model performance, the methodology integrates genetic algorithms for diverse weight initialization, kernel principal component analysis (K-PCA) for dimensionality reduction, and ensemble learning to balance computational efficiency and predictive robustness. Beyond conventional metrics, cosine similarity analysis and weight frequency decomposition are introduced as diagnostic tools for overparameterized deep neural networks (DNNs). Comparative analyses of adaptive moment estimation (ADAM) and stochastic gradient descent (SGD) show that both optimizers can achieve low validation errors, with SGD tending to yield smoother gradients and ADAM converging more rapidly. Experimental results indicate that well-constructed ensembles achieve validation errors below 1 % while maintaining consistent gradient-based optimization outcomes across different weight initializations. Monte Carlo simulations further confirm the greater robustness of SGD-trained models under parameter uncertainty, attributed to their preference for low-frequency, smooth solutions. The proposed framework ensures that AI surrogate models are both predictive and optimization-consistent, effectively bridging early-stage design exploration with high-fidelity reliability assessment in electronic packaging applications.
{"title":"AI surrogate modeling for PBGA solder joint fatigue risk assessment","authors":"Cadmus Yuan, Jian-Cheng Hong, Pin-Sian Li","doi":"10.1016/j.microrel.2025.115956","DOIUrl":"10.1016/j.microrel.2025.115956","url":null,"abstract":"<div><div>Solder joint reliability is a critical concern in advanced electronic packaging, especially as heterogeneous integration and chiplet-based architectures increase interconnect density and stricter reliability demands. This study introduces an artificial intelligence (AI)–finite element modeling (FEM) co-design framework for assessing solder fatigue failures, utilizing AI surrogate models for quick conceptual design exploration while preserving the accuracy of FEM validation. The research emphasizes developing training strategies that create AI surrogate models with strong generalization capabilities and investigates their use in conceptual design optimization using a database generated from an experimentally validated FEM.</div><div>To achieve robust model performance, the methodology integrates genetic algorithms for diverse weight initialization, kernel principal component analysis (K-PCA) for dimensionality reduction, and ensemble learning to balance computational efficiency and predictive robustness. Beyond conventional metrics, cosine similarity analysis and weight frequency decomposition are introduced as diagnostic tools for overparameterized deep neural networks (DNNs). Comparative analyses of adaptive moment estimation (ADAM) and stochastic gradient descent (SGD) show that both optimizers can achieve low validation errors, with SGD tending to yield smoother gradients and ADAM converging more rapidly. Experimental results indicate that well-constructed ensembles achieve validation errors below 1 % while maintaining consistent gradient-based optimization outcomes across different weight initializations. Monte Carlo simulations further confirm the greater robustness of SGD-trained models under parameter uncertainty, attributed to their preference for low-frequency, smooth solutions. The proposed framework ensures that AI surrogate models are both predictive and optimization-consistent, effectively bridging early-stage design exploration with high-fidelity reliability assessment in electronic packaging applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115956"},"PeriodicalIF":1.9,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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