As a high-speed memory, the static random-access memory (SRAM) has been widely used and well investigated. However, with the advanced manufactory technology develops and the critical dimension of transistor scales rapidly, SRAM has confronted with many challenges, such as the high-power consumption and the robustness issue, which impede the application of SRAM in advanced electronic devices. Here, by integrating two perpendicular anisotropy magnetic tunnel junctions (p-MTJs) to the conventional SRAM and reinforcing the CMOS circuits, a non-volatile and radiation hardened SRAM (NVRH-SRAM) design based on 14 transistors (14T) and 2 p-MTJs has been implemented. This MTJ-based NVRH-SRAM is primarily single event upset (SEU) tolerant and is a promising candidate for low power circuits, aerospace devices, and other high-speed memory applications.
{"title":"A non-volatile and radiation-hardened SRAM based on fourteen transistors and two perpendicular anisotropy magnetic tunnel junctions","authors":"Pei Yang, Kaixuan Li, Yunjiao Zhu, Xinpei Duan, Yanan Yin, Jiawei Chen, Tao Wang, Xinjie Zhou","doi":"10.1016/j.microrel.2025.115603","DOIUrl":"10.1016/j.microrel.2025.115603","url":null,"abstract":"<div><div>As a high-speed memory, the static random-access memory (SRAM) has been widely used and well investigated. However, with the advanced manufactory technology develops and the critical dimension of transistor scales rapidly, SRAM has confronted with many challenges, such as the high-power consumption and the robustness issue, which impede the application of SRAM in advanced electronic devices. Here, by integrating two perpendicular anisotropy magnetic tunnel junctions (p-MTJs) to the conventional SRAM and reinforcing the CMOS circuits, a non-volatile and radiation hardened SRAM (NVRH-SRAM) design based on 14 transistors (14T) and 2 p-MTJs has been implemented. This MTJ-based NVRH-SRAM is primarily single event upset (SEU) tolerant and is a promising candidate for low power circuits, aerospace devices, and other high-speed memory applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115603"},"PeriodicalIF":1.6,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-31DOI: 10.1016/j.microrel.2025.115611
Chao-Yang Ke, Ming-Dou Ker
ESD characterization of on-chip ESD protection devices, including the gate-grounded NMOS (GGNMOS), the gate-VDD PMOS (GDPMOS), the N+/PW diode, and the P+/NW diode was investigated. With respect to GGNMOS and GDPMOS, ESD robustness was unrelated to the number of fingers under the breakdown mode. On the contrary, under the forward mode, ESD robustness can be effectively enhanced by increasing the number of fingers. Similar results were observed on the N+/PW and the P+/NW diodes. Under the breakdown mode, ESD robustness was not related to the junction perimeter of the diode. Under the forward mode, ESD robustness can be effectively enhanced by increasing the junction perimeter. By comparing the figure of merit (FoM) among these four devices, the FoM of diode is higher than that of MOS-based ESD devices. Moreover, the concept of whole-chip ESD protection with power-rail ESD clamp circuit was recommended to guarantee the sufficient ESD robustness of SiC-based integrated circuits.
{"title":"Investigation of ESD protection devices for SiC-based monolithic integrated circuits","authors":"Chao-Yang Ke, Ming-Dou Ker","doi":"10.1016/j.microrel.2025.115611","DOIUrl":"10.1016/j.microrel.2025.115611","url":null,"abstract":"<div><div>ESD characterization of on-chip ESD protection devices, including the gate-grounded NMOS (GGNMOS), the gate-VDD PMOS (GDPMOS), the N+/PW diode, and the P+/NW diode was investigated. With respect to GGNMOS and GDPMOS, ESD robustness was unrelated to the number of fingers under the breakdown mode. On the contrary, under the forward mode, ESD robustness can be effectively enhanced by increasing the number of fingers. Similar results were observed on the N+/PW and the P+/NW diodes. Under the breakdown mode, ESD robustness was not related to the junction perimeter of the diode. Under the forward mode, ESD robustness can be effectively enhanced by increasing the junction perimeter. By comparing the figure of merit (FoM) among these four devices, the FoM of diode is higher than that of MOS-based ESD devices. Moreover, the concept of whole-chip ESD protection with power-rail ESD clamp circuit was recommended to guarantee the sufficient ESD robustness of SiC-based integrated circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115611"},"PeriodicalIF":1.6,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-29DOI: 10.1016/j.microrel.2025.115608
Nie Lei , Zhang Ming , Yu Chenrui , Yan Han , Liao Guanglan , Liu Mengran
In the realm of microelectronic packaging, 3D packaging employing Through-Silicon Vias (TSVs) is prevalent in high-end electronic devices due to its enhanced integration density and reduced power consumption. Nevertheless, the intricate fabrication processes of TSVs frequently engender internal defects, critically impairing the reliability and performance stability of the packaging. Conventional inspection methodologies are generally ineffectual in detecting subsurface defects. To address this, we propose an inspection method for internal defects in 3D TSV packaging utilizing infrared time-sequence imaging. This method involves dynamic laser excitation to induce defect-specific thermal anomalies, which are subsequently captured via infrared time-sequence imagery. These images are processed using a deep learning C3D network to facilitate defect recognition and classification. An experimental setup was developed with an infrared laser mounted on a 2D translation stage to dynamically excite the test samples while an infrared thermograph records the time-sequenced thermal images. The experimental results validate the efficacy of this approach, achieving detection accuracies of 98.1 % for identical defect types at the same location and 97.8 % for various defect locations.
{"title":"The research on the infrared time-sequence imaging inspection method for internal defects of 3D TSV packaging","authors":"Nie Lei , Zhang Ming , Yu Chenrui , Yan Han , Liao Guanglan , Liu Mengran","doi":"10.1016/j.microrel.2025.115608","DOIUrl":"10.1016/j.microrel.2025.115608","url":null,"abstract":"<div><div>In the realm of microelectronic packaging, 3D packaging employing Through-Silicon Vias (TSVs) is prevalent in high-end electronic devices due to its enhanced integration density and reduced power consumption. Nevertheless, the intricate fabrication processes of TSVs frequently engender internal defects, critically impairing the reliability and performance stability of the packaging. Conventional inspection methodologies are generally ineffectual in detecting subsurface defects. To address this, we propose an inspection method for internal defects in 3D TSV packaging utilizing infrared time-sequence imaging. This method involves dynamic laser excitation to induce defect-specific thermal anomalies, which are subsequently captured via infrared time-sequence imagery. These images are processed using a deep learning C3D network to facilitate defect recognition and classification. An experimental setup was developed with an infrared laser mounted on a 2D translation stage to dynamically excite the test samples while an infrared thermograph records the time-sequenced thermal images. The experimental results validate the efficacy of this approach, achieving detection accuracies of 98.1 % for identical defect types at the same location and 97.8 % for various defect locations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115608"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-29DOI: 10.1016/j.microrel.2025.115609
Mohammed Abdel Razzaq , Michael Meilunas , Xian A. Cao , Jim Wilcox , Abdallah Ramini
This study investigates how the solder solidification temperature affects residual stress distribution and failure locations in BGA solder joints, aiming to provide insights that enhance solder alloy selection and reflow process optimization. Through experimental thermal cycling tests on BGA208 assemblies using SAC305 (∼220 °C) and Sn37Pb (∼180 °C) solder alloys, subjected to temperatures ranging from −40 °C to 125 °C, we found that SAC305 assemblies predominantly failed at corner joints due to warpage stresses. In contrast, Sn37Pb assemblies failed at second-row joints under the die edge due to shear stresses. These results were validated by Finite element analysis (FEA) simulations, which showed that higher solidification temperatures, as in SAC305, resulted in higher residual stresses and maximum stresses at corner joints, whereas lower solidification temperatures, as in Sn37Pb, shifted stress concentrations to non-corner joints. These results underscore the critical role of the solidification temperature in determining failure locations and provide valuable insights for improving the reliability of BGA components in electronic applications.
{"title":"Effects of solder solidification temperature on residual stress distribution and failure location in BGA solder joints","authors":"Mohammed Abdel Razzaq , Michael Meilunas , Xian A. Cao , Jim Wilcox , Abdallah Ramini","doi":"10.1016/j.microrel.2025.115609","DOIUrl":"10.1016/j.microrel.2025.115609","url":null,"abstract":"<div><div>This study investigates how the solder solidification temperature affects residual stress distribution and failure locations in BGA solder joints, aiming to provide insights that enhance solder alloy selection and reflow process optimization. Through experimental thermal cycling tests on BGA208 assemblies using SAC305 (∼220 °C) and Sn37Pb (∼180 °C) solder alloys, subjected to temperatures ranging from −40 °C to 125 °C, we found that SAC305 assemblies predominantly failed at corner joints due to warpage stresses. In contrast, Sn37Pb assemblies failed at second-row joints under the die edge due to shear stresses. These results were validated by Finite element analysis (FEA) simulations, which showed that higher solidification temperatures, as in SAC305, resulted in higher residual stresses and maximum stresses at corner joints, whereas lower solidification temperatures, as in Sn37Pb, shifted stress concentrations to non-corner joints. These results underscore the critical role of the solidification temperature in determining failure locations and provide valuable insights for improving the reliability of BGA components in electronic applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115609"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-29DOI: 10.1016/j.microrel.2025.115604
Ling Xiong, Wangyong Chen, Mingyue Zheng, Linlin Cai
The ongoing drive to shrink transistor sizes has yielded substantial benefits but has also amplified reliability concerns, especially concerning aging effects. Moreover, the wide range of applications demands distinct reliability standards, with temperature playing a pivotal role. To tackle these challenges, this paper presents three approaches based on critical gate sorting: buffer insertion, gate sizing, and a hybrid technique that combines both. Simulations using the ASAP 7 nm standard cell library reveal that these methods significantly improve circuit robustness against aging and temperature fluctuations. Among these methods, buffer insertion achieves performance optimization at the expense of significant area overhead, while gate sizing provides a more balanced trade-off between performance and resource usage. Compared to gate sizing, the hybrid technique proves to be the most effective solution in scenarios with stringent power consumption requirements.
{"title":"Gate sizing and buffer insertion for circuit aging and thermal resilience enhancement","authors":"Ling Xiong, Wangyong Chen, Mingyue Zheng, Linlin Cai","doi":"10.1016/j.microrel.2025.115604","DOIUrl":"10.1016/j.microrel.2025.115604","url":null,"abstract":"<div><div>The ongoing drive to shrink transistor sizes has yielded substantial benefits but has also amplified reliability concerns, especially concerning aging effects. Moreover, the wide range of applications demands distinct reliability standards, with temperature playing a pivotal role. To tackle these challenges, this paper presents three approaches based on critical gate sorting: buffer insertion, gate sizing, and a hybrid technique that combines both. Simulations using the ASAP 7 nm standard cell library reveal that these methods significantly improve circuit robustness against aging and temperature fluctuations. Among these methods, buffer insertion achieves performance optimization at the expense of significant area overhead, while gate sizing provides a more balanced trade-off between performance and resource usage. Compared to gate sizing, the hybrid technique proves to be the most effective solution in scenarios with stringent power consumption requirements.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115604"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As a kind of widely employed power semiconductor devices, insulated gate bipolar transistor (IGBT) modules are often confronted with strong load current from tens to hundreds of amperes. Thus, the electrical-magnetic-mechanical coupling characteristics in IGBT modules deserve priority attention for reliability evaluation. Herein, an in-depth investigation of electromagnetic force effect in IGBT modules is implemented from both theoretical and experimental approaches. Utilizing uniquely designed excitation strategy of single frequency sinusoidal alternating load current superimposed by direct current bias, the exclusive frequency-doubled vibration signal induced by electromagnetic force effect is successfully observed on the IGBT bare die with the aid of laser interferometric vibrometer, providing direct and confident evidence for the existence of electromagnetic force effect in IGBT modules. This work is bound to bring new insights to fundamental exploration of electrical-mechanical coupling induced reliability issues in power electronic devices.
{"title":"Investigation of electromagnetic force effect in IGBT modules","authors":"Jiahao Wang, Cong Chen, Libing Bai, Yuxin Luo, Chaoyue Song, Yuhua Cheng","doi":"10.1016/j.microrel.2025.115606","DOIUrl":"10.1016/j.microrel.2025.115606","url":null,"abstract":"<div><div>As a kind of widely employed power semiconductor devices, insulated gate bipolar transistor (IGBT) modules are often confronted with strong load current from tens to hundreds of amperes. Thus, the electrical-magnetic-mechanical coupling characteristics in IGBT modules deserve priority attention for reliability evaluation. Herein, an in-depth investigation of electromagnetic force effect in IGBT modules is implemented from both theoretical and experimental approaches. Utilizing uniquely designed excitation strategy of single frequency sinusoidal alternating load current superimposed by direct current bias, the exclusive frequency-doubled vibration signal induced by electromagnetic force effect is successfully observed on the IGBT bare die with the aid of laser interferometric vibrometer, providing direct and confident evidence for the existence of electromagnetic force effect in IGBT modules. This work is bound to bring new insights to fundamental exploration of electrical-mechanical coupling induced reliability issues in power electronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115606"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1016/j.microrel.2025.115595
Jingguang Yao , Hongliang Zhou , Jun Cao , Jicun Lu , Xiaoning Xu , Pingmei Ming , Ziming Wang , John Persic
The intermetallic compound layer at the Cu/Al bonding interface is undergoing a dynamic evolution stage with the consumption of the Al pad during the continuous annealing process. This paper establishes a microstructure model of the Cu/Al bonding interface and analyses the crack extension behavior of the bonding interface through finite element simulation under three key aging states: initial bonding, moderately annealed and highly aged. The findings indicated that alterations in the annealed state would result in a modification of the damage mode of the bonding interface, leading to a deviation in the crack path. In the initial stages of the bonding process, crack initiation occurs at the edge of the Al pad and extends inward, resulting in fracture. The occurrence of cracks depends on the extent of annealing, with softer Al pad or Al-rich IMCs, such as CuAl2 layer, exhibiting these defects under moderately annealed conditions. Subsequently, the cracks gradually extend towards the harder and more brittle Cu9Al4 to fracture. In highly aged conditions, cracks initially emerge in the Al-rich CuAl2 layer and subsequently deflect into the CuAl layer. Finally, they deflect once more into the Cu9Al4 layer, eventually leading to fracture. In addition, cracks are affected by the grain orientation of IMCs and form at interfaces that are approximately perpendicular to the loading direction. The simulation results corroborate the fracture modes of the bonding interface in different aging processes from the micro grain perspective, which provides a technical reference for the study of the fracture mechanism of Cu/Al bonding.
{"title":"Simulation of intergranular crack extension at Cu/Al wire bonding interface","authors":"Jingguang Yao , Hongliang Zhou , Jun Cao , Jicun Lu , Xiaoning Xu , Pingmei Ming , Ziming Wang , John Persic","doi":"10.1016/j.microrel.2025.115595","DOIUrl":"10.1016/j.microrel.2025.115595","url":null,"abstract":"<div><div>The intermetallic compound layer at the Cu/Al bonding interface is undergoing a dynamic evolution stage with the consumption of the Al pad during the continuous annealing process. This paper establishes a microstructure model of the Cu/Al bonding interface and analyses the crack extension behavior of the bonding interface through finite element simulation under three key aging states: initial bonding, moderately annealed and highly aged. The findings indicated that alterations in the annealed state would result in a modification of the damage mode of the bonding interface, leading to a deviation in the crack path. In the initial stages of the bonding process, crack initiation occurs at the edge of the Al pad and extends inward, resulting in fracture. The occurrence of cracks depends on the extent of annealing, with softer Al pad or Al-rich IMCs, such as CuAl<sub>2</sub> layer, exhibiting these defects under moderately annealed conditions. Subsequently, the cracks gradually extend towards the harder and more brittle Cu<sub>9</sub>Al<sub>4</sub> to fracture. In highly aged conditions, cracks initially emerge in the Al-rich CuAl<sub>2</sub> layer and subsequently deflect into the CuAl layer. Finally, they deflect once more into the Cu<sub>9</sub>Al<sub>4</sub> layer, eventually leading to fracture. In addition, cracks are affected by the grain orientation of IMCs and form at interfaces that are approximately perpendicular to the loading direction. The simulation results corroborate the fracture modes of the bonding interface in different aging processes from the micro grain perspective, which provides a technical reference for the study of the fracture mechanism of Cu/Al bonding.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115595"},"PeriodicalIF":1.6,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115568
Qian Zhang , Shufan Li , Lie Cai , Dong Sun
GaN-based optoelectronic devices exhibit exceptional performance. However, the photo-induced electrochemical migration (PECM) effect poses risks to their long-term reliability, especially under light and humidity exposure. This paper explores the underlying causes of PECM, identifying environmental light, moisture, and the presence of metallic elements as key factors. This study reveals that the PECM-related surface insulation resistance (SIR) failure is driven by the formation of dendritic structures between the anode and cathode, with faster SIR failure observed as electrode spacing decreases. An in-depth description of the electrochemical migration process is provided.
{"title":"Failure analysis of GaN-based optoelectronic devices: Insights into photo-induced electrochemical migration","authors":"Qian Zhang , Shufan Li , Lie Cai , Dong Sun","doi":"10.1016/j.microrel.2024.115568","DOIUrl":"10.1016/j.microrel.2024.115568","url":null,"abstract":"<div><div>GaN-based optoelectronic devices exhibit exceptional performance. However, the photo-induced electrochemical migration (PECM) effect poses risks to their long-term reliability, especially under light and humidity exposure. This paper explores the underlying causes of PECM, identifying environmental light, moisture, and the presence of metallic elements as key factors. This study reveals that the PECM-related surface insulation resistance (SIR) failure is driven by the formation of dendritic structures between the anode and cathode, with faster SIR failure observed as electrode spacing decreases. An in-depth description of the electrochemical migration process is provided.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115568"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micro-Electromechanical-Relay (MER) is one of the most important electric components in electrical equipment. However, cold adhesion failure between electrical contacts in MER usually increases the risk for operating failure of closed contacts. In this letter, Au-Ni composite coatings with different Ni content are deposited on the surface of electrical contact by magnetron sputtering, to investigate the effect of coating quality on the cold adhesion. The relationship between push force and cold adhesion force is built employing mechanical contact theory to evaluate the cold adhesion. The results indicate that the cold adhesion force between electrical contacts remarkably decreases from 13.8 mN to 2.3 mN when the coating hardness gradually increases from 1.6 GPa to 3.8 GPa. The cold adhesion reveals a similar trend even at extreme environmental conditions (high/low temperature cycling in the range of 180 °C–65 °C). This finding provides an innovation strategy for solving the cold adhesion problem.
{"title":"Evolution mechanism of cold adhesion force between electrical contact determined by coating hardness","authors":"Ming-xu Zhang, Xue Zhou, Chun Cao, Xu Wang, Yong Zhang, Dao-Yi Wu, Guo-fu Zhai","doi":"10.1016/j.microrel.2024.115570","DOIUrl":"10.1016/j.microrel.2024.115570","url":null,"abstract":"<div><div>Micro-Electromechanical-Relay (MER) is one of the most important electric components in electrical equipment. However, cold adhesion failure between electrical contacts in MER usually increases the risk for operating failure of closed contacts. In this letter, Au-Ni composite coatings with different Ni content are deposited on the surface of electrical contact by magnetron sputtering, to investigate the effect of coating quality on the cold adhesion. The relationship between push force and cold adhesion force is built employing mechanical contact theory to evaluate the cold adhesion. The results indicate that the cold adhesion force between electrical contacts remarkably decreases from 13.8 mN to 2.3 mN when the coating hardness gradually increases from 1.6 GPa to 3.8 GPa. The cold adhesion reveals a similar trend even at extreme environmental conditions (high/low temperature cycling in the range of 180 °C–65 °C). This finding provides an innovation strategy for solving the cold adhesion problem.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115570"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115565
Zoubir Khatir, Ali Ibrahim, Richard Lallemand
The accurate online estimation of power electronic module health is critical for predictive maintenance, particularly in predicting the remaining useful life of systems under field operating conditions. Conventional aging indicators often require complex, costly procedures involving junction temperature estimation, which limits their suitability for on-line monitoring. This study introduces a novel electrical aging indicator tailored for bond-wire contact degradation, offering ease of online implementation and temperature independence. The indicator is based on experimental and theoretical insights into the behavior of the zero-temperature coefficient (ZTC) in the I-V characteristics of IGBTs affected by top-metal interconnect degradation. The results show that the degradation of the bond-wire contacts has an effect on the ZCT point with a strong impact on the current and very little on the voltage. Leveraging this result enables the development of an online monitoring approach, the methodology of which is demonstrated through power cycling tests. Both traditional and new aging indicators show strong correlations with aging. In addition, the proposed new indicator has a better sensitivity to the degradation.
{"title":"New temperature-independent aging indicator for power semiconductor devices – Application to IGBTs","authors":"Zoubir Khatir, Ali Ibrahim, Richard Lallemand","doi":"10.1016/j.microrel.2024.115565","DOIUrl":"10.1016/j.microrel.2024.115565","url":null,"abstract":"<div><div>The accurate online estimation of power electronic module health is critical for predictive maintenance, particularly in predicting the remaining useful life of systems under field operating conditions. Conventional aging indicators often require complex, costly procedures involving junction temperature estimation, which limits their suitability for on-line monitoring. This study introduces a novel electrical aging indicator tailored for bond-wire contact degradation, offering ease of online implementation and temperature independence. The indicator is based on experimental and theoretical insights into the behavior of the zero-temperature coefficient (ZTC) in the I-V characteristics of IGBTs affected by top-metal interconnect degradation. The results show that the degradation of the bond-wire contacts has an effect on the ZCT point with a strong impact on the current and very little on the voltage. Leveraging this result enables the development of an online monitoring approach, the methodology of which is demonstrated through power cycling tests. Both traditional and new aging indicators show strong correlations with aging. In addition, the proposed new indicator has a better sensitivity to the degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115565"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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