Microelectronics Reliability最新文献

{"title":"Machine learning classifiers with explainable insights for parametric fault diagnosis in linear analog circuits using frequency response features","authors":"Vanshika Rajpal ,&nbsp;A. Charan Kumari ,&nbsp;K. Srinivas","doi":"10.1016/j.microrel.2025.115982","DOIUrl":"10.1016/j.microrel.2025.115982","url":null,"abstract":"<div><div>Accurate and scalable fault diagnosis in analog integrated circuits (AICs) remains a significant challenge, particularly in detecting soft parametric faults arising from process variations, aging, and environmental factors. This paper presents a comprehensive machine learning–based framework for automated fault classification in linear analog circuits, demonstrated through two representative case studies, an RC band-pass filter and a Butterworth low-pass filter. Frequency-domain responses of both output voltage and supply current were analysed, and complex-valued features comprising real and imaginary components were extracted to capture the circuits' resistive and reactive characteristics.</div><div>Monte Carlo simulations with ±30 % component deviations generated a rich dataset for training and validation. Nine machine learning classifiers, including CatBoost, LightGBM, and XGBoost, were benchmarked against traditional approaches. The proposed complex-domain feature extraction method significantly outperformed magnitude-only and real-part-only baselines, with CatBoost achieving the highest accuracy of 99.75 %. Computational efficiency and inference analysis confirmed the model's suitability for real-time fault diagnosis, with millisecond-level latency and compact model size. SHAP (SHapley Additive exPlanations) analysis provided interpretability by identifying the most influential spectral features contributing to fault classification.</div><div>Finally, the framework's generalisation and practical feasibility were demonstrated through cross-circuit evaluation and a hardware validation perspective, outlining measurement procedures and highlighting its real-world applicability. The results confirm that the proposed approach effectively integrates high diagnostic accuracy, interpretability, and computational efficiency, establishing a robust and explainable solution for fault diagnosis in linear analog circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115982"},"PeriodicalIF":1.9,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power cycling-induced degradation mechanisms in SiC MOSFETs with embedded Schottky barrier diodes","authors":"Gyuhyeok Kang ,&nbsp;Ogyun Seok","doi":"10.1016/j.microrel.2025.115978","DOIUrl":"10.1016/j.microrel.2025.115978","url":null,"abstract":"<div><div>The long-term reliability of 1.2 kV 4H-SiC MOSFETs monolithically integrated with Schottky barrier diodes (SBDs) was systematically investigated under repetitive thermo-electrical stress using DC power cycling. While SBD integration suppresses reverse-recovery charge and enhances high-frequency switching performance, the additional metal–semiconductor junctions in the body diode region introduce potential failure sites susceptible to thermally activated degradation mechanisms. In this work, devices with and without embedded SBDs were subjected to controlled junction temperature swings (ΔT_j = 110 °C, T_j,m = 120 °C) for multiple cycling intervals. Temperature-sensitive electrical parameter (TSEP) monitoring, based on the low-current source–drain voltage (V_SD), was performed in-situ during every power cycling event, enabling continuous tracking of junction temperature variation associated with SBD forward voltage shift. A comprehensive parametric analysis including on state resistance (R_on), threshold voltage (V_th), breakdown voltage (BV), forward conduction characteristics (V_F), and reverse leakage characteristics was conducted to identify the dominant degradation mechanisms in SiC MOSFETs with embedded SBDs under power cycling conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115978"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluating switch lifetime in soft-switched single-stage differential-mode SST","authors":"Nanditha Gajanur ,&nbsp;Mohammad A. Abbaszada ,&nbsp;Shantanu Gupta ,&nbsp;Sudip K. Mazumder","doi":"10.1016/j.microrel.2025.115975","DOIUrl":"10.1016/j.microrel.2025.115975","url":null,"abstract":"<div><div>The reliability of semiconductor switches in single-stage differential-mode solid-state transformers (DM-SSTs) has not been systematically evaluated under soft-switching operation and realistic grid conditions. This paper presents a switch-level reliability analysis for soft-switched and hard-switched DM-SST configurations by integrating converter-specific power loss modeling with empirical lifetime prediction. Analytical derivation of device current profiles specific to the DM-SST is used to characterize electrothermal stress, which is then mapped to lifetime using degradation models obtained from power cycling tests (PCTs). Applied to realistic SST load profiles and grid voltage variations, this approach provides a probabilistic prediction of switch lifetime for the DM-SST. Lifetime estimates for both SiC MOSFETs and Si IGBTs are presented, offering insight into device degradation under converter operating conditions. The results quantify the reliability benefits of soft switching in single-stage SSTs, highlighting how switching dynamics influence long-term switch degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115975"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-physics coupling simulation and numerical computation of die shift in fan-out wafer-level packaging","authors":"Yan Ma ,&nbsp;Majiaqi Wu ,&nbsp;Lianqiao Yang","doi":"10.1016/j.microrel.2025.115981","DOIUrl":"10.1016/j.microrel.2025.115981","url":null,"abstract":"<div><div>Fan-out wafer-level packaging (FO-WLP), as a breakthrough advanced packaging technology, achieves high density interconnections by embedding chips into epoxy mold compound (EMC) and forming redistribution layers outside the die area. However, die shift, which is a slight displacement of the die from its intended position, poses a significant challenge during the molding process, affecting alignment and yield. This study systematically analyzes the effects of warpage, thermal expansion/contraction, EMC curing shrinkage and fluid drag force on die shift through multi-physics coupling simulations and numerical computation. It quantifies the contributions of thermal and fluid effects to die shift under different EMC viscosities and thicknesses. The results indicate that thermal effects are the dominant factor causing die shift; fluid effects become significant only under high-viscosity conditions, with a maximum contribution of approximately 30 %. As EMC thickness increases, the peak total shift moves toward the wafer edge, while high viscosity shifts it closer to the center. Thinner EMC exacerbates warpage but reduces die shift, whereas thicker EMC has the opposite effect. This study provides critical insights for optimizing process parameters, controlling die shift, and enhancing packaging reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115981"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"HfO₂ barrier layers: Thickness-dependent corrosion protection of copper thin films for potential microelectronic applications with sweat contact","authors":"Osman KAHVECİ ,&nbsp;Muh RUSDI ,&nbsp;Abdullah AKKAYA ,&nbsp;Enise AYYILDIZ","doi":"10.1016/j.microrel.2025.115985","DOIUrl":"10.1016/j.microrel.2025.115985","url":null,"abstract":"<div><div>Copper conductive thin films or components in microelectronic devices face significant corrosion challenges that compromise long-term reliability. This study presents a comprehensive investigation of hafnium dioxide (HfO₂) as a protective barrier layer deposited by RF magnetron sputtering at varying thicknesses (150 and 300 nm) on copper substrates for possible microelectronic applications. Multi-technique characterization methods, including SEM-EDX, AFM, XRD, FTIR, UV–Vis spectroscopy, contact angle measurements, potentiodynamic polarization, and electrochemical impedance spectroscopy (EIS), were employed to establish structure, property, and performance relationships. EDX results show that the addition of an HfO₂ layer significantly modified the surface morphology, especially on presence of 300 nm HfO₂ layer, so that the surface appears continuous and uniform. This is also supported by the FTIR analysis results, which indicate the presence of the strongest Hf<img>O and Hf-O-Hf vibrational bonds, thereby confirming the formation of an HfO₂ layer on the Cu surface. AFM results show an increase in surface topography roughness, caused by island-type growth (Volmer-Weber), as the thickness of the HfO₂ layer increases. The XRD results for un-coated sample shows sharp and clear diffraction peaks and indicates face-centered cubic (FCC) phase pattern of pure Cu nanoparticles. When the HfO₂ layer added Cu layer, XRD pattern shows the formation of a broad hump in the range of 2θ ≈ 28°–35° and HfO₂ layer formed is in the amorphous state. These results are correlated with the contact angle test results. UV–Vis results show that 300 nm HfO₂ coted films has the highest transmittance value across the entire wavelength range, as well as the lowest absorbance value. The 300 nm HfO₂ coating demonstrated optimal corrosion protection with 21.2 % reduction in corrosion current density (from 11.3 to 8.89 μA/cm²) and 29 % increase in polarization resistance (from 1.45 to 1.87 kΩ cm²) in artificial sweat environment. Finally, surface wettability studies revealed that increased hydrophobicity (contact angle:49.13° to 57.99°) was correlated with enhanced corrosion barrier performance. These findings establish RF-sputtered HfO₂ as a viable, scalable solution for copper protection in next-generation microelectronic and wearable biosensor applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115985"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning","authors":"Mohammad Rafiee ,&nbsp;Farough Agin ,&nbsp;Kuldeep Kumar ,&nbsp;Ezhilan Murali","doi":"10.1016/j.microrel.2025.115983","DOIUrl":"10.1016/j.microrel.2025.115983","url":null,"abstract":"<div><div>Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, machine-learning-assisted co-design framework that links high-fidelity finite-element analysis (FEA) with surrogate modeling, multi-objective optimization, and decision analysis. A 3D FEA model generates 500 Latin Hypercube design points for type of analysis (thermal and reliability), spanning geometry, materials, and thermal-path variables. Four minimized objectives are considered: junction-to-ambient thermal resistance (<span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>) and cycle-averaged plastic strain-energy density at the corner flip-chip cu-pillar bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub></math></span>), C4 bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>), and BGA (<span><math><mi>Δ</mi><msub><mi>W</mi><mi>BGA</mi></msub></math></span>). Tree-based regressors (Random Forest, XGBoost) achieve high test-set fidelity and drive NSGA-II to enumerate the Pareto domain. A Net Flow multi-criteria decision method (MCDM) ranks Pareto candidates to identify a champion design with balanced thermo-mechanical performance. <em>Re</em>-simulation of the champion in FEA confirms surrogate accuracy for dominant responses (≈4–5 % deviation for <span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub><mspace></mspace></math></span>and <span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>) and exact agreement for <span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>, while revealing weak coupling between thermal and mechanical objectives—enabling partial decoupling of heat-path optimization from interconnect reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115983"},"PeriodicalIF":1.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative study of extrapolation methods for solder joint lifetime estimation using crack length data","authors":"Dorottya Varga ,&nbsp;Zsombor Olajos ,&nbsp;Gabor Belina","doi":"10.1016/j.microrel.2025.115976","DOIUrl":"10.1016/j.microrel.2025.115976","url":null,"abstract":"<div><div>Estimating solder joint lifetime often involves extrapolating crack length measurements from cross-sectional images to a defined end-of-life (EoL) criterion. The original pearl string method fits a single regression line to all data points, which can result in unrealistic predictions, such as negative slopes or failure times. To address these issues, an alternative pearl string method was proposed, incorporating a fixed crack-free time (CFT) ratio to better reflect actual damage evolution. This study compares the two methods in terms of robustness, accuracy, and statistical consistency. The alternative method fits individual crack propagation curves for each specimen, enabling lifetime estimation in destructive testing with limited measurement points. Outlier sensitivity analysis showed that the original method is highly affected by anomalous data, while the alternative method exhibited minimal change. Goodness-of-fit evaluation using the Kolmogorov–Smirnov test confirmed that the alternative method aligns more closely with the validation data (<em>p</em> = 0.09 and 0.22), unlike the original method (<em>p</em> = 3.66 × 10⁻⁶ and 1.20 × 10⁻⁸). In conclusion, the alternative pearl string method offers a more robust and physically meaningful approach for lifetime extrapolation, especially in contexts with limited or noisy data.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115976"},"PeriodicalIF":1.9,"publicationDate":"2025-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Uncertainty quantification in microelectronic packaging using feedback-enhanced adaptive polynomial chaos expansion","authors":"Guozhuang Fan ,&nbsp;Jinzhu Zhou ,&nbsp;Qiangqiang Lin ,&nbsp;Jiancheng Shi","doi":"10.1016/j.microrel.2025.115973","DOIUrl":"10.1016/j.microrel.2025.115973","url":null,"abstract":"<div><div>This paper presents a feedback-enhanced adaptive polynomial chaos modeling framework for robust performance prediction of microelectronic packages incorporating wire bonding, with the aim of addressing process-induced variability in advanced packaging environments. To tackle persistent reliability challenges in microelectronic assembly—particularly those associated with gold wire bonding—the proposed approach integrates adaptive kernel density estimation with residual-driven basis refinement to dynamically model non-Gaussian process fluctuations observed across manufacturing batches. By incorporating an online feedback loop, the model autonomously adjusts to process drift and parameter shifts, enabling real-time response to deviations in the packaging workflow. Validation on a 16-channel microelectronic module demonstrates that the proposed approach maintains high prediction accuracy across varying production conditions, with over 98 % of measured samples falling within the predicted confidence bounds. The method effectively models packaging-induced performance variability and serves as a data-driven tool for manufacturing-oriented uncertainty quantification and predictive control in high-frequency module production.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115973"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of interface traps properties induced by NBTI effects at different interfaces of VDMOS","authors":"Yanyong Wang ,&nbsp;Liang He ,&nbsp;Yanfang Li ,&nbsp;Zhenni Wang ,&nbsp;Zhongyang Li ,&nbsp;Hao Zhou ,&nbsp;Kaihe Liu ,&nbsp;Maolin Zhang","doi":"10.1016/j.microrel.2025.115977","DOIUrl":"10.1016/j.microrel.2025.115977","url":null,"abstract":"<div><div>This paper investigates the negative bias temperature instability (NBTI) of P-channel vertical double-diffused MOSFETs (VDMOS). The threshold voltage (<em>V</em>_<em>TH</em>) shift in VDMOS due to NBTI is primarily caused by the generation of oxide charge and interface traps in the gate oxide layer. The interface traps at the VDMOS drain interface and channel were investigated using the Direct-Current Current-Voltage (DCIV) technique and the conductance method, respectively. The results indicate that NBTI stress induces a higher density of interface traps in the channel region. Through TCAD simulation, it was discovered that the electric field intensity in the channel region exceeds that at the drain interface under negative bias. This larger electric field intensity causes increased dissociation of interface hanging bonds, ultimately leading to a greater number of interface traps in the channel region.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115977"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of thermal contact resistance, incident depth, incident angle, drain voltage and ambient temperature on single event transient during self-heating","authors":"Yan Liu ,&nbsp;Yanhua Ma ,&nbsp;Chong Pan","doi":"10.1016/j.microrel.2025.115979","DOIUrl":"10.1016/j.microrel.2025.115979","url":null,"abstract":"<div><div>In this work, the impacts of thermal contact resistance (SR), incident depth, incident angle, drain voltage and ambient temperature on the nanosheet characteristics under single event transient during self-heating are investigated using 3D computer-aided design. The results show that the self-heating reduces the maximum transient current under single event transient by 12.65 %. This attributes to the fact that the self-heating increases lattice temperature, thereby reducing the mobility and linear energy transfer. Moreover, the maximum transient current decreases by 9.69 % with an increase of SR. Besides, the increasing incident depth arises the maximum transient current by 9.80 %. Meanwhile, an increase in incident angle decreases the maximum transient current by 0.44 %. Furthermore, as the drain voltage increases, the maximum transient current rises by 16.09 %. Additionally, the increasing ambient temperature reduces the maximum transient current by 10.72 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115979"},"PeriodicalIF":1.9,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}