Microelectronics Reliability最新文献

The evolution of electronic packaging technology towards the adoption of glass substrates marks a significant advancement in overcoming the constraints posed by traditional organic materials. This review delves into the thermo-mechanical reliability concerns associated with glass substrates, glass interposers, and Through Glass Vias (TGV), highlighting the inherent fragility of glass and its susceptibility to cracking as key challenges in their widespread application. The unique tunable modulus and closely matched coefficient of thermal expansion (CTE) to silicon, offer promising solutions to stress-related failures, particularly in large-format applications. Despite these advantages, the integration of glass substrates faces obstacles such as stress management, fragility, adhesion issues, and the uniformity of via fills, compounded by the limited availability of long-term reliability data. This paper provides a comprehensive overview of the fabrication processes for glass substrates and TGVs, the impact of design parameters such as via density and aspect ratio on glass substrate reliability, and the mitigation strategies for stress and crack of TGV. Through the examination of Finite Element Analysis (FEA) models and experimental data, we explore the delicate balance between the stress induced by Redistribution Layers (RDL) and the fracture strength of glass, influenced by various design factors. The review also considers the potential of glass substrates in high-density interconnects and advanced packaging architectures, positioning glass as a transformative material in the future of electronic packaging.

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Interface traps play a significant role in shaping the performance and reliability of semiconductor devices, particularly in advanced technologies such as Negative Capacitance based FinFET and Nanosheet (NS) FET. Hence, for the first time, using well calibrated TCAD models, we benchmark and explore into the analysis of interface traps in NC-FinFET and NC-NSFET devices at the sub-3 nm technology node, focusing on their effects on digital, analog/RF performance parameters. The investigation is mainly focussed on: (a) Positioning of acceptor (E_V + 1 - E_V-0.4) and donor (E_C + 0.2 - E_C-1.5) trap locations in the energy band (b) variation in acceptor and donor interface trap concentration (c) design of Common Source (CS) amplifier for analog integrated circuits. In addition, we explored a design space to achieve optimal capacitance matching, targeting the NC effect for an optimized device design. Our findings showed a significant improvement in I_ON/I_OFF ratio by ~9× for NC-NSFET when compared to NC-FinFET with change in acceptor trap locations. The NC-FinFETs demonstrated a resilient intrinsic gain (A_V) profile, making them suitable for high-speed amplifiers. Varying donor trap locations had minimal impact on NC-NSFET but slightly affected NC-FinFET's intrinsic gain profile. Moreover, increasing acceptor trap concentration improved digital performance, with NC-NSFET outperforming NC-FinFET and the analog/RF performance favored lower trap concentrations. In addition, NC-FinFETs were more resilient to increased donor traps concentration than NC-NSFETs. Further, the CS amplifier-based NC acceptor devices offered effective amplification and power-saving features, making them ideal for IoT and biomedical applications reliant on battery voltages.

HgCdTe based infrared focal plane array (IRFPA) continues to be the best performing sensor for imaging infrared seeker systems. A detailed study on the flip chip bonding is described for an improvement in the performance and reliability of FPA under stringent thermal and mechanical cycling load. HgCdTe material has a limitation in the bonding temperature and pressure to preserve the detector performance. Process of thermo-compression bonding is developed here for a large format HgCdTe detector array with ultra-fine pitch. Flip-chip bonding under ultra-low force of 4.6 × 10⁻⁴ N/bump is achieved with minimum residual stress and it protects the HgCdTe photo-diodes from dislocation circuit multiplication after hybridization. This thermo-compression process is directly usable for other materials such as InSb, T2SL and InGaAs etc. with due consideration of the material's properties like Young's modulus, coefficient of thermal expansion, Poisson ratio and mechanical strength. HgCdTe FPAs with the optimum bonding parameters are packed in detector-dewar-cooler-assembly (DDCA) and tested for stringent thermal shock, mechanical shock and random vibration process. The fatigue life of 10⁴ thermal cycles is achieved to make suitable for fail safe operation. HgCdTe FPA will have a life span of 13 years (if it is cooled down twice on each day) which is more than the vacuum integrity shelf life of a sealed DDCA.

In this study, the weak bias temperature instability (BTI) in both Si p- and n-MOSFETs was systematically investigated using subthreshold swing degradation (ΔS factor), threshold voltage shift (ΔV_th) and flicker noise (1/f noise) characteristics. It is found that the 1/f noise characteristics exhibit more pronounced deterioration compared to the Si/SiO₂ interface degeneration under weak BTI stress. Furthermore, the observed linear relationship between the 1/f noise characteristics and MOS interface trap density was confirmed by the carrier number fluctuation model, indicating that 1/f noise characteristics could be considered as a sensitive and effective indicator for assessing MOS interface quality after weak BTI stress.

This article reports on the light sensitivity of Organic Thin Film Transistors (OTFTs) based on Nickel Phthalocyanine (NiPc). Phototransistors with three distinct channel lengths (25 μm, 40 μm, and 50 μm) are fabricated and compared for performance analysis. We investigate the impact of irradiance at various frequencies under different applied voltages on the performance of the phototransistor. Light exposure influences the resistance of nickel-phthalocyanine. The resistance of nickel-phthalocyanine undergoes a decrement, ranging from 185 to 0.8 KΩ, as the incident light intensity increases from zero to 130 foot candela (f_c), while varying the frequency from 0.1 to 5 KHz. Under conditions of low frequency (100 Hz) and a channel length of 25 μm, the resistance of the fabricated photosensitive transistor exhibits a decrease from 92 to 40 KΩ during a voltage sweep of 5 V. The resistance of the organic phototransistor (OPT) is noted to decrease with rising irradiance, and its performance is superior at low frequencies compared to high frequencies. The decrease in resistance is attributed to the bound charge carriers that get sufficient energy from the absorbed photon to surmount the barrier when the incident light on the device possesses enough energy. These liberated conduction electrons, or holes left behind, move freely, resulting in lower resistance. The obtained results demonstrate the potential efficiency of organic photosensitive transistors for utilization in optoelectronic devices.

In this article, a novel low trigger and fast turn on electrostatic discharge (ESD) protection device, called deep N-well diode-triggered silicon-controlled-rectifier (DNWTSCR), is proposed for 1.8 V I/O protection applications in the advanced 40-nm CMOS technology. By incorporating a deep N-well parasitic diode path into the conventional DTSCR, the triggering diodes-string gets prolonged and possesses higher impedance without area penalty. Owing to this, more current will branch to the inherent SCR during the operation, and consequently the DNWTSCR will present improved turn-on characteristics. The ESD characteristics of the proposed DNWTSCR and the conventional DTSCR were evaluated by Transmission Line Pulse (TLP) and Very Fast TLP (VFTLP). As results, the DNWTSCR presents a low trigger voltage of 3.4 V and an extremely fast turn-on time of 0.85 ns, which are 41 % and 51 % lower than the conventional DTSCR, respectively. Moreover, the TCAD simulation results agree well with the transmission line pulse testing results, further confirming that the proposed DNWTSCR can be widely used as an effective ESD protection device for high-speed ICs.

Printed Circuit Board Assemblies (PCBA) are crucial components of integrated circuit products. To address the issue of solder joint failure in PCBA under thermal cycling conditions, this study proposes a multiscale modeling approach to assess the warpage of the Printed Circuit Board (PCB) and the thermal fatigue life of solder joints during the PCBA working process. Firstly, a PCBA model incorporating the PCB, substrate, chip, Epoxy Molding Compound (EMC), and solder joints was established. The equivalent thermal-mechanical properties of the Conductive Layers (CDLs) in the PCB are calculated using a mesoscopic finite element approach to capture its complex structural characteristics. Finite Element Analysis (FEA) was conducted on the reflow soldering and thermal cycling processes of the PCBA to systematically investigate the effects of temperature variations during thermal cycling and residual stress from the manufacturing process on the fatigue life of solder joints. The results indicate that during the thermal cycling process, the complex deformation of the solder joints caused by the inconsistent deformation of the PCB and substrate as well as the accumulated inelastic strain of the solder joints lead to solder joint failures, and the dangerous solder joint is concentrated at the edges of the solder joint array. The temperature range significantly influenced the fatigue life of solder joints because of the thermal fatigue life of the solder joints decreased as the temperature range increased. The presence of residual stress during manufacturing reduces the fatigue life of solder joints, thus emphasizing the need to optimize the reflow process design to reduce residual stress in solder joints. The cross-scale simulation method developed in this study enables more accurate prediction of the thermal fatigue life of solder joints, thereby facilitating reliability studies and optimized designs of integrated circuit products.

Multilayer system composed of parallel plate components with different geometric dimensions is frequently used to describe engineering objects, such as electronic assembly. In this work, an analytical method was proposed for forced vibration of this type of multilayer system. The proposed method overcomes the limitation that the traditional wave method is only applicable to all plate components must have the same in-plane dimensions. The proposed analytical method has an efficiency advantages in parameter analysis than element-based methods such as finite element method (FEM). The connection joints between two adjacent plate components, such as ball grid array (BGA) solder interconnect, are represented by elastic springs. The vibration of each component are described in terms of general and physical analytical waves, respectively, and the dynamic coupling between them are established by an equivalent dynamic flexibility matrix. The forced responses of the multilayer system are analytically calculated by solving the system equation in wave space. In the numerical examples, the effectiveness of the proposed method is validated by comparing the present results with the FEM results. The influence of number of the defective solder joints on vibration response is also investigated.

The characteristics of thermomechanical fatigue life of complex electronic device system, micro-scaled design, is highly sensitive to changes in design factors. The solder ball, which acts as a linkage between the circuit board and the package, is a vital part to examine the performance of electronic device system. Repeated thermal loading causes the solder crack growth in models, eventually leads to the breakdown of devices. There have been lots of studies on investigating the fatigue life of solder joints employing well-established finite element procedure. However, generating a finite element model reflecting the whole device often requires unnecessarily large finite element matrices which may increase the computational cost and solder joint fatigue life can be highly dependent on the mesh resolutions. Recent studies suggest the sub-modeling method to handle the meshing process and alleviate the computational cost. In this paper, we delineate the methodology of two-step sub-modeling framework, aimed at improving the mesh fidelity of complex models while ensuring the efficiency of labor-intensive process of solder joint fatigue analysis. We employ the strain energy-based Darveaux's fatigue model to predict the fatigue life of solder joints. Through the investigation of the predicted fatigue life of solder joints across various sets of design parameters, it has been observed that the design factors of electronic devices exhibit a clear pattern in relation to the predicted fatigue life, even when only the second step of two-step sub-modeling framework is considered. Our findings suggest that it is efficient to utilize solely the second step of two-step sub-modeling framework to identify an appropriate reduced design space, where design parameters can be strategically selected for designing an optimal model.