Pub Date : 2026-02-11DOI: 10.1016/j.microrel.2026.116048
J. Sobas , F. Marc
Most of the time, ageing model for digital circuit are based on short time and high stress measurements. Then, ageing is extrapolated in time and for operational condition of use. Does the model correctly predict ageing after several years of use under normal temperature and voltage conditions? This paper presents ageing and measurements of degradation made during more than 20,000 h on an optimized test bench on nine FPGA including 567 ring oscillators each, with different temperature and voltage stresses. In our knowledge, this is the longer ageing test performed on digital circuit. Based on these measures, we compare semi-empirical modelling made with high temperature stresses and short ageing time (1000 h) with low temperature stresses and long ageing time (20,000 h).
{"title":"Extrapolation of the degradation on FinFET FPGA: Comparison between 20,000 h of measurement and model","authors":"J. Sobas , F. Marc","doi":"10.1016/j.microrel.2026.116048","DOIUrl":"10.1016/j.microrel.2026.116048","url":null,"abstract":"<div><div>Most of the time, ageing model for digital circuit are based on short time and high stress measurements. Then, ageing is extrapolated in time and for operational condition of use. Does the model correctly predict ageing after several years of use under normal temperature and voltage conditions? This paper presents ageing and measurements of degradation made during more than 20,000 h on an optimized test bench on nine FPGA including 567 ring oscillators each, with different temperature and voltage stresses. In our knowledge, this is the longer ageing test performed on digital circuit. Based on these measures, we compare semi-empirical modelling made with high temperature stresses and short ageing time (1000 h) with low temperature stresses and long ageing time (20,000 h).</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116048"},"PeriodicalIF":1.9,"publicationDate":"2026-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-11DOI: 10.1016/j.microrel.2026.116050
L. Karanja , S. Moser , M. Reisinger , M. Legros
We investigate the thermomechanical behaviour of thick copper metallization on polyheaters which are chips dedicated for stressing the thick copper metallizations found in high-end power electronic devices. The degradation mechanisms of these metallizations are known to span from surface roughening to crack formation, but the underlying elemental plastic deformation mechanisms (dislocation activity, stress-assisted diffusion, …) remain elusive. Here, we have combined post-mortem TEM observations of such polyheaters that underwent ultra-fast 300 K heating cycles and in-situ TEM heating experiments up to 480 °C. Both approaches converge to establish that the dislocation microstructure inside the grains is only slightly modified over these cycles and thus that dislocation-based plasticity cannot explain the crack formation and propagation, along with surface roughening observed in these Cu metallizations.
{"title":"In-situ TEM investigation of thermomechanical fatigue of thick copper metallizations","authors":"L. Karanja , S. Moser , M. Reisinger , M. Legros","doi":"10.1016/j.microrel.2026.116050","DOIUrl":"10.1016/j.microrel.2026.116050","url":null,"abstract":"<div><div>We investigate the thermomechanical behaviour of thick copper metallization on polyheaters which are chips dedicated for stressing the thick copper metallizations found in high-end power electronic devices. The degradation mechanisms of these metallizations are known to span from surface roughening to crack formation, but the underlying elemental plastic deformation mechanisms (dislocation activity, stress-assisted diffusion, …) remain elusive. Here, we have combined post-mortem TEM observations of such polyheaters that underwent ultra-fast 300 K heating cycles and in-situ TEM heating experiments up to 480 °C. Both approaches converge to establish that the dislocation microstructure inside the grains is only slightly modified over these cycles and thus that dislocation-based plasticity cannot explain the crack formation and propagation, along with surface roughening observed in these Cu metallizations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116050"},"PeriodicalIF":1.9,"publicationDate":"2026-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-09DOI: 10.1016/j.microrel.2026.116049
Vincenzo Terracciano , Alessandro Borghese , Carlo Ceresa , Vincenzo d'Alessandro , Andrea Irace
In this study, the surge current capability of a 60 A–1200 V 4H-SiC diode fabricated by paralleling two 30 A dies is experimentally evaluated. Three bond wire configurations are investigated using a non-repetitive surge current test at 25 °C and 110 °C. The results reveal that the stitch configuration, which employs 3 × 20 mil bonding wires, significantly outperforms the alternative 4 × 15 mil and 4 × 12 mil counterparts in terms of maximum surge current robustness. An extensive analysis is also conducted to identify key differences in the failure mechanisms among the three configurations during surge current stress.
在本研究中，实验评估了由两个30a二极管并联而成的60 a - 1200 V 4H-SiC二极管的浪涌电流能力。在25°C和110°C下使用非重复浪涌电流测试对三种键合线配置进行了研究。结果表明，在最大浪涌电流稳健性方面，采用3 × 20 mil键合线的针迹配置明显优于4 × 15 mil和4 × 12 mil对应的针迹配置。还进行了广泛的分析，以确定三种配置在浪涌电流应力下失效机制的关键差异。
{"title":"Optimal bonding of 4H-SiC parallel diodes in a single TO-247 package for improved surge current robustness: experimental investigation","authors":"Vincenzo Terracciano , Alessandro Borghese , Carlo Ceresa , Vincenzo d'Alessandro , Andrea Irace","doi":"10.1016/j.microrel.2026.116049","DOIUrl":"10.1016/j.microrel.2026.116049","url":null,"abstract":"<div><div>In this study, the surge current capability of a 60 A–1200 V 4H-SiC diode fabricated by paralleling two 30 A dies is experimentally evaluated. Three bond wire configurations are investigated using a non-repetitive surge current test at 25 °C and 110 °C. The results reveal that the <em>stitch</em> configuration, which employs 3 × 20 mil bonding wires, significantly outperforms the alternative 4 × 15 mil and 4 × 12 mil counterparts in terms of maximum surge current robustness. An extensive analysis is also conducted to identify key differences in the failure mechanisms among the three configurations during surge current stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116049"},"PeriodicalIF":1.9,"publicationDate":"2026-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-07DOI: 10.1016/j.microrel.2026.116040
Chen-Yu Liang, Ming-Dou Ker
With the continuous increase in operating frequency of RF integrated circuits (RF ICs) and high-speed serial link (HSSL), optimizing electrostatic discharge (ESD) protection robustness per unit capacitance has become critical. Traditional solutions, such as dual diodes, stacked diodes, and silicon-controlled rectifier (SCR), face limitations including high parasitic capacitance, elevated conduction resistance, and difficulties in maintaining low trigger voltages (Vt1) and sufficiently high holding voltages (Vh) above the latch-up threshold. These challenges render them less effective for high-frequency applications.
In this work, a P-type diode integrated with a P-type ESD (P-ESD) implantation layer is first fabricated and characterized. Building upon this, an enhanced diode-triggered SCR (DTSCR) incorporating the P-ESD implantation layer is proposed and implemented in 28-nm CMOS technology. The proposed DTSCR exhibits improved ESD performance, including reduced Vt1, lowered Vh, and enhanced human-body model (HBM) robustness normalized by the product of conduction resistance and parasitic capacitance. These results demonstrate the potential of the DTSCR with P-ESD implantation as a promising solution for parasitic capacitance efficiency and high-robustness ESD protection in RF ICs and HSSL applications.
{"title":"A junction-engineered SCR-based ESD protection device for radio-frequency and high-speed serial link interface circuits","authors":"Chen-Yu Liang, Ming-Dou Ker","doi":"10.1016/j.microrel.2026.116040","DOIUrl":"10.1016/j.microrel.2026.116040","url":null,"abstract":"<div><div>With the continuous increase in operating frequency of RF integrated circuits (RF ICs) and high-speed serial link (HSSL), optimizing electrostatic discharge (ESD) protection robustness per unit capacitance has become critical. Traditional solutions, such as dual diodes, stacked diodes, and silicon-controlled rectifier (SCR), face limitations including high parasitic capacitance, elevated conduction resistance, and difficulties in maintaining low trigger voltages (V<sub>t1</sub>) and sufficiently high holding voltages (V<sub>h</sub>) above the latch-up threshold. These challenges render them less effective for high-frequency applications.</div><div>In this work, a P-type diode integrated with a P-type ESD (P-ESD) implantation layer is first fabricated and characterized. Building upon this, an enhanced diode-triggered SCR (DTSCR) incorporating the P-ESD implantation layer is proposed and implemented in 28-nm CMOS technology. The proposed DTSCR exhibits improved ESD performance, including reduced V<sub>t1</sub>, lowered V<sub>h</sub>, and enhanced human-body model (HBM) robustness normalized by the product of conduction resistance and parasitic capacitance. These results demonstrate the potential of the DTSCR with P-ESD implantation as a promising solution for parasitic capacitance efficiency and high-robustness ESD protection in RF ICs and HSSL applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116040"},"PeriodicalIF":1.9,"publicationDate":"2026-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-06DOI: 10.1016/j.microrel.2026.116042
Sangmin Lee , Chuantong Chen , Masahiko Nishijima , Akihiro Katsura , Takuya Nakagiri , Juno Kim , Jung Shin Lee , Minwoo Daniel Rhee , Katsuaki Suganuma
In this study, the bonding strength and fracture behavior of wafer-to-wafer (W2W) bonding chip-scale Chevron-notch (CN) Si specimen was investigated using the tensile test with real-time acoustic emission (AE) monitoring. Fracture analysis could be identified into two failure modes, “interface open type” and “matrix crack type”. The bonding strength of the interface open type was slightly higher (6.41 J/m2) than the matrix crack type (6.12 J/m2). On the other hand, the interface open type exhibited higher AE absolute energy (4.0 × 107 aJ), 2.7 s of signal detection duration, and more detected signals (14.7 counts) compared to the matrix crack type, 2.3 × 107 aJ, 1.6 s, and 10.4 counts, respectively. Conventionally, both bonding strength measurement and microstructural analysis were required to classify fracture types, but AE monitoring enabled real-time identification during the tensile test.
{"title":"Real-time detection of fracture mode at the direct bonded Chevron-notch Si chip via acoustic emission","authors":"Sangmin Lee , Chuantong Chen , Masahiko Nishijima , Akihiro Katsura , Takuya Nakagiri , Juno Kim , Jung Shin Lee , Minwoo Daniel Rhee , Katsuaki Suganuma","doi":"10.1016/j.microrel.2026.116042","DOIUrl":"10.1016/j.microrel.2026.116042","url":null,"abstract":"<div><div>In this study, the bonding strength and fracture behavior of wafer-to-wafer (W2W) bonding chip-scale Chevron-notch (CN) Si specimen was investigated using the tensile test with real-time acoustic emission (AE) monitoring. Fracture analysis could be identified into two failure modes, “interface open type” and “matrix crack type”. The bonding strength of the interface open type was slightly higher (6.41 J/m<sup>2</sup>) than the matrix crack type (6.12 J/m<sup>2</sup>). On the other hand, the interface open type exhibited higher AE absolute energy (4.0 × 10<sup>7</sup> aJ), 2.7 s of signal detection duration, and more detected signals (14.7 counts) compared to the matrix crack type, 2.3 × 10<sup>7</sup> aJ, 1.6 s, and 10.4 counts, respectively. Conventionally, both bonding strength measurement and microstructural analysis were required to classify fracture types, but AE monitoring enabled real-time identification during the tensile test.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116042"},"PeriodicalIF":1.9,"publicationDate":"2026-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-04DOI: 10.1016/j.microrel.2026.116038
Zhe Liang , Yu Zhu , Ru Wang , Zhanjie Du , Yang Chen , Peng Yang , Yunhui Shi
This study aimed to optimize the backside chemical mechanical polishing (CMP) process of silicon through-hole (TSV) wafers by investigating diethylenetriamine (DETA). The study reveals DETA's synergistic mechanism through electrochemical analysis, characterization (FESEM/XPS), and density-functional theory (DFT) calculations. Under optimized conditions (1.5 wt% SiO2, 0.05 wt% SDBS and 0.25 wt% DETA), a high Si-to-Cu removal rate ratio of 16.7 is achieved, with a Si removal rate exceeding 1 μm/min. This ensures efficient Cu pillar exposure. Furthermore, surface roughness is significantly improved: Si Sq decreases from 1.790 nm to 0.825 nm and Cu Sq from 3.190 nm to 1.540 nm. The total thickness variation (TTV) meets industry standards. The findings provide a viable process optimization scheme and theoretical support for high-precision TSV polishing.
{"title":"Mechanism and performance optimization of diethylenetriamine in selectivity ratios for silicon and copper removal during TSV back-side CMP","authors":"Zhe Liang , Yu Zhu , Ru Wang , Zhanjie Du , Yang Chen , Peng Yang , Yunhui Shi","doi":"10.1016/j.microrel.2026.116038","DOIUrl":"10.1016/j.microrel.2026.116038","url":null,"abstract":"<div><div>This study aimed to optimize the backside chemical mechanical polishing (CMP) process of silicon through-hole (TSV) wafers by investigating diethylenetriamine (DETA). The study reveals DETA's synergistic mechanism through electrochemical analysis, characterization (FESEM/XPS), and density-functional theory (DFT) calculations. Under optimized conditions (1.5 wt% SiO<sub>2</sub>, 0.05 wt% SDBS and 0.25 wt% DETA), a high Si-to-Cu removal rate ratio of 16.7 is achieved, with a Si removal rate exceeding 1 μm/min. This ensures efficient Cu pillar exposure. Furthermore, surface roughness is significantly improved: Si Sq decreases from 1.790 nm to 0.825 nm and Cu Sq from 3.190 nm to 1.540 nm. The total thickness variation (TTV) meets industry standards. The findings provide a viable process optimization scheme and theoretical support for high-precision TSV polishing.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116038"},"PeriodicalIF":1.9,"publicationDate":"2026-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-03DOI: 10.1016/j.microrel.2026.116026
Kejia Wang , Zhendong Zhang , Fugui Zhou , Genhao Liang , Yuwei Fan , Lishan Zhao , Yaqing Chi
Hydrogen-terminated diamond MOS devices exhibit significant potential for space electronics applications due to their ultra-wide bandgap and radiation resistance. However, the degradation mechanism of device performance under X-ray total ionizing dose (TID) effects remains unclear. This study employed TCAD simulations to systematically investigate the influence of X-ray irradiation doses ranging from 0 to 50 MGy on the transport properties of the two-dimensional hole gas (2DHG) and electrical characteristics of the devices. Results indicated that with increasing irradiation dose, the saturation drain current and leakage current decreased, while the threshold voltage shifted negatively. This phenomenon is primarily attributed to trapped charges generated by TID effects, which impair the unique 2DHG transport properties in hydrogen-terminated diamond devices. Under high-dose conditions, hydrogen-terminated diamond MOS devices demonstrate superior radiation resistance compared to Si-based and other wide-bandgap semiconductor devices. This research provides a critical theoretical foundation for radiation-hardened design of aerospace-grade diamond devices.
{"title":"Research on the degradation mechanism of the electrical properties of hydrogen-terminated diamond MOS devices under X-ray irradiation","authors":"Kejia Wang , Zhendong Zhang , Fugui Zhou , Genhao Liang , Yuwei Fan , Lishan Zhao , Yaqing Chi","doi":"10.1016/j.microrel.2026.116026","DOIUrl":"10.1016/j.microrel.2026.116026","url":null,"abstract":"<div><div>Hydrogen-terminated diamond MOS devices exhibit significant potential for space electronics applications due to their ultra-wide bandgap and radiation resistance. However, the degradation mechanism of device performance under X-ray total ionizing dose (TID) effects remains unclear. This study employed TCAD simulations to systematically investigate the influence of X-ray irradiation doses ranging from 0 to 50 MGy on the transport properties of the two-dimensional hole gas (2DHG) and electrical characteristics of the devices. Results indicated that with increasing irradiation dose, the saturation drain current and leakage current decreased, while the threshold voltage shifted negatively. This phenomenon is primarily attributed to trapped charges generated by TID effects, which impair the unique 2DHG transport properties in hydrogen-terminated diamond devices. Under high-dose conditions, hydrogen-terminated diamond MOS devices demonstrate superior radiation resistance compared to Si-based and other wide-bandgap semiconductor devices. This research provides a critical theoretical foundation for radiation-hardened design of aerospace-grade diamond devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116026"},"PeriodicalIF":1.9,"publicationDate":"2026-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-02-02DOI: 10.1016/j.microrel.2026.116027
Clément Chedozeau , Merouane Ouhab , Natasha Vermaak , Nicolas Degrenne , François Hild
Reliability of power modules based on Insulated Gate Bipolar Transistors (IGBTs) is majorly challenged by thermomechanical fatigue, especially at the wirebond–chip interface where lift-off failure mechanisms commonly occur. This paper introduces a novel analytical model tailored to the geometry and material properties of the wirebond–chip interface to rapidly predict reliability performance maps highlighting different zones of expected elastoplastic behaviors under thermomechanical cycling. The model integrates a thermomechanical stress formulation with a Dugdale Cohesive Zone Model to capture plastic zone development at the interface and applies the Lower Bound Shakedown Theorem to identify elastoplastic behaviors without having to perform full cyclic incremental finite element simulations. The proposed analysis enables classification of cyclic behaviors into elastic, shakedown, and alternating plasticity regimes, providing a deeper understanding of the transition to low cycle fatigue at the shakedown/alternating plasticity boundary. Analytical predictions are compared to 2D finite element analyses, which confirm the ability of the model to capture key features like plastic strain evolution and its stabilization. The proposed modular model serves as a rapid and adaptable tool for early-stage reliability assessment as a function of geometric, material, and loading parameters.
{"title":"Analytical reliability performance maps for bond wire interfaces in power modules under cyclic thermomechanical loads","authors":"Clément Chedozeau , Merouane Ouhab , Natasha Vermaak , Nicolas Degrenne , François Hild","doi":"10.1016/j.microrel.2026.116027","DOIUrl":"10.1016/j.microrel.2026.116027","url":null,"abstract":"<div><div>Reliability of power modules based on Insulated Gate Bipolar Transistors (IGBTs) is majorly challenged by thermomechanical fatigue, especially at the wirebond–chip interface where lift-off failure mechanisms commonly occur. This paper introduces a novel analytical model tailored to the geometry and material properties of the wirebond–chip interface to rapidly predict reliability performance maps highlighting different zones of expected elastoplastic behaviors under thermomechanical cycling. The model integrates a thermomechanical stress formulation with a Dugdale Cohesive Zone Model to capture plastic zone development at the interface and applies the Lower Bound Shakedown Theorem to identify elastoplastic behaviors without having to perform full cyclic incremental finite element simulations. The proposed analysis enables classification of cyclic behaviors into elastic, shakedown, and alternating plasticity regimes, providing a deeper understanding of the transition to low cycle fatigue at the shakedown/alternating plasticity boundary. Analytical predictions are compared to 2D finite element analyses, which confirm the ability of the model to capture key features like plastic strain evolution and its stabilization. The proposed modular model serves as a rapid and adaptable tool for early-stage reliability assessment as a function of geometric, material, and loading parameters.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116027"},"PeriodicalIF":1.9,"publicationDate":"2026-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For three phase inverters, power semiconductor device MOSFET is the most sensitive component to failure which affects the reliability of the inverters directly. Through previous research on failure physical models, the junction temperature swing will mainly affect the remaining useful life of the MOSFET. Active thermal management is an effective way to control the temperature swing of control components. This paper proposes an optimized model predictive control for thermal management, which is achieved by suppressing overall system losses and focusing on vulnerable components, effectively suppressing the maximum junction temperature swing of the system. Afterwards, the reinforcement learning is used for weighting factors auto-tuning. The proposed method verified through experiment can effectively achieve balanced optimization of inverter life and performance and improve the reliability of the inverter system.
{"title":"Reinforcement learning-based weighting factors auto-tuning for thermal management in assembled inverters","authors":"Cen Chen, Junping Wei, Chenyi Wang, Kaiwen Xiao, Zhenning Zhou, Haodong Wang","doi":"10.1016/j.microrel.2026.116039","DOIUrl":"10.1016/j.microrel.2026.116039","url":null,"abstract":"<div><div>For three phase inverters, power semiconductor device MOSFET is the most sensitive component to failure which affects the reliability of the inverters directly. Through previous research on failure physical models, the junction temperature swing will mainly affect the remaining useful life of the MOSFET. Active thermal management is an effective way to control the temperature swing of control components. This paper proposes an optimized model predictive control for thermal management, which is achieved by suppressing overall system losses and focusing on vulnerable components, effectively suppressing the maximum junction temperature swing of the system. Afterwards, the reinforcement learning is used for weighting factors auto-tuning. The proposed method verified through experiment can effectively achieve balanced optimization of inverter life and performance and improve the reliability of the inverter system.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116039"},"PeriodicalIF":1.9,"publicationDate":"2026-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-29DOI: 10.1016/j.microrel.2026.116035
Binrui Xue , Ying Wei , Mingzhu Xun , Dan Zhang , Xiaowen Liang , Jiaxing Wang , Jingyi Xu , Jie Feng , Xuefeng Yu , Lin Wen , Qi Guo , Yudong Li
This study investigates the gate oxide reliability of silicon carbide (SiC) power MOSFETs irradiated by protons of three different energies, without inducing SEB. The results show that proton irradiation-induced latent damage in the gate oxide leads to a significant decrease in gate oxide breakdown voltage. As proton energy increases, the degradation of the device's gate oxide breakdown characteristics becomes more severe. After 300 MeV proton irradiation, the gate oxide breakdown voltage of the device approaches the gate's rated voltage. Monte Carlo simulations were used to calculate the equivalent Total Ionizing Dose (TID) and Displacement Damage Dose (DDD) for protons of different energies, along with the types, energies, and Linear Energy Transfer (LET) of the generated secondary particles. The analysis suggests that the latent damage in the SiC MOSFET gate oxide is primarily caused by secondary particles. Higher proton energy results in greater LET and range of secondary particles, leading to more severe latent damage within the device's gate oxide layer and, consequently, more significant degradation of gate oxide reliability.
{"title":"Degradation mechanisms of gate oxide reliability in SiC Power MOSFETs under different energy proton irradiation","authors":"Binrui Xue , Ying Wei , Mingzhu Xun , Dan Zhang , Xiaowen Liang , Jiaxing Wang , Jingyi Xu , Jie Feng , Xuefeng Yu , Lin Wen , Qi Guo , Yudong Li","doi":"10.1016/j.microrel.2026.116035","DOIUrl":"10.1016/j.microrel.2026.116035","url":null,"abstract":"<div><div>This study investigates the gate oxide reliability of silicon carbide (SiC) power MOSFETs irradiated by protons of three different energies, without inducing SEB. The results show that proton irradiation-induced latent damage in the gate oxide leads to a significant decrease in gate oxide breakdown voltage. As proton energy increases, the degradation of the device's gate oxide breakdown characteristics becomes more severe. After 300 MeV proton irradiation, the gate oxide breakdown voltage of the device approaches the gate's rated voltage. Monte Carlo simulations were used to calculate the equivalent Total Ionizing Dose (TID) and Displacement Damage Dose (DDD) for protons of different energies, along with the types, energies, and Linear Energy Transfer (LET) of the generated secondary particles. The analysis suggests that the latent damage in the SiC MOSFET gate oxide is primarily caused by secondary particles. Higher proton energy results in greater LET and range of secondary particles, leading to more severe latent damage within the device's gate oxide layer and, consequently, more significant degradation of gate oxide reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116035"},"PeriodicalIF":1.9,"publicationDate":"2026-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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