This paper investigates the time-dependent gate breakdown of High Electron Mobility Transistors (HEMT) by applying constant stress to the gate until a catastrophic failure occurs. Measurements were conducted on two references. Reference A was tested from −55 °C to 80 °C, showing a negative activation energy, which is more likely due to dielectric breakdown near the p-GaN triggered by impact ionization and accelerated at lower temperatures. Device B, tested from −40 °C to 120 °C, exhibited a positive activation energy, indicating a lower Mean Time To Failure at higher temperatures. This positive activation energy is linked to the behavior of the gate temperature-dependent leakage current, which might increase faster with temperature than the impact ionization decrease, leading to the positive activation energy.
{"title":"On the activation energy in SP-GaN gate HEMT devices during gate lifetime test","authors":"Maroun Alam , Valeria Rustichelli , Moustafa Zerarka , Christophe Banc , Jean-François Pieprzyk , Olivier Perrotin , Romain Ceccarelli , David Trémouilles , Mohamed Matmat , Fabio Coccetti","doi":"10.1016/j.microrel.2025.115986","DOIUrl":"10.1016/j.microrel.2025.115986","url":null,"abstract":"<div><div>This paper investigates the time-dependent gate breakdown of High Electron Mobility Transistors (HEMT) by applying constant stress to the gate until a catastrophic failure occurs. Measurements were conducted on two references. Reference A was tested from −55 °C to 80 °C, showing a negative activation energy, which is more likely due to dielectric breakdown near the p-GaN triggered by impact ionization and accelerated at lower temperatures. Device B, tested from −40 °C to 120 °C, exhibited a positive activation energy, indicating a lower Mean Time To Failure at higher temperatures. This positive activation energy is linked to the behavior of the gate temperature-dependent leakage current, which might increase faster with temperature than the impact ionization decrease, leading to the positive activation energy.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115986"},"PeriodicalIF":1.9,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-20DOI: 10.1016/j.microrel.2025.115980
I. Marozau , Q. Tang , M. Kulsreshath , Y. Li , S.J. Bleiker , F. Niklaus , D. Pamunuwa
Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.
{"title":"Mechanical shock and vibration testing of volatile and non-volatile nanoelectromechanical switches","authors":"I. Marozau , Q. Tang , M. Kulsreshath , Y. Li , S.J. Bleiker , F. Niklaus , D. Pamunuwa","doi":"10.1016/j.microrel.2025.115980","DOIUrl":"10.1016/j.microrel.2025.115980","url":null,"abstract":"<div><div>Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115980"},"PeriodicalIF":1.9,"publicationDate":"2025-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1016/j.microrel.2025.115984
Huihui Wu, Haisheng Miao, Yingying Yang, Jiawei Yu, Ye Fu, Zhenhua Song, Zhaofeng Li
The gate-source voltage (Vgs) is a critical electrical parameter which can make the Split-Gate-Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) maintain stability and reliability in various control scenarios. The impacts of high density plasma chemical vapor deposition (HDPCVD) and low pressure chemical vapor deposition (LPCVD) methods on the morphology of the inter-poly oxide (IPO) layer, as well as their subsequent effects on Vgs performance, were investigated in this study. Specifically, two sputtering agents, Ar and He, were utilized in the HDPCVD approach. Wet etching rates of the different films explain the mechanism of rounded IPO morphology formation. Scanning electron microscope (SEM) observations and electrical characterization results demonstrate that the rounded bottom corners of the optimized gate polysilicon, fabricated by HDP He combined with Ar plasma method, exhibit superior Vgs & lower leakage current performance.
{"title":"Enhanced gate-source voltage in SGT MOSFET via inter poly oxide process-induced morphology improvement","authors":"Huihui Wu, Haisheng Miao, Yingying Yang, Jiawei Yu, Ye Fu, Zhenhua Song, Zhaofeng Li","doi":"10.1016/j.microrel.2025.115984","DOIUrl":"10.1016/j.microrel.2025.115984","url":null,"abstract":"<div><div>The gate-source voltage (Vgs) is a critical electrical parameter which can make the Split-Gate-Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) maintain stability and reliability in various control scenarios. The impacts of high density plasma chemical vapor deposition (HDPCVD) and low pressure chemical vapor deposition (LPCVD) methods on the morphology of the inter-poly oxide (IPO) layer, as well as their subsequent effects on Vgs performance, were investigated in this study. Specifically, two sputtering agents, Ar and He, were utilized in the HDPCVD approach. Wet etching rates of the different films explain the mechanism of rounded IPO morphology formation. Scanning electron microscope (SEM) observations and electrical characterization results demonstrate that the rounded bottom corners of the optimized gate polysilicon, fabricated by HDP He combined with Ar plasma method, exhibit superior Vgs & lower leakage current performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115984"},"PeriodicalIF":1.9,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-17DOI: 10.1016/j.microrel.2025.115982
Vanshika Rajpal , A. Charan Kumari , K. Srinivas
Accurate and scalable fault diagnosis in analog integrated circuits (AICs) remains a significant challenge, particularly in detecting soft parametric faults arising from process variations, aging, and environmental factors. This paper presents a comprehensive machine learning–based framework for automated fault classification in linear analog circuits, demonstrated through two representative case studies, an RC band-pass filter and a Butterworth low-pass filter. Frequency-domain responses of both output voltage and supply current were analysed, and complex-valued features comprising real and imaginary components were extracted to capture the circuits' resistive and reactive characteristics.
Monte Carlo simulations with ±30 % component deviations generated a rich dataset for training and validation. Nine machine learning classifiers, including CatBoost, LightGBM, and XGBoost, were benchmarked against traditional approaches. The proposed complex-domain feature extraction method significantly outperformed magnitude-only and real-part-only baselines, with CatBoost achieving the highest accuracy of 99.75 %. Computational efficiency and inference analysis confirmed the model's suitability for real-time fault diagnosis, with millisecond-level latency and compact model size. SHAP (SHapley Additive exPlanations) analysis provided interpretability by identifying the most influential spectral features contributing to fault classification.
Finally, the framework's generalisation and practical feasibility were demonstrated through cross-circuit evaluation and a hardware validation perspective, outlining measurement procedures and highlighting its real-world applicability. The results confirm that the proposed approach effectively integrates high diagnostic accuracy, interpretability, and computational efficiency, establishing a robust and explainable solution for fault diagnosis in linear analog circuits.
{"title":"Machine learning classifiers with explainable insights for parametric fault diagnosis in linear analog circuits using frequency response features","authors":"Vanshika Rajpal , A. Charan Kumari , K. Srinivas","doi":"10.1016/j.microrel.2025.115982","DOIUrl":"10.1016/j.microrel.2025.115982","url":null,"abstract":"<div><div>Accurate and scalable fault diagnosis in analog integrated circuits (AICs) remains a significant challenge, particularly in detecting soft parametric faults arising from process variations, aging, and environmental factors. This paper presents a comprehensive machine learning–based framework for automated fault classification in linear analog circuits, demonstrated through two representative case studies, an RC band-pass filter and a Butterworth low-pass filter. Frequency-domain responses of both output voltage and supply current were analysed, and complex-valued features comprising real and imaginary components were extracted to capture the circuits' resistive and reactive characteristics.</div><div>Monte Carlo simulations with ±30 % component deviations generated a rich dataset for training and validation. Nine machine learning classifiers, including CatBoost, LightGBM, and XGBoost, were benchmarked against traditional approaches. The proposed complex-domain feature extraction method significantly outperformed magnitude-only and real-part-only baselines, with CatBoost achieving the highest accuracy of 99.75 %. Computational efficiency and inference analysis confirmed the model's suitability for real-time fault diagnosis, with millisecond-level latency and compact model size. SHAP (SHapley Additive exPlanations) analysis provided interpretability by identifying the most influential spectral features contributing to fault classification.</div><div>Finally, the framework's generalisation and practical feasibility were demonstrated through cross-circuit evaluation and a hardware validation perspective, outlining measurement procedures and highlighting its real-world applicability. The results confirm that the proposed approach effectively integrates high diagnostic accuracy, interpretability, and computational efficiency, establishing a robust and explainable solution for fault diagnosis in linear analog circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115982"},"PeriodicalIF":1.9,"publicationDate":"2025-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115978
Gyuhyeok Kang , Ogyun Seok
The long-term reliability of 1.2 kV 4H-SiC MOSFETs monolithically integrated with Schottky barrier diodes (SBDs) was systematically investigated under repetitive thermo-electrical stress using DC power cycling. While SBD integration suppresses reverse-recovery charge and enhances high-frequency switching performance, the additional metal–semiconductor junctions in the body diode region introduce potential failure sites susceptible to thermally activated degradation mechanisms. In this work, devices with and without embedded SBDs were subjected to controlled junction temperature swings (ΔTj = 110 °C, Tj,m = 120 °C) for multiple cycling intervals. Temperature-sensitive electrical parameter (TSEP) monitoring, based on the low-current source–drain voltage (VSD), was performed in-situ during every power cycling event, enabling continuous tracking of junction temperature variation associated with SBD forward voltage shift. A comprehensive parametric analysis including on state resistance (Ron), threshold voltage (Vth), breakdown voltage (BV), forward conduction characteristics (VF), and reverse leakage characteristics was conducted to identify the dominant degradation mechanisms in SiC MOSFETs with embedded SBDs under power cycling conditions.
{"title":"Power cycling-induced degradation mechanisms in SiC MOSFETs with embedded Schottky barrier diodes","authors":"Gyuhyeok Kang , Ogyun Seok","doi":"10.1016/j.microrel.2025.115978","DOIUrl":"10.1016/j.microrel.2025.115978","url":null,"abstract":"<div><div>The long-term reliability of 1.2 kV 4H-SiC MOSFETs monolithically integrated with Schottky barrier diodes (SBDs) was systematically investigated under repetitive thermo-electrical stress using DC power cycling. While SBD integration suppresses reverse-recovery charge and enhances high-frequency switching performance, the additional metal–semiconductor junctions in the body diode region introduce potential failure sites susceptible to thermally activated degradation mechanisms. In this work, devices with and without embedded SBDs were subjected to controlled junction temperature swings (ΔT<sub>j</sub> = 110 °C, T<sub>j,m</sub> = 120 °C) for multiple cycling intervals. Temperature-sensitive electrical parameter (TSEP) monitoring, based on the low-current source–drain voltage (V<sub>SD</sub>), was performed in-situ during every power cycling event, enabling continuous tracking of junction temperature variation associated with SBD forward voltage shift. A comprehensive parametric analysis including on state resistance (R<sub>on</sub>), threshold voltage (V<sub>th</sub>), breakdown voltage (BV), forward conduction characteristics (V<sub>F</sub>), and reverse leakage characteristics was conducted to identify the dominant degradation mechanisms in SiC MOSFETs with embedded SBDs under power cycling conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115978"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115975
Nanditha Gajanur , Mohammad A. Abbaszada , Shantanu Gupta , Sudip K. Mazumder
The reliability of semiconductor switches in single-stage differential-mode solid-state transformers (DM-SSTs) has not been systematically evaluated under soft-switching operation and realistic grid conditions. This paper presents a switch-level reliability analysis for soft-switched and hard-switched DM-SST configurations by integrating converter-specific power loss modeling with empirical lifetime prediction. Analytical derivation of device current profiles specific to the DM-SST is used to characterize electrothermal stress, which is then mapped to lifetime using degradation models obtained from power cycling tests (PCTs). Applied to realistic SST load profiles and grid voltage variations, this approach provides a probabilistic prediction of switch lifetime for the DM-SST. Lifetime estimates for both SiC MOSFETs and Si IGBTs are presented, offering insight into device degradation under converter operating conditions. The results quantify the reliability benefits of soft switching in single-stage SSTs, highlighting how switching dynamics influence long-term switch degradation.
{"title":"Evaluating switch lifetime in soft-switched single-stage differential-mode SST","authors":"Nanditha Gajanur , Mohammad A. Abbaszada , Shantanu Gupta , Sudip K. Mazumder","doi":"10.1016/j.microrel.2025.115975","DOIUrl":"10.1016/j.microrel.2025.115975","url":null,"abstract":"<div><div>The reliability of semiconductor switches in single-stage differential-mode solid-state transformers (DM-SSTs) has not been systematically evaluated under soft-switching operation and realistic grid conditions. This paper presents a switch-level reliability analysis for soft-switched and hard-switched DM-SST configurations by integrating converter-specific power loss modeling with empirical lifetime prediction. Analytical derivation of device current profiles specific to the DM-SST is used to characterize electrothermal stress, which is then mapped to lifetime using degradation models obtained from power cycling tests (PCTs). Applied to realistic SST load profiles and grid voltage variations, this approach provides a probabilistic prediction of switch lifetime for the DM-SST. Lifetime estimates for both SiC MOSFETs and Si IGBTs are presented, offering insight into device degradation under converter operating conditions. The results quantify the reliability benefits of soft switching in single-stage SSTs, highlighting how switching dynamics influence long-term switch degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115975"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115981
Yan Ma , Majiaqi Wu , Lianqiao Yang
Fan-out wafer-level packaging (FO-WLP), as a breakthrough advanced packaging technology, achieves high density interconnections by embedding chips into epoxy mold compound (EMC) and forming redistribution layers outside the die area. However, die shift, which is a slight displacement of the die from its intended position, poses a significant challenge during the molding process, affecting alignment and yield. This study systematically analyzes the effects of warpage, thermal expansion/contraction, EMC curing shrinkage and fluid drag force on die shift through multi-physics coupling simulations and numerical computation. It quantifies the contributions of thermal and fluid effects to die shift under different EMC viscosities and thicknesses. The results indicate that thermal effects are the dominant factor causing die shift; fluid effects become significant only under high-viscosity conditions, with a maximum contribution of approximately 30 %. As EMC thickness increases, the peak total shift moves toward the wafer edge, while high viscosity shifts it closer to the center. Thinner EMC exacerbates warpage but reduces die shift, whereas thicker EMC has the opposite effect. This study provides critical insights for optimizing process parameters, controlling die shift, and enhancing packaging reliability.
{"title":"Multi-physics coupling simulation and numerical computation of die shift in fan-out wafer-level packaging","authors":"Yan Ma , Majiaqi Wu , Lianqiao Yang","doi":"10.1016/j.microrel.2025.115981","DOIUrl":"10.1016/j.microrel.2025.115981","url":null,"abstract":"<div><div>Fan-out wafer-level packaging (FO-WLP), as a breakthrough advanced packaging technology, achieves high density interconnections by embedding chips into epoxy mold compound (EMC) and forming redistribution layers outside the die area. However, die shift, which is a slight displacement of the die from its intended position, poses a significant challenge during the molding process, affecting alignment and yield. This study systematically analyzes the effects of warpage, thermal expansion/contraction, EMC curing shrinkage and fluid drag force on die shift through multi-physics coupling simulations and numerical computation. It quantifies the contributions of thermal and fluid effects to die shift under different EMC viscosities and thicknesses. The results indicate that thermal effects are the dominant factor causing die shift; fluid effects become significant only under high-viscosity conditions, with a maximum contribution of approximately 30 %. As EMC thickness increases, the peak total shift moves toward the wafer edge, while high viscosity shifts it closer to the center. Thinner EMC exacerbates warpage but reduces die shift, whereas thicker EMC has the opposite effect. This study provides critical insights for optimizing process parameters, controlling die shift, and enhancing packaging reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115981"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-16DOI: 10.1016/j.microrel.2025.115985
Osman KAHVECİ , Muh RUSDI , Abdullah AKKAYA , Enise AYYILDIZ
Copper conductive thin films or components in microelectronic devices face significant corrosion challenges that compromise long-term reliability. This study presents a comprehensive investigation of hafnium dioxide (HfO₂) as a protective barrier layer deposited by RF magnetron sputtering at varying thicknesses (150 and 300 nm) on copper substrates for possible microelectronic applications. Multi-technique characterization methods, including SEM-EDX, AFM, XRD, FTIR, UV–Vis spectroscopy, contact angle measurements, potentiodynamic polarization, and electrochemical impedance spectroscopy (EIS), were employed to establish structure, property, and performance relationships. EDX results show that the addition of an HfO₂ layer significantly modified the surface morphology, especially on presence of 300 nm HfO₂ layer, so that the surface appears continuous and uniform. This is also supported by the FTIR analysis results, which indicate the presence of the strongest HfO and Hf-O-Hf vibrational bonds, thereby confirming the formation of an HfO₂ layer on the Cu surface. AFM results show an increase in surface topography roughness, caused by island-type growth (Volmer-Weber), as the thickness of the HfO₂ layer increases. The XRD results for un-coated sample shows sharp and clear diffraction peaks and indicates face-centered cubic (FCC) phase pattern of pure Cu nanoparticles. When the HfO2 layer added Cu layer, XRD pattern shows the formation of a broad hump in the range of 2θ ≈ 28°–35° and HfO2 layer formed is in the amorphous state. These results are correlated with the contact angle test results. UV–Vis results show that 300 nm HfO₂ coted films has the highest transmittance value across the entire wavelength range, as well as the lowest absorbance value. The 300 nm HfO₂ coating demonstrated optimal corrosion protection with 21.2 % reduction in corrosion current density (from 11.3 to 8.89 μA/cm2) and 29 % increase in polarization resistance (from 1.45 to 1.87 kΩ cm2) in artificial sweat environment. Finally, surface wettability studies revealed that increased hydrophobicity (contact angle:49.13° to 57.99°) was correlated with enhanced corrosion barrier performance. These findings establish RF-sputtered HfO₂ as a viable, scalable solution for copper protection in next-generation microelectronic and wearable biosensor applications.
{"title":"HfO₂ barrier layers: Thickness-dependent corrosion protection of copper thin films for potential microelectronic applications with sweat contact","authors":"Osman KAHVECİ , Muh RUSDI , Abdullah AKKAYA , Enise AYYILDIZ","doi":"10.1016/j.microrel.2025.115985","DOIUrl":"10.1016/j.microrel.2025.115985","url":null,"abstract":"<div><div>Copper conductive thin films or components in microelectronic devices face significant corrosion challenges that compromise long-term reliability. This study presents a comprehensive investigation of hafnium dioxide (HfO₂) as a protective barrier layer deposited by RF magnetron sputtering at varying thicknesses (150 and 300 nm) on copper substrates for possible microelectronic applications. Multi-technique characterization methods, including SEM-EDX, AFM, XRD, FTIR, UV–Vis spectroscopy, contact angle measurements, potentiodynamic polarization, and electrochemical impedance spectroscopy (EIS), were employed to establish structure, property, and performance relationships. EDX results show that the addition of an HfO₂ layer significantly modified the surface morphology, especially on presence of 300 nm HfO₂ layer, so that the surface appears continuous and uniform. This is also supported by the FTIR analysis results, which indicate the presence of the strongest Hf<img>O and Hf-O-Hf vibrational bonds, thereby confirming the formation of an HfO₂ layer on the Cu surface. AFM results show an increase in surface topography roughness, caused by island-type growth (Volmer-Weber), as the thickness of the HfO₂ layer increases. The XRD results for un-coated sample shows sharp and clear diffraction peaks and indicates face-centered cubic (FCC) phase pattern of pure Cu nanoparticles. When the HfO<sub>2</sub> layer added Cu layer, XRD pattern shows the formation of a broad hump in the range of 2θ ≈ 28°–35° and HfO<sub>2</sub> layer formed is in the amorphous state. These results are correlated with the contact angle test results. UV–Vis results show that 300 nm HfO₂ coted films has the highest transmittance value across the entire wavelength range, as well as the lowest absorbance value. The 300 nm HfO₂ coating demonstrated optimal corrosion protection with 21.2 % reduction in corrosion current density (from 11.3 to 8.89 μA/cm<sup>2</sup>) and 29 % increase in polarization resistance (from 1.45 to 1.87 kΩ cm<sup>2</sup>) in artificial sweat environment. Finally, surface wettability studies revealed that increased hydrophobicity (contact angle:49.13° to 57.99°) was correlated with enhanced corrosion barrier performance. These findings establish RF-sputtered HfO₂ as a viable, scalable solution for copper protection in next-generation microelectronic and wearable biosensor applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115985"},"PeriodicalIF":1.9,"publicationDate":"2025-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, machine-learning-assisted co-design framework that links high-fidelity finite-element analysis (FEA) with surrogate modeling, multi-objective optimization, and decision analysis. A 3D FEA model generates 500 Latin Hypercube design points for type of analysis (thermal and reliability), spanning geometry, materials, and thermal-path variables. Four minimized objectives are considered: junction-to-ambient thermal resistance () and cycle-averaged plastic strain-energy density at the corner flip-chip cu-pillar bump (), C4 bump (), and BGA (). Tree-based regressors (Random Forest, XGBoost) achieve high test-set fidelity and drive NSGA-II to enumerate the Pareto domain. A Net Flow multi-criteria decision method (MCDM) ranks Pareto candidates to identify a champion design with balanced thermo-mechanical performance. Re-simulation of the champion in FEA confirms surrogate accuracy for dominant responses (≈4–5 % deviation for and ) and exact agreement for , while revealing weak coupling between thermal and mechanical objectives—enabling partial decoupling of heat-path optimization from interconnect reliability.
{"title":"Thermo-mechanical co-design of 2.5D flip-chip packages with silicon and glass interposers via finite element analysis and machine learning","authors":"Mohammad Rafiee , Farough Agin , Kuldeep Kumar , Ezhilan Murali","doi":"10.1016/j.microrel.2025.115983","DOIUrl":"10.1016/j.microrel.2025.115983","url":null,"abstract":"<div><div>Advanced 2.5D flip-chip packages with silicon/glass interposers may pose tightly coupled thermo-mechanical trade-offs. This work presents a simulation-driven, machine-learning-assisted co-design framework that links high-fidelity finite-element analysis (FEA) with surrogate modeling, multi-objective optimization, and decision analysis. A 3D FEA model generates 500 Latin Hypercube design points for type of analysis (thermal and reliability), spanning geometry, materials, and thermal-path variables. Four minimized objectives are considered: junction-to-ambient thermal resistance (<span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>) and cycle-averaged plastic strain-energy density at the corner flip-chip cu-pillar bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub></math></span>), C4 bump (<span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>), and BGA (<span><math><mi>Δ</mi><msub><mi>W</mi><mi>BGA</mi></msub></math></span>). Tree-based regressors (Random Forest, XGBoost) achieve high test-set fidelity and drive NSGA-II to enumerate the Pareto domain. A Net Flow multi-criteria decision method (MCDM) ranks Pareto candidates to identify a champion design with balanced thermo-mechanical performance. <em>Re</em>-simulation of the champion in FEA confirms surrogate accuracy for dominant responses (≈4–5 % deviation for <span><math><mi>Δ</mi><msub><mi>W</mi><mtext>bump</mtext></msub><mspace></mspace></math></span>and <span><math><mi>Δ</mi><msub><mi>W</mi><mrow><mi>C</mi><mn>4</mn></mrow></msub></math></span>) and exact agreement for <span><math><msub><mi>Θ</mi><mi>JA</mi></msub></math></span>, while revealing weak coupling between thermal and mechanical objectives—enabling partial decoupling of heat-path optimization from interconnect reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115983"},"PeriodicalIF":1.9,"publicationDate":"2025-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-12DOI: 10.1016/j.microrel.2025.115976
Dorottya Varga , Zsombor Olajos , Gabor Belina
Estimating solder joint lifetime often involves extrapolating crack length measurements from cross-sectional images to a defined end-of-life (EoL) criterion. The original pearl string method fits a single regression line to all data points, which can result in unrealistic predictions, such as negative slopes or failure times. To address these issues, an alternative pearl string method was proposed, incorporating a fixed crack-free time (CFT) ratio to better reflect actual damage evolution. This study compares the two methods in terms of robustness, accuracy, and statistical consistency. The alternative method fits individual crack propagation curves for each specimen, enabling lifetime estimation in destructive testing with limited measurement points. Outlier sensitivity analysis showed that the original method is highly affected by anomalous data, while the alternative method exhibited minimal change. Goodness-of-fit evaluation using the Kolmogorov–Smirnov test confirmed that the alternative method aligns more closely with the validation data (p = 0.09 and 0.22), unlike the original method (p = 3.66 × 10−6 and 1.20 × 10−8). In conclusion, the alternative pearl string method offers a more robust and physically meaningful approach for lifetime extrapolation, especially in contexts with limited or noisy data.
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