Pub Date : 2024-11-04DOI: 10.1016/j.microrel.2024.115534
Yanfei Gong , Xingtong Chen , Qiang Zhao , Zhensong Li , Yueqin Li , Jieqing Fan , Jianhong Hao , Fang Zhang , Zhiwei Dong
This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.
本研究调查了导通状态辐照偏置下总电离剂量（TID）对体鳍式场效应晶体管的影响，旨在分析辐照增强效应的原因和物理机制。利用技术计算机辅助设计 (TCAD)，我们首次发现位于浅沟槽隔离（STI）氧化物顶点的寄生晶体管对器件的亚阈值劣化有显著作用，导致离态漏电流明显增加。此外，在相同的辐照偏置条件下，窄鳍片和短沟道器件的关态漏电流增加更为明显。这种增加分别归因于 STI 氧化物中捕获的电荷量增加和冲穿停止层（PTS）静电电位升高。此外，较高的漏极电压会降低 STI 寄生晶体管的阈值电压，从而导致漏极电压升高时的关态电流增大。总之，研究导通偏压下体式 FinFET 的 TID 效应至关重要，因为它可以为强化纳米结构器件防止辐照引起的降解提供理论支持。
{"title":"A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation","authors":"Yanfei Gong , Xingtong Chen , Qiang Zhao , Zhensong Li , Yueqin Li , Jieqing Fan , Jianhong Hao , Fang Zhang , Zhiwei Dong","doi":"10.1016/j.microrel.2024.115534","DOIUrl":"10.1016/j.microrel.2024.115534","url":null,"abstract":"<div><div>This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115534"},"PeriodicalIF":1.6,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142577875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-02DOI: 10.1016/j.microrel.2024.115529
Shuyi Li , Chunyue Huang , Xiaobin Liu , Gui Wang , Ying Liang , Chao Gao , Zhiqin Cao
The solder joint finite element analysis model of the 0201 chip component was established, by carrying out the shear loading and tensile loading finite element analysis respectively, the stress distribution pattern of the solder joint shear stress and tension stress were obtained. A solder joint stress measurement platform for the chip component was built, the solder joint stress measurement for the chip component under shear load was completed, and the accuracy of the simulation analysis results was verified. Selecting the solder joint volume, pad gap height, and pad length as design variables, and taking the maximum shear and tensile stress of the solder joint as the target, 16 groups of different parameter level combinations were designed by orthogonal test method, and combining with gray correlation analysis method, the bi-objective optimization design of shear and tensile stress of chip component solder joints was carried out—the optimal level combination of shear and tensile stress was obtained and verified by simulation. The results show that the influence ranking of maximum shear stress and tensile stress in solder joints of chip component are both pad gap height, pad length, and solder joint volume. The optimal parameter level combination is the solder joint volume of 0.0147mm, pad gap height of 0.05 mm, pad length of 0.35 mm, the maximum shear stress and the maximum tensile stress of the chip component solder joints increase by 44% and 23% respectively after the optimization, enhancing the shear strength and tensile strength of the solder joints in chip component simultaneously.
{"title":"Solder joints stress analysis and optimization of chip component under shear and tensile load based on orthogonal experimental design and gray correlation analysis","authors":"Shuyi Li , Chunyue Huang , Xiaobin Liu , Gui Wang , Ying Liang , Chao Gao , Zhiqin Cao","doi":"10.1016/j.microrel.2024.115529","DOIUrl":"10.1016/j.microrel.2024.115529","url":null,"abstract":"<div><div>The solder joint finite element analysis model of the 0201 chip component was established, by carrying out the shear loading and tensile loading finite element analysis respectively, the stress distribution pattern of the solder joint shear stress and tension stress were obtained. A solder joint stress measurement platform for the chip component was built, the solder joint stress measurement for the chip component under shear load was completed, and the accuracy of the simulation analysis results was verified. Selecting the solder joint volume, pad gap height, and pad length as design variables, and taking the maximum shear and tensile stress of the solder joint as the target, 16 groups of different parameter level combinations were designed by orthogonal test method, and combining with gray correlation analysis method, the bi-objective optimization design of shear and tensile stress of chip component solder joints was carried out—the optimal level combination of shear and tensile stress was obtained and verified by simulation. The results show that the influence ranking of maximum shear stress and tensile stress in solder joints of chip component are both pad gap height, pad length, and solder joint volume. The optimal parameter level combination is the solder joint volume of 0.0147mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>, pad gap height of 0.05 mm, pad length of 0.35 mm, the maximum shear stress and the maximum tensile stress of the chip component solder joints increase by 44% and 23% respectively after the optimization, enhancing the shear strength and tensile strength of the solder joints in chip component simultaneously.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115529"},"PeriodicalIF":1.6,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142572879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-02DOI: 10.1016/j.microrel.2024.115533
Mohamad Aizat bin Abas , Muhamed Abdul Fatah bin Muhamed Mukhtar
This paper studies the effect of different air gaps on multi-stack printed circuit board (PCB) using finite volume method (FVM). Air gaps of 150 mm2 and 450 mm2 were introduced to investigate their influence on flow parameters such as filling time, pressure distribution, and void formation during the capillary underfill encapsulation process. It was found that increasing the air gap size improved the filling time by 10 %, though it also doubled the pressure, which helps reduce void formation but requires careful control to prevent encapsulant overflow. Throughout the study, an L-type dispensing method was applied on a perimeter type multi-stack BGA with wall type barrier added on the sides of the multi-stack PCB to prevent encapsulant. This new wall type barrier henceforth requires comprehensive study on the size of the air gaps to ensure crucial flow parameters such as void formation, filling time, pressure distribution and flow front pattern are optimized. Two air gap sizes given as 150 mm2 and 450 mm2 are used in this study. Moreover, the fluid flow patterns from both studies are investigated to determine the problem of racing effect and void formation. Based on the findings, it was found that 10 % improvement in the filling time can be made by using a bigger air gap of 450 mm2. However, with bigger air gap, the pressure increases two-fold which can be good in reducing the void formation though the trade-off can be on the risk of excessive overflow of encapsulant.
{"title":"Effects of different air gaps of underfill encapsulant on multi-stack printed circuit board","authors":"Mohamad Aizat bin Abas , Muhamed Abdul Fatah bin Muhamed Mukhtar","doi":"10.1016/j.microrel.2024.115533","DOIUrl":"10.1016/j.microrel.2024.115533","url":null,"abstract":"<div><div>This paper studies the effect of different air gaps on multi-stack printed circuit board (PCB) using finite volume method (FVM). Air gaps of 150 mm<sup>2</sup> and 450 mm<sup>2</sup> were introduced to investigate their influence on flow parameters such as filling time, pressure distribution, and void formation during the capillary underfill encapsulation process. It was found that increasing the air gap size improved the filling time by 10 %, though it also doubled the pressure, which helps reduce void formation but requires careful control to prevent encapsulant overflow. Throughout the study, an L-type dispensing method was applied on a perimeter type multi-stack BGA with wall type barrier added on the sides of the multi-stack PCB to prevent encapsulant. This new wall type barrier henceforth requires comprehensive study on the size of the air gaps to ensure crucial flow parameters such as void formation, filling time, pressure distribution and flow front pattern are optimized. Two air gap sizes given as 150 mm<sup>2</sup> and 450 mm<sup>2</sup> are used in this study. Moreover, the fluid flow patterns from both studies are investigated to determine the problem of racing effect and void formation. Based on the findings, it was found that 10 % improvement in the filling time can be made by using a bigger air gap of 450 mm<sup>2</sup>. However, with bigger air gap, the pressure increases two-fold which can be good in reducing the void formation though the trade-off can be on the risk of excessive overflow of encapsulant.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115533"},"PeriodicalIF":1.6,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142572880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1016/j.microrel.2024.115532
Zhimei Yang , Yun Li , Mingmin Huang , Min Gong , Yao Ma
The evolution of deep levels in n-type 4H-SiC Schottky barrier diodes (SBDs) irradiated with 9.5 MeV/u 209Bi ions at room temperature was investigated by Deep Level Transient Spectroscopy (DLTS). DLTS scans from 40 K to 800 K indicated the presence of EN1, EHTi(h) (EC-0.13(1) eV), EH1(EC-0.48(2) eV), EH4 (EC-0.97(3)eV), and EH6/7 (EC-1.60(1) eV) defects levels within the energy range from 0.12 to 1.6 eV below the conduction band edge (EC). The DLTS results for the 4H-SiC SBD samples before and after irradiation clearly demonstrated that swift heavy ion (SHI) irradiation induced the evolution of deep level defects or defect states in 4H-SiC SBD device. Notably, at a fluence of 1 × 1011 ions/cm2, the ion-induced deep level defects or defect states exhibited significant recovery due to the cumulative effect of heat, leading to SiC re-crystallization.
{"title":"The evolution of defects in n-type 4H-SiC Schottky barrier diode irradiated with swift heavy ion using the Deep Level Transient Spectroscopy","authors":"Zhimei Yang , Yun Li , Mingmin Huang , Min Gong , Yao Ma","doi":"10.1016/j.microrel.2024.115532","DOIUrl":"10.1016/j.microrel.2024.115532","url":null,"abstract":"<div><div>The evolution of deep levels in n-type 4H-SiC Schottky barrier diodes (SBDs) irradiated with 9.5 MeV/u <sup>209</sup>Bi ions at room temperature was investigated by Deep Level Transient Spectroscopy (DLTS). DLTS scans from 40 K to 800 K indicated the presence of <em>EN</em><sub><em>1</em></sub><em>, EH</em><sub><em>Ti(h)</em></sub> (<em>E</em><sub><em>C</em></sub>-0.13(1) eV), <em>EH</em><sub><em>1</em></sub>(<em>E</em><sub><em>C</em></sub>-0.48(2) eV), <em>EH</em><sub><em>4</em></sub> (<em>E</em><sub><em>C</em></sub>-0.97(3)eV), and <em>EH</em><sub><em>6/7</em></sub> (<em>E</em><sub><em>C</em></sub><em>-</em>1.60(1) eV) defects levels within the energy range from 0.12 to 1.6 eV below the conduction band edge (<em>E</em><sub><em>C</em></sub>). The DLTS results for the 4H-SiC SBD samples before and after irradiation clearly demonstrated that swift heavy ion (SHI) irradiation induced the evolution of deep level defects or defect states in 4H-SiC SBD device. Notably, at a fluence of 1 × 10<sup>11</sup> ions/cm<sup>2</sup>, the ion-induced deep level defects or defect states exhibited significant recovery due to the cumulative effect of heat, leading to SiC re-crystallization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115532"},"PeriodicalIF":1.6,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142553762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-28DOI: 10.1016/j.microrel.2024.115528
Mohammad A. Gharaibeh , Jürgen Wilde
Finite element analysis (FEA) is a widely used technique for simulating the thermally induced mechanical behavior of die bonding materials in electronics. The Anand unified viscoplasticity model is commonly employed to simulate the mechanical responses of such interconnections. This model comprises nine parameters, the individual effects of which are not fully understood in the literature. This paper aims to investigate the impact of each Anand parameter on the mechanical response of sintered silver (Ag) bonds through extensive finite element simulations. Various Anand models for sintered Ag, sourced from literature, are utilized to create a systematic study matrix for each parameter. These material coefficients are then incorporated into thermal and thermomechanical simulations to induce inelastic deformations in the sintered Ag bonds. The bonding layer response is analyzed in terms of stress-strain relationships, inelastic strains, and inelastic strain energy density. The results indicated that certain Anand parameters could cause the bond response to shift towards brittle behavior, while others could result in a more ductile behavior. Using statistical factorial analysis, it is found that the significance of each parameter varied greatly, from negligible to highly significant. The findings of this study are valuable for understanding the behavior of various bonds configurations and their expected thermal fatigue performance based on their Anand creep constants. Additionally, this paper lays the groundwork for understanding the meaning of Anand constants and their influence on the mechanical response of any bond material which is not discussed in literature yet.
{"title":"The variation in Anand model parameters – How does that affect the bond's response? A comparative study considering sintered Ag bonds","authors":"Mohammad A. Gharaibeh , Jürgen Wilde","doi":"10.1016/j.microrel.2024.115528","DOIUrl":"10.1016/j.microrel.2024.115528","url":null,"abstract":"<div><div>Finite element analysis (FEA) is a widely used technique for simulating the thermally induced mechanical behavior of die bonding materials in electronics. The Anand unified viscoplasticity model is commonly employed to simulate the mechanical responses of such interconnections. This model comprises nine parameters, the individual effects of which are not fully understood in the literature. This paper aims to investigate the impact of each Anand parameter on the mechanical response of sintered silver (Ag) bonds through extensive finite element simulations. Various Anand models for sintered Ag, sourced from literature, are utilized to create a systematic study matrix for each parameter. These material coefficients are then incorporated into thermal and thermomechanical simulations to induce inelastic deformations in the sintered Ag bonds. The bonding layer response is analyzed in terms of stress-strain relationships, inelastic strains, and inelastic strain energy density. The results indicated that certain Anand parameters could cause the bond response to shift towards brittle behavior, while others could result in a more ductile behavior. Using statistical factorial analysis, it is found that the significance of each parameter varied greatly, from negligible to highly significant. The findings of this study are valuable for understanding the behavior of various bonds configurations and their expected thermal fatigue performance based on their Anand creep constants. Additionally, this paper lays the groundwork for understanding the meaning of Anand constants and their influence on the mechanical response of any bond material which is not discussed in literature yet.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115528"},"PeriodicalIF":1.6,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The 2.5D packaging technology is a high–performance method for electronic packaging. This study addresses the reliability issues of 2.5D packaging during the manufacturing process. A multi–physics field coupling Finite Element Method (FEM) has been developed, combined with sub–modeling techniques, to investigate the curing of underfill adhesive, the curing of Epoxy Molding Compound (EMC), and the reflow soldering between the interposer and substrate in a 2.5D packaging entity during various manufacturing procedures. The focus is on the thermo–mechanical–chemical behavior of viscoelastic components within the packaging structure, as well as the viscoplastic characteristics of the micro solder balls and microbumps. A systematic analysis is conducted on the warpage deformation and stress distribution of the 2.5D packaging at crucial time points. The results demonstrate that after curing, the overall warpage of the packaging exhibits a ‘concave’ warpage profile. Additionally, as the thickness of the EMC above the chip increases, the warpage value of the packaging also increases. The warpage value defined by linear elasticity is larger than that defined by viscoelasticity. The maximum Von Mises stress value in the key areas of the submodel is greater than the maximum Von Mises stress value in the corresponding key areas of the global model. After reflow soldering, the stress concentration in the micro solder balls occurs at the edge of the micro solder ball array. The maximum stress values for each component of the packaging are observed in the interface areas between the components. Packaging components that undergo the curing process have notably higher warpage and Von Mises stress values than those that do not undergo the curing process. The simulation method established in this study can accurately predict the warpage deformation and stress distribution state of 2.5D packaging, providing significant engineering application value for process optimization and reliability enhancement of 2.5D packaging in the production process.
2.5D 封装技术是一种高性能的电子封装方法。本研究探讨了 2.5D 封装在制造过程中的可靠性问题。研究人员开发了一种多物理场耦合有限元法（FEM），并结合子建模技术，以研究 2.5D 封装实体在各种制造过程中的底部填充粘合剂固化、环氧树脂模塑料固化以及中间件与基板之间的回流焊接。重点是封装结构中粘弹性成分的热机械化学行为，以及微焊球和微凸点的粘弹性特征。对 2.5D 封装在关键时间点的翘曲变形和应力分布进行了系统分析。结果表明，固化后，封装的整体翘曲呈现出 "凹 "形翘曲曲线。此外，随着芯片上方 EMC 厚度的增加，封装的翘曲值也会增加。线性弹性定义的翘曲值大于粘弹性定义的翘曲值。子模型关键区域的最大 Von Mises 应力值大于全局模型相应关键区域的最大 Von Mises 应力值。回流焊接后，微焊球的应力集中发生在微焊球阵列的边缘。包装中每个元件的最大应力值都出现在元件之间的界面区域。经历固化过程的封装元件的翘曲和 Von Mises 应力值明显高于未经历固化过程的元件。本研究建立的模拟方法可以准确预测 2.5D 包装的翘曲变形和应力分布状态，为 2.5D 包装在生产过程中的工艺优化和可靠性提升提供了重要的工程应用价值。
{"title":"Finite element analysis of 2.5D packaging processes based on multi-physics field coupling for predicting the reliability of IC components","authors":"Wenqian Li, Xinda Wang, Ruiqian Zheng, Xiaohui Zhao, Hao Zheng, Zhiyan Zhao, Mengxuan Cheng, Yong Jiang, Yuxi Jia","doi":"10.1016/j.microrel.2024.115530","DOIUrl":"10.1016/j.microrel.2024.115530","url":null,"abstract":"<div><div>The 2.5D packaging technology is a high–performance method for electronic packaging. This study addresses the reliability issues of 2.5D packaging during the manufacturing process. A multi–physics field coupling Finite Element Method (FEM) has been developed, combined with sub–modeling techniques, to investigate the curing of underfill adhesive, the curing of Epoxy Molding Compound (EMC), and the reflow soldering between the interposer and substrate in a 2.5D packaging entity during various manufacturing procedures. The focus is on the thermo–mechanical–chemical behavior of viscoelastic components within the packaging structure, as well as the viscoplastic characteristics of the micro solder balls and microbumps. A systematic analysis is conducted on the warpage deformation and stress distribution of the 2.5D packaging at crucial time points. The results demonstrate that after curing, the overall warpage of the packaging exhibits a ‘concave’ warpage profile. Additionally, as the thickness of the EMC above the chip increases, the warpage value of the packaging also increases. The warpage value defined by linear elasticity is larger than that defined by viscoelasticity. The maximum Von Mises stress value in the key areas of the submodel is greater than the maximum Von Mises stress value in the corresponding key areas of the global model. After reflow soldering, the stress concentration in the micro solder balls occurs at the edge of the micro solder ball array. The maximum stress values for each component of the packaging are observed in the interface areas between the components. Packaging components that undergo the curing process have notably higher warpage and Von Mises stress values than those that do not undergo the curing process. The simulation method established in this study can accurately predict the warpage deformation and stress distribution state of 2.5D packaging, providing significant engineering application value for process optimization and reliability enhancement of 2.5D packaging in the production process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115530"},"PeriodicalIF":1.6,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-24DOI: 10.1016/j.microrel.2024.115527
Hanwen Ren , Siyang Zhao , Jian Mu , Wei Wang , Wanshui Yu , Feng Wang , Zhiyun Han , Zhihui Li , Qingmin Li , Jian Wang
As the key package structure of insulated gate bipolar transistor (IGBT), the bond wire and solder layer are susceptible to failure due to alternating thermal stress, which can seriously change the operating characteristics of the package structure. In this paper, an electrical-thermal-mechanical multi-physical field coupling simulation model of IGBT including the fine bond wire and solder layer structure is constructed, whose equivalence and accuracy are verified by experiments and characteristic curves. Based on the constructed healthy model, the simulation results find that the fourth bond wire at the center location shows the highest temperature of 38.7 °C and the maximum mechanical stress of 55.5 MPa. Subsequently, the researches on single-structure failure and dual-structure simultaneous failure are carried out. The results show that bond wire failure only significantly affects its own operating characteristics, while solder layer failure affects itself and bond wire simultaneously. Moreover, the temperature rise due to the bond wire failure is more significant with an 86.8 % increase, while the mechanical stress change due to the solder layer failure is larger with a 178.2 % increase. The research in this paper can guide the reliability improvement of IGBT and the optimization of IGBT package structure.
{"title":"Research on the multi-physical field coupling modelling of IGBT package module and the effect of different structure failure interaction","authors":"Hanwen Ren , Siyang Zhao , Jian Mu , Wei Wang , Wanshui Yu , Feng Wang , Zhiyun Han , Zhihui Li , Qingmin Li , Jian Wang","doi":"10.1016/j.microrel.2024.115527","DOIUrl":"10.1016/j.microrel.2024.115527","url":null,"abstract":"<div><div>As the key package structure of insulated gate bipolar transistor (IGBT), the bond wire and solder layer are susceptible to failure due to alternating thermal stress, which can seriously change the operating characteristics of the package structure. In this paper, an electrical-thermal-mechanical multi-physical field coupling simulation model of IGBT including the fine bond wire and solder layer structure is constructed, whose equivalence and accuracy are verified by experiments and characteristic curves. Based on the constructed healthy model, the simulation results find that the fourth bond wire at the center location shows the highest temperature of 38.7 °C and the maximum mechanical stress of 55.5 MPa. Subsequently, the researches on single-structure failure and dual-structure simultaneous failure are carried out. The results show that bond wire failure only significantly affects its own operating characteristics, while solder layer failure affects itself and bond wire simultaneously. Moreover, the temperature rise due to the bond wire failure is more significant with an 86.8 % increase, while the mechanical stress change due to the solder layer failure is larger with a 178.2 % increase. The research in this paper can guide the reliability improvement of IGBT and the optimization of IGBT package structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115527"},"PeriodicalIF":1.6,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1016/j.microrel.2024.115522
Preethi Elizabeth Iype , V. Suresh Babu , Geenu Paul
High electron mobility transistors (HEMTs) based on a wider bandgap AlGaN channel prove more efficient for high-voltage operation. The significant advantages of AlGaN channel HEMTs include a high critical electric field and higher saturation velocity. These characteristics contribute substantially to expanding the operating regime of power electronics, making them more suitable for applications requiring high voltage. This research work introduces a novel structure for a HEMT based on AlGaN/GaN with a recessed Gamma (Γ)-gate. The proposed HEMTs are composed of a 30 nm supply/barrier layer and an 18 nm channel layer, constructed on a Beta Gallium Oxide (BGO) substrate. Additionally, a delta-doped layer is incorporated to enhance device characteristics. The Direct Current (DC) features of the introduced scheme are compared with those of Γ-gate, rectangular and T-gate configurations, and analyzed using Silvaco TCAD software under various considerations. Key parameters including threshold voltage and transconductance are extracted from the DC characteristics. The proposed device provides a comparable cut-off frequency of 998 GHz for 20 nm gate length. Finally, the thermal efficiency of the introduced scheme, utilizing lateral lattice thermal conductivity, results in peak temperatures of 398.2 K, demonstrating superior performance compared to existing gate structures. The optimized performance of the device is assessed against existing devices, demonstrating its superiority among the compared schemes.
{"title":"Investigation of thermal efficiency of recessed Γ gate over Γ gate, T gate and rectangular gate AlGaN/GaN HEMT on BGO substrate","authors":"Preethi Elizabeth Iype , V. Suresh Babu , Geenu Paul","doi":"10.1016/j.microrel.2024.115522","DOIUrl":"10.1016/j.microrel.2024.115522","url":null,"abstract":"<div><div>High electron mobility transistors (HEMTs) based on a wider bandgap AlGaN channel prove more efficient for high-voltage operation. The significant advantages of AlGaN channel HEMTs include a high critical electric field and higher saturation velocity. These characteristics contribute substantially to expanding the operating regime of power electronics, making them more suitable for applications requiring high voltage. This research work introduces a novel structure for a HEMT based on AlGaN/GaN with a recessed Gamma (Γ)-gate. The proposed HEMTs are composed of a 30 nm supply/barrier layer and an 18 nm channel layer, constructed on a Beta Gallium Oxide (BGO) substrate. Additionally, a delta-doped layer is incorporated to enhance device characteristics. The Direct Current (DC) features of the introduced scheme are compared with those of Γ-gate, rectangular and T-gate configurations, and analyzed using Silvaco TCAD software under various considerations. Key parameters including threshold voltage and transconductance are extracted from the DC characteristics. The proposed device provides a comparable cut-off frequency of 998 GHz for 20 nm gate length. Finally, the thermal efficiency of the introduced scheme, utilizing lateral lattice thermal conductivity, results in peak temperatures of 398.2 K, demonstrating superior performance compared to existing gate structures. The optimized performance of the device is assessed against existing devices, demonstrating its superiority among the compared schemes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115522"},"PeriodicalIF":1.6,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Insulated-gate bipolar transistor (IGBT) modules are extensively utilized in high-speed trains, ships, and electric vehicles. Compared to those used in power systems, IGBT modules in these applications are more susceptible to vibration effects on their reliability. This paper proposes a multi-physics field simulation method and a lifetime model for IGBT modules to assess the impact of different vibration directions on solder layer fatigue. Initially, a multi-physics field model of the IGBT module is developed, incorporating electrical, thermal, mechanical, and vibration coupling. The effectiveness of this multi-physics simulation model is verified by an experimental platform. Subsequently, the influence of different vibration directions on solder layer fatigue in the IGBT module is analysed, and a life model of the IGBT is proposed through simulation. Finally, a power cycling with a vibration environment experimental platform is established to validate the effect of vibration on solder layer fatigue in the IGBT module. The simulation and experimental results indicate that vertical vibration accelerates the solder layer fatigue of IGBT modules, and the lifetime of an IGBT module operating under vertical vibration at 30 Hz is about 15 % shorter than that of an IGBT module operating under power cycling alone. The error between the calculated results of the solder layer failure and the experimental result is <5 %.
{"title":"Influence of different vibration directions on the solder layer fatigue in IGBT modules","authors":"Yifan Jian, Shinian Peng, Zhi Chen, Zhengxi He, Liang He, Xinzhi Lv","doi":"10.1016/j.microrel.2024.115526","DOIUrl":"10.1016/j.microrel.2024.115526","url":null,"abstract":"<div><div>Insulated-gate bipolar transistor (IGBT) modules are extensively utilized in high-speed trains, ships, and electric vehicles. Compared to those used in power systems, IGBT modules in these applications are more susceptible to vibration effects on their reliability. This paper proposes a multi-physics field simulation method and a lifetime model for IGBT modules to assess the impact of different vibration directions on solder layer fatigue. Initially, a multi-physics field model of the IGBT module is developed, incorporating electrical, thermal, mechanical, and vibration coupling. The effectiveness of this multi-physics simulation model is verified by an experimental platform. Subsequently, the influence of different vibration directions on solder layer fatigue in the IGBT module is analysed, and a life model of the IGBT is proposed through simulation. Finally, a power cycling with a vibration environment experimental platform is established to validate the effect of vibration on solder layer fatigue in the IGBT module. The simulation and experimental results indicate that vertical vibration accelerates the solder layer fatigue of IGBT modules, and the lifetime of an IGBT module operating under vertical vibration at 30 Hz is about 15 % shorter than that of an IGBT module operating under power cycling alone. The error between the calculated results of the solder layer failure and the experimental result is <5 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115526"},"PeriodicalIF":1.6,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-21DOI: 10.1016/j.microrel.2024.115525
Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai
When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.
{"title":"A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure","authors":"Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai","doi":"10.1016/j.microrel.2024.115525","DOIUrl":"10.1016/j.microrel.2024.115525","url":null,"abstract":"<div><div>When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115525"},"PeriodicalIF":1.6,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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