Microelectronics Reliability最新文献

{"title":"Design of single ended 9T SRAM cell with improved read performance and expanded write margin for aerospace applications","authors":"Saloni Bansal,&nbsp;V.K. Tomar","doi":"10.1016/j.microrel.2026.115998","DOIUrl":"10.1016/j.microrel.2026.115998","url":null,"abstract":"<div><div>Space radiation including photons, heavy ions, neutrons and α-particles poses significant challenges to the stability and reliability of memory circuits. These high-energy particles can penetrate into the semiconductor materials and interact causing charge deposition and ionization tracks that can lead to data corruption, soft errors, or even permanent failures in extreme cases. As transistor sizes shrink, the integration density of the memory circuits, such as static random-access memory (SRAM) cells increase, making them more susceptible to single-event upsets (SEUs). 6T SRAM cell is more prone to soft errors, where unintended bit flip can occur due to external radiation, resulting in potential reliability issues during memory operations. To mitigate such issues, this paper proposed, a novel radiation hardened 9T SRAM cell to improve soft error rate. The performance of the proposed 9T SRAM cell is evaluated at 45 nm technology node and compared with previously reported SRAM cells, such as 6T, TA8T, 9T, 11T, 10T, 12T, WFC12T, GRNFET9T and PNT9T SRAM cell configurations across a range of supply voltages from 0.5V to 1V. The proposed 9T SRAM cell operates in a single-ended read and write mode and enabling efficient read and write operations. Its read stability shows an improvement by 1.96×/1.83×/1.02×/1.91×/1.02×/1.01×/2.06×/1.43× as compared to conventional 6T, TA8T, 9T, 11T,10T, WFC12T, GRNFET9T and PNT9T SRAM cells, respectively, at 1 V supply voltage. The critical charge in proposed 9T SRAM cell is 2.5×/2.35×/1.14×/1.33×/1.19×/1.08×/2.47×/1.11×/1.11× improved as compared to 6T/TA8T/9T/11T/10T/12T/WFC12T/GRNFET9T/PNT9T SRAM cells. In addition to this, proposed 9T cell has 1.13×/1.06×/1.95×/1.20×/1.04×/1.04×/1.12×/1.05×1.20× less read access time than conv.6T/TA8T/9T/11T/10T/12T/WFC12T GRNFET9T/PNT9T SRAM cells.</div><div>Moreover, I_on/I_off ratio in proposed 9T SRAM cell is 3.0×/2.98×/4.26×/3.01×/3.21×/1.13×/3.2×/3.0×/3.42× higher than conv.6T/TA8T/9T/11T/10T/12T/WFC12T/GRNFET9T/PNT9T SRAM cells. The Monte Carlo simulation is conducted with 4000 random samples to analyze the impact of process variations on read power and read current. The overall performance and soft-error resilience of the proposed 9T SRAM cell are investigated with the ratio of reliability and stability to energy product (RSEAP). This highest RSEAP value of proposed 9T SRAM cell makes its suitability for aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 115998"},"PeriodicalIF":1.9,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermally cycling-stable and highly heat-dissipative BGA packages manufactured by fluxless laser soldering: Experimental and numerical investigations","authors":"Dongjin Kim ,&nbsp;Seonghui Han ,&nbsp;Junha Baik ,&nbsp;Junwoo Park ,&nbsp;Ha-Young Yu ,&nbsp;Kwansik Chung ,&nbsp;Eunchae Kim ,&nbsp;Sehoon Yoo","doi":"10.1016/j.microrel.2026.116018","DOIUrl":"10.1016/j.microrel.2026.116018","url":null,"abstract":"<div><div>This study developed the flux-less solder ball (i.e., Sn-3wt%Ag-0.5wt%Cu) attachment technology (FLAT), a novel and eco-friendly approach that eliminates flux processing during mass reflow while significantly reducing the warpages. Furthermore, the ball grid array (BGA) package applied with FLAT was directly compared with the BGA package manufactured by the conventional mass reflow manufacturing method in terms of thermal cycling reliability. As a result, FLAT made an intermetallic compound (IMC) of less than 1.6 μm at bonding interfaces by an instantaneous laser heat source, and solidified immediately after nucleation, forming a solder ball composed of uniform and fine beta-Sn. In contrast, the conventional mass reflow soldering using flux has caused the formation of massive Cu₆Sn₅ chunks inside the BGA package, and even the thickness of the IMC at the bonding interface with the pad exceeded 4.8 μm. The interfacial IMC layer suppressed by FLAT suppressed the spalling phenomenon during the continuous thermal cycling tests. In contrast, the interfacial IMC layer formed by the conventional mass reflow process had a relatively long aspect ratio, which promoted interdiffusion with the Sn matrix during thermal cycling, allowing the spalling of a large amount of Cu₆Sn₅ chunks into the Sn matrix. This distinguished behavior explains the distinct pros and cons of the two processes in thermal shock resistance, which determines the rigidity and heat dissipation properties within the solder. This study systematically addresses the thermal cycling behaviors of BGA packages manufactured by FLAT and MR, and heat transfer performances originated from this IMC growth behavior through numerical calculation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116018"},"PeriodicalIF":1.9,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of multiple AI models for failure classification in smart plug top case study","authors":"M.L. Hoang ,&nbsp;S. Daniele ,&nbsp;N. Delmonte ,&nbsp;M. Dal Re ,&nbsp;P. Cova ,&nbsp;D. Santoro","doi":"10.1016/j.microrel.2026.116019","DOIUrl":"10.1016/j.microrel.2026.116019","url":null,"abstract":"<div><div>Smart plug tops (SPTs) with sensing capabilities are increasingly important for real-time monitoring and diagnostics in internal combustion engines. However, the deployment of numerous electronic devices and the increasing system complexity can lead to multiple types of failures that must be accurately investigated and categorized. This research presents a machine learning (ML) based approach for the categorization and prediction of various failure modes occurring in SPTs. The method involves systematic collection of sensor data during the testing phase of SPTs, which is then linked to failures identified through lifetime analysis. The ML model is trained using relevant features extracted from the acquired data, such as voltage levels, charge times, current levels, and other electrical parameters characterizing the SPT's operating behavior. The model is refined using a training and validation method to accurately predict various types of failures, such as electric discharge on the transformer secondary winding, damping diode breakdown, and short circuits between windings. A major challenge addressed in this work is the limited number of failure samples, since the device predominantly operates under normal conditions and only occasionally exhibits faulty behavior. Hence, an upsampling technique was applied to improve this imbalanced dataset. Various Artificial Intelligence (AI) models, including Machine Learning and Deep Learning were compared with each other to find out the most appropriate one for this particular case. The best classification algorithm achieves high accuracy along with good precision, recall, and F1-score on the test data. The results demonstrate the potential of ML-based analysis to enable the early identification of problem symptoms during acceptance testing and to provide a probabilistic classification of different failure types, thereby supporting predictive maintenance and reliability assessment of SPTs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116019"},"PeriodicalIF":1.9,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of single event effects in full-customized modules for clock and data recovery circuits in 16 Gbps SerDes","authors":"Yahao Fang,&nbsp;Jianjun Chen,&nbsp;Bin Liang,&nbsp;Yaqing Chi,&nbsp;Deng Luo,&nbsp;Hanhan Sun,&nbsp;Qian Sun,&nbsp;Bo Yu","doi":"10.1016/j.microrel.2026.116011","DOIUrl":"10.1016/j.microrel.2026.116011","url":null,"abstract":"<div><div>Single event effects are investigated through heavy-ion experiments and laser experiments on full-customized modules for clock and data recovery circuits in 16 Gbps Serializer/Deserializer (SerDes). The experimental results show that the BER is highly susceptible to single event effects. Laser experiments identified several sensitive points, all located within the Voltage-Controlled Oscillator (VCO). The results of the study provide theoretical guidance for the future targeted hardened design of full-customized modules.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116011"},"PeriodicalIF":1.9,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Standardized test method for pure bending evaluation of foldable display materials under natural-arc folding","authors":"S.Y. Lim ,&nbsp;I.H. Cho ,&nbsp;H.R. Hwang ,&nbsp;U.H. Jeong","doi":"10.1016/j.microrel.2026.116016","DOIUrl":"10.1016/j.microrel.2026.116016","url":null,"abstract":"<div><div>With the growing market for foldable displays, there is an increasing demand for standardized test methods to evaluate the bending characteristics of foldable materials. This study analyzed the mechanical principles of the folding mechanisms in commercial foldable displays, thereby focusing on the tension-free folding paths that minimize unnecessary stress during material evaluation. Using theoretical analysis and finite element modeling, we investigated various testing scenarios and their impact on the material stress distribution thereby revealing that a natural-arc folding mechanism with appropriate specimen mounting provide more reliable conditions for evaluating the pure bending characteristics. Further, these findings suggest that thickness-adjusted bottom-mounting methods improve consistency by accurately simulating the ideal folding conditions. This study contributes to the development of standardized testing approaches for foldable display materials, while acknowledging existing industrial practices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116016"},"PeriodicalIF":1.9,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive assessment of dynamic and static performance of SiC MOSFETs under highly accelerated power cycling conditions","authors":"Xinyu Zhu ,&nbsp;Yuan Chen ,&nbsp;Pengkai Wang ,&nbsp;Hu He","doi":"10.1016/j.microrel.2026.116012","DOIUrl":"10.1016/j.microrel.2026.116012","url":null,"abstract":"<div><div>The Power Cycling Tests (PCT) constitute a critical method for assessing the long-term reliability of SiC MOSFETs. Existing studies have primarily focused on the degradation of static characteristic, which are typically measured after the device is interrupted from normal operation, thereby precluding the real-time monitoring of the aging process. Given the widespread use of SiC MOSFETs in circuit switching, investigating the degradation of their dynamic characteristics is essential for accurately simulating actual performance. This study comprehensively evaluates the changes in the dynamic and static characteristics of devices before and after PCT, encompassing the variations of gate leakage current, drain leakage current, threshold voltage, on-resistance, and junction capacitances (<em>C</em>_<em>iss</em>, <em>C</em>_<em>oss</em>, and <em>C</em>_<em>rss</em>), as well as switching parameters and turn-on waveforms, to analyze the degradation mechanisms. Additionally, the analysis of capacitances variations facilitated the investigation into charge injection into the gate oxide layer. The findings offer new insights into early indicators of device degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116012"},"PeriodicalIF":1.9,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A BiLSTM-based digital twin model for photovoltaic strings under current mismatch condition","authors":"Yihan Chen ,&nbsp;Mingyao Ma ,&nbsp;Wenting Ma ,&nbsp;Rui Zhang ,&nbsp;Zhenyu Fang","doi":"10.1016/j.microrel.2026.116020","DOIUrl":"10.1016/j.microrel.2026.116020","url":null,"abstract":"<div><div>The reliability of photovoltaic (PV) systems is increasingly challenged by string-level faults affecting both performance and safety. To address this issue, this study proposes a four-layer digital twin (DT) framework for intelligent monitoring and fault diagnosis of PV strings under mismatch conditions. In the virtual layer, the Sandia Array Performance Model and the Perez model are employed to estimate module temperature and plane-of-array irradiance, which are then input into a bidirectional long short-term memory (BiLSTM) network for current prediction. To enhance adaptability, a solar-elevation-based Current Mismatch Ratio (CMR) is introduced as an auxiliary correction factor, enabling dynamic modeling of mismatch behavior. The CMR-assisted BiLSTM achieves a root mean square error (RMSE) of 0.4306 and a coefficient of determination (<span><math><msup><mrow><mi>R</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span>) of 0.9594, demonstrating high predictive accuracy. In the decision layer, a sliding-window mechanism combined with a support vector machine classifier distinguishes bypass diode short-circuit faults from mismatch phenomena using statistical features of <span><math><msup><mrow><mi>R</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span> and RMSE. Validation based on operational data from actual PV power plants shows that the proposed DT-based approach achieves an accuracy of 96.76%, precision of 93.39%, recall of 97.96%, and an F1-score of 95.63%, outperforming traditional reference string–based methods by 1.22%, 3.12%, and 1.59% in accuracy, precision, and F1-score, respectively. These results confirm that the proposed DT framework provides real-time fault diagnosis and predictive maintenance, significantly improving the operational reliability of PV systems under dynamic environmental conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116020"},"PeriodicalIF":1.9,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145993604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Local stress distribution in sintered nanoporous silver films under mechanical and thermal loading","authors":"Kokouvi Happy N'Tsouaglo ,&nbsp;Loic Signor ,&nbsp;Jérôme Colin ,&nbsp;Xavier Milhet","doi":"10.1016/j.microrel.2026.116009","DOIUrl":"10.1016/j.microrel.2026.116009","url":null,"abstract":"<div><div>The sintering process of silver paste has attracted increasing attention in electronic packaging due to its exceptional bonding quality and ability to withstand high operating temperatures. However, industrial constraints often lead to conditions that result in a porous microstructure after sintering, which adversely affects material properties, particularly during aging. In this study, we investigate both the global and local elastic response of sintered Ag (s-Ag) porous structures under mechanical and thermal loading. Two types of three-dimensional (3D) microstructures are considered: real microstructures obtained from serial block-face scanning electron microscopy, and synthetic ones generated by random placement of overlapping spheres. In addition, a realistic tri-layer Cu/s-Ag/Cu assembly is analyzed to simulate conditions encountered in power modules. Full-field numerical simulations were conducted using the finite element method. For the porous microstructures examined, the macroscopic elastic behavior of s-Ag, which exhibits quasi-isotropy, is found to primarily depend only on the pore volume fraction. Local stresses in Ag matrix due to an applied mechanical loading, as well as thermal stresses due to a temperature increase in sintered Ag-Cu assembly, show a high spatial heterogeneity. Maximal stress level can reach about twice the mean value. Even though these areas of stress concentration depend strongly on the specific pores cluster, conversely, for a given pore volume fraction, the stress probability distribution is weakly influenced by the details of the nanoporous structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116009"},"PeriodicalIF":1.9,"publicationDate":"2026-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance evaluation of InN-based Junctionless FETs under single and double gate architectures","authors":"Swati Verma ,&nbsp;Pushpa Raikwal ,&nbsp;Neeraj K. Jaiswal","doi":"10.1016/j.microrel.2026.116014","DOIUrl":"10.1016/j.microrel.2026.116014","url":null,"abstract":"<div><div>In this manuscript for the first time we incorporated the indium nitride (InN) in junctionless field effect transistor (JLFET) after investigating its electronic behavior and transport properties. The purpose of the investigation is to overcome the limitation of conventional Si-based device. Owing to its properties like varied bandgap (0.66 eV–1.34 eV) obtained via passivation technique, high electron mobility, large saturation velocity and comparatively less effective mass. InN offers excellent transport properties and enables improved drive current. The performance evaluation of diverse gate architecture i.e. single and double gate of InN-based JLFET. The InN-SGJLFET structure demonstrates simplicity and reduced fabrication complexity, but it suffers from limited gate control. In contrast, the InN-DGJLFET provides superior electrostatic integrity by enhancing gate channel coupling. The 2-D simulation of single and double gate InN-based JLFET, when compared with conventional Si-JLFET exhibits: (1) high <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span>/<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>F</mi><mi>F</mi></mrow></msub></math></span> current ratio of <span><math><mrow><mo>≈</mo><mspace></mspace><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>7</mn></mrow></msup></mrow></math></span>; (2) Low OFF-state current <span><math><mrow><mo>≈</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>11</mn></mrow></msup><mi>A</mi><mo>/</mo><mi>μ</mi><mi>m</mi></mrow></math></span>; and (3) Better subthreshold swing (SS) (<span><math><mo>≈</mo></math></span>62.17 mV/decade) for InN-DGJLFET. The figure of merit of the device like ON-current (<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span>), OFF-current (<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>F</mi><mi>F</mi></mrow></msub></math></span>), ON-OFF current ratio, SS and drain-induced barrier lowering (DIBL) have been evaluated. The comparative analysis highlights that InN-DGJLFETs is more suitable for sub-10-nm regime devices, where strong electrostatic gate control is crucial for balancing the operation and power efficiency. Further, the comparative study of process variation is performed on considered devices. These findings suggest that InN-based JLFETs, particularly in multi-gate configuration, can serve as promising candidates for next-generation ultra-scaled low-power electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116014"},"PeriodicalIF":1.9,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146038224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"In-depth 2D FEM analysis of gate cracking in SiC MOSFETs under repetitive short-circuit conditions: Application of a damage-based model for crack length prediction","authors":"Mustafa Shqair,&nbsp;Emmanuel Sarraute,&nbsp;Frédéric Richardeau","doi":"10.1016/j.microrel.2026.116005","DOIUrl":"10.1016/j.microrel.2026.116005","url":null,"abstract":"<div><div>An advanced structural and physical model of Intermediate Layer Dielectric (ILD) cracking in a planar gate under short-circuit (SC) conditions has been developed as a continuation of our previous studies. This approach utilizes an energy-based Rankine damage model, which is applied based on the mechanical properties of SiO₂. The Rankine model has been seamlessly integrated into a comprehensive 2D electrothermal-metallurgical and elastoplastic-mechanical framework, which accounts for both the high-temperature rise and its return to its reference value during the cooling phase. In a novel approach, multiple repetitive mechanical cycles were simulated to evaluate the progression and rate of crack penetration, with variations in parameters such as pulse duration and damage model coefficients. This model illustrated the evolution of crack formation and direction during cycling, in alignment with the crack progression observed experimentally in microsections.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 116005"},"PeriodicalIF":1.9,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}