Pub Date : 2026-01-06DOI: 10.1016/j.microrel.2026.115997
Rodrigo Drummond, Bernardo Cougo, Duc-Hoan Tran
Significant temperature variation in frequencies from 10 to 100 Hz was observed in SiC dies used in inverter and rectifier applications. These fast thermal cycles can significantly reduce SiC power module lifetimes. This paper presents an approach and testbench to investigate module aging due to these cycles. The testbench creates die temperature variations up to 40 K at 10 to 100 Hz. The power module is stressed as in a real inverter or rectifier, maintaining the same average temperature and power cycles at the frequency of sinusoidal current. Thermal cycle amplitudes are selected using accurate thermoelectrical model of the dies. This model is obtained via Modified Opposition Method for switching and conduction losses of SiC dies and a fast thermal camera for dynamic temperature measurements and estimation of self and mutual thermal impedance of the dies. Experimental results demonstrate that the algorithm accurately imposes the desired high-frequency power cycles in SiC inside power module.
{"title":"Application-representative high-frequency power cycling of SiC power modules used in inverters and rectifiers","authors":"Rodrigo Drummond, Bernardo Cougo, Duc-Hoan Tran","doi":"10.1016/j.microrel.2026.115997","DOIUrl":"10.1016/j.microrel.2026.115997","url":null,"abstract":"<div><div>Significant temperature variation in frequencies from 10 to 100 Hz was observed in SiC dies used in inverter and rectifier applications. These fast thermal cycles can significantly reduce SiC power module lifetimes. This paper presents an approach and testbench to investigate module aging due to these cycles. The testbench creates die temperature variations up to 40 K at 10 to 100 Hz. The power module is stressed as in a real inverter or rectifier, maintaining the same average temperature and power cycles at the frequency of sinusoidal current. Thermal cycle amplitudes are selected using accurate thermoelectrical model of the dies. This model is obtained via Modified Opposition Method for switching and conduction losses of SiC dies and a fast thermal camera for dynamic temperature measurements and estimation of self and mutual thermal impedance of the dies. Experimental results demonstrate that the algorithm accurately imposes the desired high-frequency power cycles in SiC inside power module.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115997"},"PeriodicalIF":1.9,"publicationDate":"2026-01-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-05DOI: 10.1016/j.microrel.2025.115992
Ge Shi , Zhong Jun Yu , Zheng Xu , Xing Yao Zeng , Yan Wei Dai , Fei Qin , Hai Bo Zhang
System-in-package (SiP) technology utilizing low temperature cofired ceramic substrates (LTCC-SiP) offer millimeter-wave components higher integration density and superior radio frequency (RF) performance. However, the thermal management challenges of LTCC-SiP require urgent resolution due to the low thermal conductivity of LTCC materials and the increasingly high thermal dissipation demands of power amplifier (PA) chips. To better address this situation, this study investigates the thermal performance of LTCC-SiP through heat transfer and computational fluid dynamics (CFD) analyses. The research focuses on: (1) determining the equivalent thermal conductivity of LTCC substrates with varying filler diameters, pitches, aspect ratios, as well as different conductor and ground grid distributions; (2) evaluating the junction temperature and thermal resistance of SiP structures incorporating LTCC substrates, considering factors such as chip area ratio, chip thickness, frame and LTCC cavity/substrate heights, frame width, frame material, cavity potting material, and the presence of liquid-cooled channels in the cover; and (3) assessing the junction temperature and thermal resistance in three-dimensional stacking configurations with LTCC substrates. Research findings indicate that the thermal performance of LTCC-SiP can be enhanced through multiple methodologies. Furthermore, the findings are synthesized into practical design charts and guidelines to facilitate engineering applications.
{"title":"Structural optimization design of LTCC substrate and their impacts on thermal performances of system-in-package","authors":"Ge Shi , Zhong Jun Yu , Zheng Xu , Xing Yao Zeng , Yan Wei Dai , Fei Qin , Hai Bo Zhang","doi":"10.1016/j.microrel.2025.115992","DOIUrl":"10.1016/j.microrel.2025.115992","url":null,"abstract":"<div><div>System-in-package (SiP) technology utilizing low temperature cofired ceramic substrates (LTCC-SiP) offer millimeter-wave components higher integration density and superior radio frequency (RF) performance. However, the thermal management challenges of LTCC-SiP require urgent resolution due to the low thermal conductivity of LTCC materials and the increasingly high thermal dissipation demands of power amplifier (PA) chips. To better address this situation, this study investigates the thermal performance of LTCC-SiP through heat transfer and computational fluid dynamics (CFD) analyses. The research focuses on: (1) determining the equivalent thermal conductivity of LTCC substrates with varying filler diameters, pitches, aspect ratios, as well as different conductor and ground grid distributions; (2) evaluating the junction temperature and thermal resistance of SiP structures incorporating LTCC substrates, considering factors such as chip area ratio, chip thickness, frame and LTCC cavity/substrate heights, frame width, frame material, cavity potting material, and the presence of liquid-cooled channels in the cover; and (3) assessing the junction temperature and thermal resistance in three-dimensional stacking configurations with LTCC substrates. Research findings indicate that the thermal performance of LTCC-SiP can be enhanced through multiple methodologies. Furthermore, the findings are synthesized into practical design charts and guidelines to facilitate engineering applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115992"},"PeriodicalIF":1.9,"publicationDate":"2026-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1016/j.microrel.2025.115993
Xinyu Wang , Osama Awadelkarim
We report on the electrical stress reliability of gamma (γ) irradiated Si- and SiC-MOSFETs and their thermal annealing. The MOSFETs were irradiated by a Cobalt-60 (Co-60) source for up to 2 Mega Rad. The irradiation was followed by positive- or negative-polarity DC electrical stress and thermal annealing at 100 °C. The MOSFET's current-voltage characteristics were measured and analyzed in control devices, and in stressed unirradiated and irradiated devices, as well as in annealed devices. Our results reveal that Si-MOSFETs exhibit significant radiation-induced negative charge buildup in the gate oxide and its interface with Si. The negative charge buildup in the Si-MOSFETs is observed to occur upon DC electrical stress and the charge is enhanced in irradiated Si-MOSFETs suggesting the degradation of device stress reliability by irradiation. In contrast, SiC-MOSFETs exhibit superior irradiation resilience in comparison with Si-MOSFETs, however irradiated SiC-MOSFETs experience relatively increased stress-induced charge trapping and, hence, more degraded stress reliability, particularly under negative DC bias stress. These observations are explained in terms of hydrogen- and nitrogen-related defects, created during defect passivation processes in the gate oxides of the MOSFETs, and their interactions with energetic particles generated by irradiation and subsequent electrical stress. Thermal annealing of the irradiated and electrically stressed MOSFETs is observed to partially recover the threshold voltage but fails to restore the subthreshold slope, indicating persistent interface charge trapping. These findings highlight the impact of irradiation and emphasize the need for advanced defect passivation strategies to enhance the long-term reliability of MOSFETs in radiation-intensive environments.
{"title":"The effects of gamma irradiation of SiC- and Si-MOSFETs on their response to electrical stress and thermal annealing","authors":"Xinyu Wang , Osama Awadelkarim","doi":"10.1016/j.microrel.2025.115993","DOIUrl":"10.1016/j.microrel.2025.115993","url":null,"abstract":"<div><div>We report on the electrical stress reliability of gamma (γ) irradiated Si- and SiC-MOSFETs and their thermal annealing. The MOSFETs were irradiated by a Cobalt-60 (Co-60) source for up to 2 Mega Rad. The irradiation was followed by positive- or negative-polarity DC electrical stress and thermal annealing at 100 °C. The MOSFET's current-voltage characteristics were measured and analyzed in control devices, and in stressed unirradiated and irradiated devices, as well as in annealed devices. Our results reveal that Si-MOSFETs exhibit significant radiation-induced negative charge buildup in the gate oxide and its interface with Si. The negative charge buildup in the Si-MOSFETs is observed to occur upon DC electrical stress and the charge is enhanced in irradiated Si-MOSFETs suggesting the degradation of device stress reliability by irradiation. In contrast, SiC-MOSFETs exhibit superior irradiation resilience in comparison with Si-MOSFETs, however irradiated SiC-MOSFETs experience relatively increased stress-induced charge trapping and, hence, more degraded stress reliability, particularly under negative DC bias stress. These observations are explained in terms of hydrogen- and nitrogen-related defects, created during defect passivation processes in the gate oxides of the MOSFETs, and their interactions with energetic particles generated by irradiation and subsequent electrical stress. Thermal annealing of the irradiated and electrically stressed MOSFETs is observed to partially recover the threshold voltage but fails to restore the subthreshold slope, indicating persistent interface charge trapping. These findings highlight the impact of irradiation and emphasize the need for advanced defect passivation strategies to enhance the long-term reliability of MOSFETs in radiation-intensive environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115993"},"PeriodicalIF":1.9,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-02DOI: 10.1016/j.microrel.2025.115991
Peng Zhang , Songbai Xue , Lu Liu , Jianhao Wang , Fupeng Huo , Hiroshi Nishikawa
As one of the most widely used lead-free solder alloys, near eutectic Sn-Ag-Cu solder is characterized by poor impact reliability, which has garnered significant attention in the microelectronic packaging industry. This study explored the incorporation of epoxy resin into Sn-3.0Ag-0.5Cu (SAC305) solder paste to augment the mechanical properties of the SAC305 BGA solder joints. Microstructural observation revealed that, after reflow soldering, the cured epoxy surrounded the bottom of the solder ball, providing an additional bonding area between the solder ball and the PCB board. During the low-speed shear test, the incorporation of 4 % and 8 % epoxy resulted in a noticeable enhancement in the maximum shear forces of the SAC305 solder joints, attributed to the mechanical reinforcement provided by the epoxy. Furthermore, the epoxy addition did not change the fracture mode of the SAC305 solder joints. In the impact test, the SAC305 solder joint with 4 % epoxy demonstrated the highest maximum force at 59.79 N, representing a notable 29.0 % increase over the pure SAC305 solder joint. Concurrently, the addition of 4 % epoxy caused the fracture location to shift from the interfacial IMC layer to the solder bulk, manifesting an evident ductile fracture. This evolution could be attributed to the extrinsic toughening offered by epoxy, effectively dissipating impact energy and diminishing the dynamic stress transferred to the interface area. However, with further addition of epoxy, the volume of the solder ball decreased and the effective adhesive area between the solder ball and the epoxy reduced, resulting in a weakening of the external reinforcement effect of the epoxy. Therefore, the impact stability of SAC305 solder joints with 8 % epoxy decreased, and some solder joints exhibited a ductile-brittle mixed fracture mode characterized by quasi-ductile fracture.
{"title":"Improvement in impact property of SAC305 BGA solder joint through epoxy addition","authors":"Peng Zhang , Songbai Xue , Lu Liu , Jianhao Wang , Fupeng Huo , Hiroshi Nishikawa","doi":"10.1016/j.microrel.2025.115991","DOIUrl":"10.1016/j.microrel.2025.115991","url":null,"abstract":"<div><div>As one of the most widely used lead-free solder alloys, near eutectic Sn-Ag-Cu solder is characterized by poor impact reliability, which has garnered significant attention in the microelectronic packaging industry. This study explored the incorporation of epoxy resin into Sn-3.0Ag-0.5Cu (SAC305) solder paste to augment the mechanical properties of the SAC305 BGA solder joints. Microstructural observation revealed that, after reflow soldering, the cured epoxy surrounded the bottom of the solder ball, providing an additional bonding area between the solder ball and the PCB board. During the low-speed shear test, the incorporation of 4 % and 8 % epoxy resulted in a noticeable enhancement in the maximum shear forces of the SAC305 solder joints, attributed to the mechanical reinforcement provided by the epoxy. Furthermore, the epoxy addition did not change the fracture mode of the SAC305 solder joints. In the impact test, the SAC305 solder joint with 4 % epoxy demonstrated the highest maximum force at 59.79 N, representing a notable 29.0 % increase over the pure SAC305 solder joint. Concurrently, the addition of 4 % epoxy caused the fracture location to shift from the interfacial IMC layer to the solder bulk, manifesting an evident ductile fracture. This evolution could be attributed to the extrinsic toughening offered by epoxy, effectively dissipating impact energy and diminishing the dynamic stress transferred to the interface area. However, with further addition of epoxy, the volume of the solder ball decreased and the effective adhesive area between the solder ball and the epoxy reduced, resulting in a weakening of the external reinforcement effect of the epoxy. Therefore, the impact stability of SAC305 solder joints with 8 % epoxy decreased, and some solder joints exhibited a ductile-brittle mixed fracture mode characterized by quasi-ductile fracture.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115991"},"PeriodicalIF":1.9,"publicationDate":"2026-01-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-31DOI: 10.1016/j.microrel.2025.115989
M. Balasubrahmanyam, Ekta Goel
This research examines the impact of interface traps on the DC and AC/RF characteristics of advanced Nanosheet Field Effect Transistor (NSFET) architectures like Stacked NSFET, H-shaped NSFET (HS NSFET) and Pyramidal H-shaped NSFET (PHS NSFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/ insulator. The proposed devices with positive (donor) and negative (acceptor) fixed interface charges (FICs), have been simulated using TCAD tool. To understand the impact of different FICs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance (gm), parasitic capacitance, fT, GBP and TFP have been analysed. Our findings offer critical insights for enhancing NSFETs design for next-generation applications in high-performance and low power electronics. Further a five-stage ring oscillator has also been explored and it has been found that PHS NSFET exhibit better oscillating frequency when compared to SNSFET and HS NSFET at different FICs.
{"title":"Impact of interface traps on advanced nanosheet FETs: A reliability perspective from device to circuit level","authors":"M. Balasubrahmanyam, Ekta Goel","doi":"10.1016/j.microrel.2025.115989","DOIUrl":"10.1016/j.microrel.2025.115989","url":null,"abstract":"<div><div>This research examines the impact of interface traps on the DC and AC/RF characteristics of advanced Nanosheet Field Effect Transistor (NSFET) architectures like Stacked NSFET, H-shaped NSFET (HS NSFET) and Pyramidal H-shaped NSFET (PHS NSFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/ insulator. The proposed devices with positive (donor) and negative (acceptor) fixed interface charges (FICs), have been simulated using TCAD tool. To understand the impact of different FICs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance (g<sub>m</sub>), parasitic capacitance, f<sub>T</sub>, GBP and TFP have been analysed. Our findings offer critical insights for enhancing NSFETs design for next-generation applications in high-performance and low power electronics. Further a five-stage ring oscillator has also been explored and it has been found that PHS NSFET exhibit better oscillating frequency when compared to SNSFET and HS NSFET at different FICs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115989"},"PeriodicalIF":1.9,"publicationDate":"2025-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-29DOI: 10.1016/j.microrel.2025.115988
Shreeji H. Shah , Rajesh A. Thakker
Physically Unclonable Functions (PUFs) play a critical role in hardware security by exploiting intrinsic process variations. This study presents a comprehensive analysis of circuit-level factors impacting the reliability and performance of PUFs, focusing on current mirror-based architecture. The simulations are carried out using 65 nm Predictive Technology Models (PTM). The effects of output swing variations in current mirrors on PUF reliability are systematically investigated, revealing their significant influence on response stability under process, voltage, and temperature fluctuations. Additionally, the impact of hysteresis characteristics, specifically the window size and transitioning slope, is examined for their contribution to reliability enhancement. A reliability - in terms of bitflip probability, is thoroughly examined across temperature −20 °C to 80 °C. A quantitative evaluation of uniformity and uniqueness is performed across different transistor sizing configurations, providing insight into the trade-offs between design parameters and PUF performance. The findings offer practical design guidelines to achieve improved reliability with better uniformity and uniqueness, contributing to the development of robust and secure PUF implementations. The optimized design with reliability perspective has 0 % native bitflips without post-processing, demonstrates 49.83 % uniformity and 50.43 % uniqueness having 3.69μm2 area/bit, providing a balance between silicon-cost and PUF performance metric.
{"title":"Reliability aware design of complementary cascode current mirror based physically unclonable functions and characterization","authors":"Shreeji H. Shah , Rajesh A. Thakker","doi":"10.1016/j.microrel.2025.115988","DOIUrl":"10.1016/j.microrel.2025.115988","url":null,"abstract":"<div><div>Physically Unclonable Functions (PUFs) play a critical role in hardware security by exploiting intrinsic process variations. This study presents a comprehensive analysis of circuit-level factors impacting the reliability and performance of PUFs, focusing on current mirror-based architecture. The simulations are carried out using 65 nm Predictive Technology Models (PTM). The effects of output swing variations in current mirrors on PUF reliability are systematically investigated, revealing their significant influence on response stability under process, voltage, and temperature fluctuations. Additionally, the impact of hysteresis characteristics, specifically the window size and transitioning slope, is examined for their contribution to reliability enhancement. A reliability - in terms of bitflip probability, is thoroughly examined across temperature −20 °C to 80 °C. A quantitative evaluation of uniformity and uniqueness is performed across different transistor sizing configurations, providing insight into the trade-offs between design parameters and PUF performance. The findings offer practical design guidelines to achieve improved reliability with better uniformity and uniqueness, contributing to the development of robust and secure PUF implementations. The optimized design with reliability perspective has 0 % native bitflips without post-processing, demonstrates 49.83 % uniformity and 50.43 % uniqueness having 3.69μm<sup>2</sup> area/bit, providing a balance between silicon-cost and PUF performance metric.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115988"},"PeriodicalIF":1.9,"publicationDate":"2025-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145885487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-24DOI: 10.1016/j.microrel.2025.115990
Koki Okame , Shin-ichi Nishizawa , Wataru Saito
This paper reports on the integration of power cycling sensors into a PIN diode chip and the experimental verification of the correlation between the change in sensor current and the increase in package thermal resistance through power cycling tests. The sensor device consists of a Schottky barrier MISFET and can be integrated into a power device. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density in the MIS gate. In a previous study, the sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical bending stress. The thermomechanical stress induced by power cycling tests is mainly a biaxial stress, whereas bending stress has a different geometry, with uniaxial and shear stress components. Therefore, a power cycling test is needed to generate thermomechanical stress and evaluate the actual sensitivity. In this study, the increase in package thermal resistance and the decrease in sensor current with an increasing number of stress cycles in the power cycling test were observed, demonstrating the operation of the sensor due to repetitive thermal stress.
{"title":"Experimental demonstration of power cycling sensors integrated into a power device chip","authors":"Koki Okame , Shin-ichi Nishizawa , Wataru Saito","doi":"10.1016/j.microrel.2025.115990","DOIUrl":"10.1016/j.microrel.2025.115990","url":null,"abstract":"<div><div>This paper reports on the integration of power cycling sensors into a PIN diode chip and the experimental verification of the correlation between the change in sensor current and the increase in package thermal resistance through power cycling tests. The sensor device consists of a Schottky barrier MISFET and can be integrated into a power device. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density in the MIS gate. In a previous study, the sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical bending stress. The thermomechanical stress induced by power cycling tests is mainly a biaxial stress, whereas bending stress has a different geometry, with uniaxial and shear stress components. Therefore, a power cycling test is needed to generate thermomechanical stress and evaluate the actual sensitivity. In this study, the increase in package thermal resistance and the decrease in sensor current with an increasing number of stress cycles in the power cycling test were observed, demonstrating the operation of the sensor due to repetitive thermal stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115990"},"PeriodicalIF":1.9,"publicationDate":"2025-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates the time-dependent gate breakdown of High Electron Mobility Transistors (HEMT) by applying constant stress to the gate until a catastrophic failure occurs. Measurements were conducted on two references. Reference A was tested from −55 °C to 80 °C, showing a negative activation energy, which is more likely due to dielectric breakdown near the p-GaN triggered by impact ionization and accelerated at lower temperatures. Device B, tested from −40 °C to 120 °C, exhibited a positive activation energy, indicating a lower Mean Time To Failure at higher temperatures. This positive activation energy is linked to the behavior of the gate temperature-dependent leakage current, which might increase faster with temperature than the impact ionization decrease, leading to the positive activation energy.
{"title":"On the activation energy in SP-GaN gate HEMT devices during gate lifetime test","authors":"Maroun Alam , Valeria Rustichelli , Moustafa Zerarka , Christophe Banc , Jean-François Pieprzyk , Olivier Perrotin , Romain Ceccarelli , David Trémouilles , Mohamed Matmat , Fabio Coccetti","doi":"10.1016/j.microrel.2025.115986","DOIUrl":"10.1016/j.microrel.2025.115986","url":null,"abstract":"<div><div>This paper investigates the time-dependent gate breakdown of High Electron Mobility Transistors (HEMT) by applying constant stress to the gate until a catastrophic failure occurs. Measurements were conducted on two references. Reference A was tested from −55 °C to 80 °C, showing a negative activation energy, which is more likely due to dielectric breakdown near the p-GaN triggered by impact ionization and accelerated at lower temperatures. Device B, tested from −40 °C to 120 °C, exhibited a positive activation energy, indicating a lower Mean Time To Failure at higher temperatures. This positive activation energy is linked to the behavior of the gate temperature-dependent leakage current, which might increase faster with temperature than the impact ionization decrease, leading to the positive activation energy.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"177 ","pages":"Article 115986"},"PeriodicalIF":1.9,"publicationDate":"2025-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-20DOI: 10.1016/j.microrel.2025.115980
I. Marozau , Q. Tang , M. Kulsreshath , Y. Li , S.J. Bleiker , F. Niklaus , D. Pamunuwa
Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.
{"title":"Mechanical shock and vibration testing of volatile and non-volatile nanoelectromechanical switches","authors":"I. Marozau , Q. Tang , M. Kulsreshath , Y. Li , S.J. Bleiker , F. Niklaus , D. Pamunuwa","doi":"10.1016/j.microrel.2025.115980","DOIUrl":"10.1016/j.microrel.2025.115980","url":null,"abstract":"<div><div>Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115980"},"PeriodicalIF":1.9,"publicationDate":"2025-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-19DOI: 10.1016/j.microrel.2025.115984
Huihui Wu, Haisheng Miao, Yingying Yang, Jiawei Yu, Ye Fu, Zhenhua Song, Zhaofeng Li
The gate-source voltage (Vgs) is a critical electrical parameter which can make the Split-Gate-Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) maintain stability and reliability in various control scenarios. The impacts of high density plasma chemical vapor deposition (HDPCVD) and low pressure chemical vapor deposition (LPCVD) methods on the morphology of the inter-poly oxide (IPO) layer, as well as their subsequent effects on Vgs performance, were investigated in this study. Specifically, two sputtering agents, Ar and He, were utilized in the HDPCVD approach. Wet etching rates of the different films explain the mechanism of rounded IPO morphology formation. Scanning electron microscope (SEM) observations and electrical characterization results demonstrate that the rounded bottom corners of the optimized gate polysilicon, fabricated by HDP He combined with Ar plasma method, exhibit superior Vgs & lower leakage current performance.
{"title":"Enhanced gate-source voltage in SGT MOSFET via inter poly oxide process-induced morphology improvement","authors":"Huihui Wu, Haisheng Miao, Yingying Yang, Jiawei Yu, Ye Fu, Zhenhua Song, Zhaofeng Li","doi":"10.1016/j.microrel.2025.115984","DOIUrl":"10.1016/j.microrel.2025.115984","url":null,"abstract":"<div><div>The gate-source voltage (Vgs) is a critical electrical parameter which can make the Split-Gate-Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) maintain stability and reliability in various control scenarios. The impacts of high density plasma chemical vapor deposition (HDPCVD) and low pressure chemical vapor deposition (LPCVD) methods on the morphology of the inter-poly oxide (IPO) layer, as well as their subsequent effects on Vgs performance, were investigated in this study. Specifically, two sputtering agents, Ar and He, were utilized in the HDPCVD approach. Wet etching rates of the different films explain the mechanism of rounded IPO morphology formation. Scanning electron microscope (SEM) observations and electrical characterization results demonstrate that the rounded bottom corners of the optimized gate polysilicon, fabricated by HDP He combined with Ar plasma method, exhibit superior Vgs & lower leakage current performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115984"},"PeriodicalIF":1.9,"publicationDate":"2025-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145789707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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