Microelectronics Reliability最新文献_第4页

The effects of gamma irradiation of SiC- and Si-MOSFETs on their response to electrical stress and thermal annealing 研究了γ辐照对SiC- mosfet和si - mosfet电应力响应和热处理的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-02 DOI: 10.1016/j.microrel.2025.115993

Xinyu Wang , Osama Awadelkarim

We report on the electrical stress reliability of gamma (γ) irradiated Si- and SiC-MOSFETs and their thermal annealing. The MOSFETs were irradiated by a Cobalt-60 (Co-60) source for up to 2 Mega Rad. The irradiation was followed by positive- or negative-polarity DC electrical stress and thermal annealing at 100 °C. The MOSFET's current-voltage characteristics were measured and analyzed in control devices, and in stressed unirradiated and irradiated devices, as well as in annealed devices. Our results reveal that Si-MOSFETs exhibit significant radiation-induced negative charge buildup in the gate oxide and its interface with Si. The negative charge buildup in the Si-MOSFETs is observed to occur upon DC electrical stress and the charge is enhanced in irradiated Si-MOSFETs suggesting the degradation of device stress reliability by irradiation. In contrast, SiC-MOSFETs exhibit superior irradiation resilience in comparison with Si-MOSFETs, however irradiated SiC-MOSFETs experience relatively increased stress-induced charge trapping and, hence, more degraded stress reliability, particularly under negative DC bias stress. These observations are explained in terms of hydrogen- and nitrogen-related defects, created during defect passivation processes in the gate oxides of the MOSFETs, and their interactions with energetic particles generated by irradiation and subsequent electrical stress. Thermal annealing of the irradiated and electrically stressed MOSFETs is observed to partially recover the threshold voltage but fails to restore the subthreshold slope, indicating persistent interface charge trapping. These findings highlight the impact of irradiation and emphasize the need for advanced defect passivation strategies to enhance the long-term reliability of MOSFETs in radiation-intensive environments.

我们报告了γ (γ)辐照的Si-和sic - mosfet及其热退火的电应力可靠性。将mosfet用钴-60 （Co-60）源照射至2兆Rad，辐照后进行正负极性直流电应力和100°C的热退火。在控制器件、应力未辐照器件和辐照器件以及退火器件中测量和分析了MOSFET的电流-电压特性。我们的研究结果表明，Si- mosfet在栅极氧化物及其与Si的界面中表现出明显的辐射诱导负电荷积累。在直流电应力作用下，si - mosfet中负电荷的积累被观察到，并且在辐照的si - mosfet中负电荷增加，这表明辐照降低了器件的应力可靠性。相比之下，sic - mosfet表现出比si - mosfet更好的辐照弹性，然而，sic - mosfet辐照后会经历相对增加的应力诱导电荷捕获，因此应力可靠性更低，特别是在负直流偏压应力下。这些观察结果被解释为在mosfet栅极氧化物的缺陷钝化过程中产生的氢和氮相关缺陷，以及它们与辐射和随后的电应力产生的高能粒子的相互作用。观察到辐照和电应力mosfet的热退火可以部分恢复阈值电压，但无法恢复亚阈值斜率，表明界面电荷持续捕获。这些发现突出了辐射的影响，并强调需要先进的缺陷钝化策略来提高mosfet在辐射密集环境中的长期可靠性。

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引用次数: 0

Improvement in impact property of SAC305 BGA solder joint through epoxy addition 添加环氧树脂改善sac305bga焊点冲击性能

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2026-01-02 DOI: 10.1016/j.microrel.2025.115991

Peng Zhang , Songbai Xue , Lu Liu , Jianhao Wang , Fupeng Huo , Hiroshi Nishikawa

As one of the most widely used lead-free solder alloys, near eutectic Sn-Ag-Cu solder is characterized by poor impact reliability, which has garnered significant attention in the microelectronic packaging industry. This study explored the incorporation of epoxy resin into Sn-3.0Ag-0.5Cu (SAC305) solder paste to augment the mechanical properties of the SAC305 BGA solder joints. Microstructural observation revealed that, after reflow soldering, the cured epoxy surrounded the bottom of the solder ball, providing an additional bonding area between the solder ball and the PCB board. During the low-speed shear test, the incorporation of 4 % and 8 % epoxy resulted in a noticeable enhancement in the maximum shear forces of the SAC305 solder joints, attributed to the mechanical reinforcement provided by the epoxy. Furthermore, the epoxy addition did not change the fracture mode of the SAC305 solder joints. In the impact test, the SAC305 solder joint with 4 % epoxy demonstrated the highest maximum force at 59.79 N, representing a notable 29.0 % increase over the pure SAC305 solder joint. Concurrently, the addition of 4 % epoxy caused the fracture location to shift from the interfacial IMC layer to the solder bulk, manifesting an evident ductile fracture. This evolution could be attributed to the extrinsic toughening offered by epoxy, effectively dissipating impact energy and diminishing the dynamic stress transferred to the interface area. However, with further addition of epoxy, the volume of the solder ball decreased and the effective adhesive area between the solder ball and the epoxy reduced, resulting in a weakening of the external reinforcement effect of the epoxy. Therefore, the impact stability of SAC305 solder joints with 8 % epoxy decreased, and some solder joints exhibited a ductile-brittle mixed fracture mode characterized by quasi-ductile fracture.

近共晶Sn-Ag-Cu钎料作为应用最广泛的无铅钎料合金之一，其冲击可靠性差的特点在微电子封装行业引起了广泛的关注。本研究探讨了在Sn-3.0Ag-0.5Cu （SAC305）锡膏中加入环氧树脂以提高SAC305 BGA焊点的力学性能。显微结构观察表明，回流焊后，固化的环氧树脂包围了焊锡球的底部，在焊锡球和PCB板之间提供了额外的粘合区域。在低速剪切试验中，加入4%和8%的环氧树脂后，SAC305焊点的最大剪切力明显增强，这是由于环氧树脂提供的机械增强。此外，环氧树脂的加入并没有改变SAC305焊点的断裂方式。在冲击试验中，添加4%环氧树脂的SAC305焊点在59.79 N时表现出最大的冲击力，比纯SAC305焊点的冲击力提高了29.0%。同时，4%环氧树脂的加入导致断口位置从界面IMC层转移到焊料块，表现出明显的韧性断裂。这种演变可归因于环氧树脂提供的外在增韧，有效地消散了冲击能量并减小了传递到界面区域的动应力。然而，随着环氧树脂的进一步加入，焊锡球的体积减小，焊锡球与环氧树脂之间的有效粘接面积减小，导致环氧树脂的外补强作用减弱。因此，添加8%环氧树脂的SAC305焊点的冲击稳定性下降，部分焊点呈现出以准韧性断裂为特征的韧脆混合断裂模式。

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引用次数: 0

Impact of interface traps on advanced nanosheet FETs: A reliability perspective from device to circuit level 界面陷阱对先进纳米片场效应管的影响：从器件到电路级的可靠性观点

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-31 DOI: 10.1016/j.microrel.2025.115989

M. Balasubrahmanyam, Ekta Goel

This research examines the impact of interface traps on the DC and AC/RF characteristics of advanced Nanosheet Field Effect Transistor (NSFET) architectures like Stacked NSFET, H-shaped NSFET (HS NSFET) and Pyramidal H-shaped NSFET (PHS NSFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/ insulator. The proposed devices with positive (donor) and negative (acceptor) fixed interface charges (FICs), have been simulated using TCAD tool. To understand the impact of different FICs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance (g_m), parasitic capacitance, f_T, GBP and TFP have been analysed. Our findings offer critical insights for enhancing NSFETs design for next-generation applications in high-performance and low power electronics. Further a five-stage ring oscillator has also been explored and it has been found that PHS NSFET exhibit better oscillating frequency when compared to SNSFET and HS NSFET at different FICs.

本研究通过在半导体/绝缘体界面引入局域电荷（供体/受体），研究了界面陷阱对先进的纳米片场效应晶体管（NSFET）结构（如堆叠NSFET、h形NSFET （HS NSFET）和金字塔形h形NSFET (PHS NSFET)）的直流和交流/射频特性的影响。采用TCAD工具模拟了具有正（供体）和负（受体）固定界面电荷（FICs）的器件。为了了解不同fic对直流和模拟/RF性能的影响，分析了电场、传输特性、跨导（gm）、寄生电容、fT、GBP和TFP等参数。我们的研究结果为增强高性能和低功耗电子产品中下一代应用的nsfet设计提供了关键见解。此外，还对五级环形振荡器进行了探索，发现在不同的FICs下，PHS NSFET比snfet和HS NSFET表现出更好的振荡频率。

引用次数: 0

Reliability aware design of complementary cascode current mirror based physically unclonable functions and characterization 基于物理不可克隆功能和特性的互补级联电流镜可靠性感知设计

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-29 DOI: 10.1016/j.microrel.2025.115988

Shreeji H. Shah , Rajesh A. Thakker

Physically Unclonable Functions (PUFs) play a critical role in hardware security by exploiting intrinsic process variations. This study presents a comprehensive analysis of circuit-level factors impacting the reliability and performance of PUFs, focusing on current mirror-based architecture. The simulations are carried out using 65 nm Predictive Technology Models (PTM). The effects of output swing variations in current mirrors on PUF reliability are systematically investigated, revealing their significant influence on response stability under process, voltage, and temperature fluctuations. Additionally, the impact of hysteresis characteristics, specifically the window size and transitioning slope, is examined for their contribution to reliability enhancement. A reliability - in terms of bitflip probability, is thoroughly examined across temperature −20 °C to 80 °C. A quantitative evaluation of uniformity and uniqueness is performed across different transistor sizing configurations, providing insight into the trade-offs between design parameters and PUF performance. The findings offer practical design guidelines to achieve improved reliability with better uniformity and uniqueness, contributing to the development of robust and secure PUF implementations. The optimized design with reliability perspective has 0 % native bitflips without post-processing, demonstrates 49.83 % uniformity and 50.43 % uniqueness having 3.69μm² area/bit, providing a balance between silicon-cost and PUF performance metric.

物理不可克隆函数（puf）通过利用固有的进程变化在硬件安全性中起着关键作用。本研究全面分析了影响puf可靠性和性能的电路级因素，重点关注当前基于镜像的架构。采用65nm预测技术模型（PTM）进行仿真。系统研究了电流镜输出摆幅变化对PUF可靠性的影响，揭示了它们在工艺、电压和温度波动下对响应稳定性的显著影响。此外，还研究了迟滞特性（特别是窗大小和过渡斜率）对可靠性增强的影响。在温度- 20°C至80°C范围内，彻底检查了可靠性（就位翻转概率而言）。对不同晶体管尺寸配置的均匀性和独特性进行定量评估，从而深入了解设计参数和PUF性能之间的权衡。研究结果提供了实用的设计指南，以实现更好的一致性和唯一性，从而提高可靠性，有助于开发健壮和安全的PUF实现。基于可靠性的优化设计在无后处理的情况下具有0%的原生位翻转，具有3.69μm2面积/位，具有49.83%的均匀性和50.43%的唯一性，在硅成本和PUF性能指标之间取得了平衡。

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引用次数: 0

Experimental demonstration of power cycling sensors integrated into a power device chip 集成在功率器件芯片中的功率循环传感器的实验演示

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-24 DOI: 10.1016/j.microrel.2025.115990

Koki Okame , Shin-ichi Nishizawa , Wataru Saito

This paper reports on the integration of power cycling sensors into a PIN diode chip and the experimental verification of the correlation between the change in sensor current and the increase in package thermal resistance through power cycling tests. The sensor device consists of a Schottky barrier MISFET and can be integrated into a power device. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density in the MIS gate. In a previous study, the sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical bending stress. The thermomechanical stress induced by power cycling tests is mainly a biaxial stress, whereas bending stress has a different geometry, with uniaxial and shear stress components. Therefore, a power cycling test is needed to generate thermomechanical stress and evaluate the actual sensitivity. In this study, the increase in package thermal resistance and the decrease in sensor current with an increasing number of stress cycles in the power cycling test were observed, demonstrating the operation of the sensor due to repetitive thermal stress.

本文报道了将功率循环传感器集成到PIN二极管芯片中，并通过功率循环测试实验验证了传感器电流变化与封装热阻增加之间的相关性。该传感器装置由肖特基势垒MISFET组成，可集成到功率器件中。功率循环退化是通过SB-MISFET漏极电流的减少来检测的，因为重复的机械应力增加了MIS栅极中的界面态密度。在之前的一项研究中，传感器设备展示了由于重复机械弯曲应力而导致漏极电流减少的基本操作。功率循环试验引起的热机械应力主要是双向应力，而弯曲应力具有不同的几何形状，具有单轴和剪切应力成分。因此，需要进行功率循环试验来产生热机械应力并评估实际灵敏度。在本研究中，我们观察到在功率循环测试中，随着应力循环次数的增加，封装热阻增大，传感器电流减小，证明了传感器在重复热应力的作用下工作。

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引用次数: 0

On the activation energy in SP-GaN gate HEMT devices during gate lifetime test 栅极寿命测试中SP-GaN栅极HEMT器件活化能的研究

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-23 DOI: 10.1016/j.microrel.2025.115986

Maroun Alam , Valeria Rustichelli , Moustafa Zerarka , Christophe Banc , Jean-François Pieprzyk , Olivier Perrotin , Romain Ceccarelli , David Trémouilles , Mohamed Matmat , Fabio Coccetti

This paper investigates the time-dependent gate breakdown of High Electron Mobility Transistors (HEMT) by applying constant stress to the gate until a catastrophic failure occurs. Measurements were conducted on two references. Reference A was tested from −55 °C to 80 °C, showing a negative activation energy, which is more likely due to dielectric breakdown near the p-GaN triggered by impact ionization and accelerated at lower temperatures. Device B, tested from −40 °C to 120 °C, exhibited a positive activation energy, indicating a lower Mean Time To Failure at higher temperatures. This positive activation energy is linked to the behavior of the gate temperature-dependent leakage current, which might increase faster with temperature than the impact ionization decrease, leading to the positive activation energy.

本文通过对高电子迁移率晶体管栅极施加恒定应力直至发生灾难性破坏的方法，研究了高电子迁移率晶体管栅极的时变击穿。在两个参考文献上进行了测量。参考文献A在- 55°C至80°C范围内测试，显示出负活化能，这更可能是由于撞击电离引发的p-GaN附近的介电击穿，并在较低温度下加速。在−40°C到120°C的测试中，器件B显示出正的活化能，表明在较高温度下的平均失效时间较短。这种正活化能与栅极温度相关的泄漏电流的行为有关，泄漏电流随温度的增加可能比冲击电离的减少更快，从而导致正活化能。

引用次数: 0

Mechanical shock and vibration testing of volatile and non-volatile nanoelectromechanical switches 易失性和非易失性纳米机电开关的机械冲击和振动测试

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-20 DOI: 10.1016/j.microrel.2025.115980

I. Marozau , Q. Tang , M. Kulsreshath , Y. Li , S.J. Bleiker , F. Niklaus , D. Pamunuwa

Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.

纳米机电（NEM）开关由于其零泄漏电流和辐射硬度，在恶劣环境下的超低功耗电子产品中具有很大的前景。然而，它们在极端载荷下的机械鲁棒性研究还不够充分。这项工作研究了3端和7端NEM继电器在高达5000 g的机械冲击和高达70 g的振动下的性能。所有测试的设备都保留了机械功能，证实了良好的结构完整性。电气特性揭示了7T继电器的拉入和拉出电压的变化以及编程状态的损失，尽管它们的非易失性能力保持不变。这些不稳定性主要是由于软金接触涂层，这是容易磨损和变形。研究结果强调了NEM技术在恶劣环境中的适用性，并指出了未来通过更合适的接触材料和设备小型化的改进。

引用次数: 0

Enhanced gate-source voltage in SGT MOSFET via inter poly oxide process-induced morphology improvement 通过多氧化物间工艺诱导的形态学改善提高SGT MOSFET的栅源电压

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-19 DOI: 10.1016/j.microrel.2025.115984

Huihui Wu, Haisheng Miao, Yingying Yang, Jiawei Yu, Ye Fu, Zhenhua Song, Zhaofeng Li

The gate-source voltage (Vgs) is a critical electrical parameter which can make the Split-Gate-Trench Metal Oxide Semiconductor Field Effect Transistor (SGT MOSFET) maintain stability and reliability in various control scenarios. The impacts of high density plasma chemical vapor deposition (HDPCVD) and low pressure chemical vapor deposition (LPCVD) methods on the morphology of the inter-poly oxide (IPO) layer, as well as their subsequent effects on Vgs performance, were investigated in this study. Specifically, two sputtering agents, Ar and He, were utilized in the HDPCVD approach. Wet etching rates of the different films explain the mechanism of rounded IPO morphology formation. Scanning electron microscope (SEM) observations and electrical characterization results demonstrate that the rounded bottom corners of the optimized gate polysilicon, fabricated by HDP He combined with Ar plasma method, exhibit superior Vgs & lower leakage current performance.

栅极-源电压（Vgs）是保证分栅-沟槽金属氧化物半导体场效应晶体管（SGT MOSFET）在各种控制场景下保持稳定性和可靠性的关键电学参数。研究了高密度等离子体化学气相沉积（HDPCVD）和低压化学气相沉积（LPCVD）方法对聚氧化物间层（IPO）形貌的影响，以及它们对Vgs性能的后续影响。具体来说，在HDPCVD方法中使用了两种溅射剂Ar和He。不同薄膜的湿蚀刻速率解释了圆形IPO形态形成的机理。扫描电镜（SEM）观察和电学表征结果表明，优化后的HDP - He结合Ar等离子体法制备的栅极多晶硅的圆角底角具有优异的Vgs和较低的漏电流性能。

引用次数: 0

Machine learning classifiers with explainable insights for parametric fault diagnosis in linear analog circuits using frequency response features 使用频率响应特征的线性模拟电路中具有可解释的参数故障诊断见解的机器学习分类器

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-17 DOI: 10.1016/j.microrel.2025.115982

Vanshika Rajpal , A. Charan Kumari , K. Srinivas

Accurate and scalable fault diagnosis in analog integrated circuits (AICs) remains a significant challenge, particularly in detecting soft parametric faults arising from process variations, aging, and environmental factors. This paper presents a comprehensive machine learning–based framework for automated fault classification in linear analog circuits, demonstrated through two representative case studies, an RC band-pass filter and a Butterworth low-pass filter. Frequency-domain responses of both output voltage and supply current were analysed, and complex-valued features comprising real and imaginary components were extracted to capture the circuits' resistive and reactive characteristics.

Monte Carlo simulations with ±30 % component deviations generated a rich dataset for training and validation. Nine machine learning classifiers, including CatBoost, LightGBM, and XGBoost, were benchmarked against traditional approaches. The proposed complex-domain feature extraction method significantly outperformed magnitude-only and real-part-only baselines, with CatBoost achieving the highest accuracy of 99.75 %. Computational efficiency and inference analysis confirmed the model's suitability for real-time fault diagnosis, with millisecond-level latency and compact model size. SHAP (SHapley Additive exPlanations) analysis provided interpretability by identifying the most influential spectral features contributing to fault classification.

Finally, the framework's generalisation and practical feasibility were demonstrated through cross-circuit evaluation and a hardware validation perspective, outlining measurement procedures and highlighting its real-world applicability. The results confirm that the proposed approach effectively integrates high diagnostic accuracy, interpretability, and computational efficiency, establishing a robust and explainable solution for fault diagnosis in linear analog circuits.

在模拟集成电路（aic）中，准确和可扩展的故障诊断仍然是一个重大挑战，特别是在检测由工艺变化、老化和环境因素引起的软参数故障方面。本文提出了一个全面的基于机器学习的框架，用于线性模拟电路的自动故障分类，并通过两个代表性的案例研究，RC带通滤波器和巴特沃斯低通滤波器进行了演示。分析了输出电压和电源电流的频域响应，提取了包含实分量和虚分量的复值特征，以捕获电路的电阻和无功特性。具有±30%分量偏差的蒙特卡罗模拟生成了用于训练和验证的丰富数据集。包括CatBoost、LightGBM和XGBoost在内的9个机器学习分类器与传统方法进行了基准测试。所提出的复域特征提取方法显著优于纯幅值和纯实部基线，其中CatBoost达到了99.75%的最高准确率。计算效率和推理分析表明，该模型具有毫秒级的延迟和紧凑的模型尺寸，适合于实时故障诊断。SHAP （SHapley加性解释）分析通过识别有助于断层分类的最具影响力的光谱特征来提供可解释性。最后，通过交叉电路评估和硬件验证的角度论证了该框架的概括性和实际可行性，概述了测量程序并强调了其在现实世界中的适用性。结果表明，该方法有效地集成了较高的诊断精度、可解释性和计算效率，为线性模拟电路的故障诊断建立了鲁棒性和可解释性的解决方案。

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引用次数: 0

Power cycling-induced degradation mechanisms in SiC MOSFETs with embedded Schottky barrier diodes 嵌入肖特基势垒二极管的SiC mosfet的功率循环诱导退化机制

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-12-16 DOI: 10.1016/j.microrel.2025.115978

Gyuhyeok Kang , Ogyun Seok

The long-term reliability of 1.2 kV 4H-SiC MOSFETs monolithically integrated with Schottky barrier diodes (SBDs) was systematically investigated under repetitive thermo-electrical stress using DC power cycling. While SBD integration suppresses reverse-recovery charge and enhances high-frequency switching performance, the additional metal–semiconductor junctions in the body diode region introduce potential failure sites susceptible to thermally activated degradation mechanisms. In this work, devices with and without embedded SBDs were subjected to controlled junction temperature swings (ΔT_j = 110 °C, T_j,m = 120 °C) for multiple cycling intervals. Temperature-sensitive electrical parameter (TSEP) monitoring, based on the low-current source–drain voltage (V_SD), was performed in-situ during every power cycling event, enabling continuous tracking of junction temperature variation associated with SBD forward voltage shift. A comprehensive parametric analysis including on state resistance (R_on), threshold voltage (V_th), breakdown voltage (BV), forward conduction characteristics (V_F), and reverse leakage characteristics was conducted to identify the dominant degradation mechanisms in SiC MOSFETs with embedded SBDs under power cycling conditions.

利用直流电源循环系统地研究了单片集成肖特基势垒二极管（sbd）的1.2 kV 4H-SiC mosfet在重复热电应力下的长期可靠性。虽然SBD集成抑制反向恢复电荷并提高高频开关性能，但在体二极管区域的额外金属半导体结引入了容易受到热激活降解机制影响的潜在失效点。在这项工作中，带和不带嵌入式sdd的器件在多个循环间隔内受到控制的结温波动（ΔTj = 110°C, Tj,m = 120°C）。基于低电流源漏电压（VSD）的温度敏感电参数（TSEP）监测在每次电源循环过程中都进行了现场监测，从而能够连续跟踪与SBD前向电压移位相关的结温变化。通过对状态电阻（Ron）、阈值电压（Vth）、击穿电压（BV）、正导特性（VF）和反漏特性的综合参数分析，确定了功率循环条件下嵌入sdd的SiC mosfet的主要退化机制。

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引用次数: 0