In this study, the effect of Ag content (x = 0, 1, 2, 3 wt%) on the microstructural evolution and the distribution of second phase particles in Sn-0.7Cu-xAg were analyzed utilizing scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Morphology of second-phase particles in low-temperature fracture surfaces of Sn-3.5Ag and Sn-0.7Cu solder alloys was characterized using TEM and focused ion beam (FIB) techniques. The results demonstrated that Ag within the solder matrix significantly inhibited the formation of Cu6Sn5 intermetallic compounds (IMCs). With increasing Ag content, Cu6Sn5 particles evolved from extensive, strip-like structures to a finer, more uniform distribution. Ag3Sn particles predominantly accumulated at grain boundaries, with minimal Ag detected within the solder matrix. In contrast, Cu6Sn5 particles, along with a significant dispersion of copper (Cu) throughout the matrix, were also observed at grain boundaries. Quantitative analysis demonstrated that the suppression of Cu6Sn5 formation (assessed via Gibbs free energy calculations) reached its maximum efficacy at a critical Ag concentration of 0.17 at.%, with diminishing effects observed when Ag content exceeded 0.35 at. %.
{"title":"Effect of Ag addition on the microstructure and distribution of second-phase particles in tin-based solder alloys","authors":"Wei Zhang , Xiangxi Zhao , Jiayun Feng , Wei Liu , Ruyu Tian , Yanhong Tian","doi":"10.1016/j.microrel.2025.115969","DOIUrl":"10.1016/j.microrel.2025.115969","url":null,"abstract":"<div><div>In this study, the effect of Ag content (x = 0, 1, 2, 3 wt%) on the microstructural evolution and the distribution of second phase particles in Sn-0.7Cu-xAg were analyzed utilizing scanning electron microscopy (SEM) and transmission electron microscopy (TEM). Morphology of second-phase particles in low-temperature fracture surfaces of Sn-3.5Ag and Sn-0.7Cu solder alloys was characterized using TEM and focused ion beam (FIB) techniques. The results demonstrated that Ag within the solder matrix significantly inhibited the formation of Cu<sub>6</sub>Sn<sub>5</sub> intermetallic compounds (IMCs). With increasing Ag content, Cu<sub>6</sub>Sn<sub>5</sub> particles evolved from extensive, strip-like structures to a finer, more uniform distribution. Ag<sub>3</sub>Sn particles predominantly accumulated at grain boundaries, with minimal Ag detected within the solder matrix. In contrast, Cu<sub>6</sub>Sn<sub>5</sub> particles, along with a significant dispersion of copper (Cu) throughout the matrix, were also observed at grain boundaries. Quantitative analysis demonstrated that the suppression of Cu<sub>6</sub>Sn<sub>5</sub> formation (assessed via Gibbs free energy calculations) reached its maximum efficacy at a critical Ag concentration of 0.17 at.%, with diminishing effects observed when Ag content exceeded 0.35 at. %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115969"},"PeriodicalIF":1.9,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-25DOI: 10.1016/j.microrel.2025.115952
M. Sanogo , T. Kociniewski , Z. Khatir
In this paper, we improved the signal-to-noise ratio (S/N) of thermoreflectance images of trench Insulated Gate Bipolar Transistors (IGBT) particularly in low-intensity areas caused by insufficient illumination or defocusing due to topography and depth variations within these components. To enhance and homogenize signal intensity across the entire surface, we accurately determined the focal planes and optimal lighting conditions for each region. Then, before performing reflectivity calculations, we reconstructed a single high intensity optical image by selecting pixels based on their local focus values. This optical image reconstruction ensures a uniform distribution of maximum intensity across the image and significantly improvises the S/N ratio minimizing artifacts in the final reflectivity map.
{"title":"Improved thermoreflectance imaging of trench IGBT via focus and illumination optimized reconstruction","authors":"M. Sanogo , T. Kociniewski , Z. Khatir","doi":"10.1016/j.microrel.2025.115952","DOIUrl":"10.1016/j.microrel.2025.115952","url":null,"abstract":"<div><div>In this paper, we improved the signal-to-noise ratio (S/N) of thermoreflectance images of trench Insulated Gate Bipolar Transistors (IGBT) particularly in low-intensity areas caused by insufficient illumination or defocusing due to topography and depth variations within these components. To enhance and homogenize signal intensity across the entire surface, we accurately determined the focal planes and optimal lighting conditions for each region. Then, before performing reflectivity calculations, we reconstructed a single high intensity optical image by selecting pixels based on their local focus values. This optical image reconstruction ensures a uniform distribution of maximum intensity across the image and significantly improvises the S/N ratio minimizing artifacts in the final reflectivity map.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115952"},"PeriodicalIF":1.9,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145618428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-22DOI: 10.1016/j.microrel.2025.115959
Suleiman Ibrahim Mohammad , Asokan Vasudevan , S. Sujai , Premananda Pradhan , Nivin Joy Thykattusserry , Ripendeep Singh , Yashwant Singh Bisht
This work investigates the combined effects of cobalt (Co) nanoparticle incorporation and magnetic field-assisted reflow processing on the microstructure and fatigue reliability of eutectic 42Sn58Bi solder joints. A set of six sample groups was prepared to independently and jointly assess the influence of 0.8 wt% Co reinforcement, application of a 1.0 T magnetic field, and thermal cycling. The results show that Co nanoparticles refine the eutectic lamellae and suppress intermetallic compound (IMC) coarsening at the interface, while magnetic field-assisted reflow enhances nanoparticle dispersion and produces a fine, honeycomb-like microstructure. After thermal cycling, unreinforced joints exhibited severe coarsening, localized strain accumulation, and brittle fracture, whereas Co nanoparticle-reinforced samples retained greater microstructural stability but showed moderate resistance to fatigue degradation. In contrast, joints fabricated using the combined Co + magnetic field approach maintained a uniformly refined microstructure, distributed stresses more evenly, and demonstrated enhanced hardness, strength, and ductility during prolonged cycling. These findings underscore the strong interdependence among nanoparticle dispersion, IMC evolution, and cyclic deformation behavior, offering a promising strategy for developing durable SnBi solder joints for advanced electronic packaging where thermal and mechanical reliability are paramount.
{"title":"Enhanced fatigue reliability of SnBi solder joints through integrated cobalt nanoparticle reinforcement and magnetic field-assisted reflow","authors":"Suleiman Ibrahim Mohammad , Asokan Vasudevan , S. Sujai , Premananda Pradhan , Nivin Joy Thykattusserry , Ripendeep Singh , Yashwant Singh Bisht","doi":"10.1016/j.microrel.2025.115959","DOIUrl":"10.1016/j.microrel.2025.115959","url":null,"abstract":"<div><div>This work investigates the combined effects of cobalt (Co) nanoparticle incorporation and magnetic field-assisted reflow processing on the microstructure and fatigue reliability of eutectic 42Sn<img>58Bi solder joints. A set of six sample groups was prepared to independently and jointly assess the influence of 0.8 wt% Co reinforcement, application of a 1.0 T magnetic field, and thermal cycling. The results show that Co nanoparticles refine the eutectic lamellae and suppress intermetallic compound (IMC) coarsening at the interface, while magnetic field-assisted reflow enhances nanoparticle dispersion and produces a fine, honeycomb-like microstructure. After thermal cycling, unreinforced joints exhibited severe coarsening, localized strain accumulation, and brittle fracture, whereas Co nanoparticle-reinforced samples retained greater microstructural stability but showed moderate resistance to fatigue degradation. In contrast, joints fabricated using the combined Co + magnetic field approach maintained a uniformly refined microstructure, distributed stresses more evenly, and demonstrated enhanced hardness, strength, and ductility during prolonged cycling. These findings underscore the strong interdependence among nanoparticle dispersion, IMC evolution, and cyclic deformation behavior, offering a promising strategy for developing durable Sn<img>Bi solder joints for advanced electronic packaging where thermal and mechanical reliability are paramount.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115959"},"PeriodicalIF":1.9,"publicationDate":"2025-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-20DOI: 10.1016/j.microrel.2025.115958
Hao Zhang , Zixue Jiang , Luntao Wang , Yao Tan , Xiaowen Song , Chao Li , Jialiang Song , Hao Yu , Junsheng Wu , Kui Xiao
Electrochemical migration (ECM) has become a major reliability concern in miniaturized and high-density electronic components, particularly under damp-heat and condensation environments. This study comparatively investigates the ECM behavior of chip resistors exposed to these two moisture regimes. After applying a 6 V bias voltage for 30 min under damp-heat atmospheres with 60 %, 70 %, and 80 % relative humidity, no significant signs of corrosion were observed at the resistor terminals. In damp-heat conditions (up to 90 % RH), the anode underwent gradual Sn oxidation dominated by Sn4+ species, yet no dendritic structures were observed due to the absence of a continuous electrolyte film. In contrast, condensation environments (RH > 60 %) facilitated the formation of a continuous liquid layer, leading to rapid ECM initiation and the growth of Sn-based dendrites enriched in Sn2+ species. Furthermore, as the relative humidity increased, the degree of corrosion at both ends of the resistor became more severe correspondingly. At 90 % RH, simultaneous anodic darkening and aggravated corrosion were observed, confirming the accelerated redox processes within the condensed electrolyte. The results demonstrate that ECM failure occurs only when both a continuous electrolyte film and an external bias potential coexist, providing new insights into moisture-induced reliability degradation of surface-mount components.
{"title":"Mechanisms of electrochemical migration in damp-heat and dew-condensation environments of chip resistors","authors":"Hao Zhang , Zixue Jiang , Luntao Wang , Yao Tan , Xiaowen Song , Chao Li , Jialiang Song , Hao Yu , Junsheng Wu , Kui Xiao","doi":"10.1016/j.microrel.2025.115958","DOIUrl":"10.1016/j.microrel.2025.115958","url":null,"abstract":"<div><div>Electrochemical migration (ECM) has become a major reliability concern in miniaturized and high-density electronic components, particularly under damp-heat and condensation environments. This study comparatively investigates the ECM behavior of chip resistors exposed to these two moisture regimes. After applying a 6 V bias voltage for 30 min under damp-heat atmospheres with 60 %, 70 %, and 80 % relative humidity, no significant signs of corrosion were observed at the resistor terminals. In damp-heat conditions (up to 90 % RH), the anode underwent gradual Sn oxidation dominated by Sn<sup>4+</sup> species, yet no dendritic structures were observed due to the absence of a continuous electrolyte film. In contrast, condensation environments (RH > 60 %) facilitated the formation of a continuous liquid layer, leading to rapid ECM initiation and the growth of Sn-based dendrites enriched in Sn<sup>2+</sup> species. Furthermore, as the relative humidity increased, the degree of corrosion at both ends of the resistor became more severe correspondingly. At 90 % RH, simultaneous anodic darkening and aggravated corrosion were observed, confirming the accelerated redox processes within the condensed electrolyte. The results demonstrate that ECM failure occurs only when both a continuous electrolyte film and an external bias potential coexist, providing new insights into moisture-induced reliability degradation of surface-mount components.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115958"},"PeriodicalIF":1.9,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-19DOI: 10.1016/j.microrel.2025.115957
Jonghyeon Ha, Minki Suh, Minsang Ryu, Dabok Lee, Dae-Young Jeon, Jungsik Kim
In this study, the effects of gamma-ray irradiation on fully depleted silicon on insulator (FD-SOI) Nanowire FETs (NWFETs) at different irradiation temperatures (265, 300, and 400 K) were analyzed. For PMOS, positive threshold shift (ΔVth) owing to interface and oxide traps could be observed regardless of the irradiation temperature. However, NMOS showed a different temperature trend. At 400 K, the oxide traps were cured during annealing, enhancing the influence of interface traps and resulting in a positive ΔVth. In comparison, at 265 K, the oxide traps became more influential due to reduced hole mobility in the buried oxide (BOX), resulting in a negative ΔVth. Annealing was performed at room temperature for 24 and 168 h to investigate the ΔVth owing to the annealing effect (ΔVth-anneal). In NMOS, a positive ΔVth-anneal occurred regardless of width (W) as the oxide traps were cured by annealing. PMOS showed a negative ΔVth-anneal regardless of W.
{"title":"Radiation effect in FD-SOI nanowire FETs due to high dose rate gamma-ray under variable irradiation temperatures","authors":"Jonghyeon Ha, Minki Suh, Minsang Ryu, Dabok Lee, Dae-Young Jeon, Jungsik Kim","doi":"10.1016/j.microrel.2025.115957","DOIUrl":"10.1016/j.microrel.2025.115957","url":null,"abstract":"<div><div>In this study, the effects of gamma-ray irradiation on fully depleted silicon on insulator (FD-SOI) Nanowire FETs (NWFETs) at different irradiation temperatures (265, 300, and 400 K) were analyzed. For PMOS, positive threshold shift (<em>ΔV</em><sub><em>th</em></sub>) owing to interface and oxide traps could be observed regardless of the irradiation temperature. However, NMOS showed a different temperature trend. At 400 K, the oxide traps were cured during annealing, enhancing the influence of interface traps and resulting in a positive <em>ΔV</em><sub><em>th</em></sub>. In comparison, at 265 K, the oxide traps became more influential due to reduced hole mobility in the buried oxide (BOX), resulting in a negative <em>ΔV</em><sub><em>th</em></sub>. Annealing was performed at room temperature for 24 and 168 h to investigate the <em>ΔV</em><sub><em>th</em></sub> owing to the annealing effect (<em>ΔV</em><sub><em>th-anneal</em></sub>). In NMOS, a positive <em>ΔV</em><sub><em>th-anneal</em></sub> occurred regardless of width (<em>W)</em> as the oxide traps were cured by annealing. PMOS showed a negative <em>ΔV</em><sub><em>th-anneal</em></sub> regardless of <em>W</em>.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115957"},"PeriodicalIF":1.9,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145571985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-18DOI: 10.1016/j.microrel.2025.115955
Xufang Zhang , Mingkun Li , Shihao Lu , Shuopei Jiao , Shichao Wang , Pengyu Li , Zhiwei Jiao , Kang An , Hong Dong , Wei Wang , Jing Zhang
The performance of diamond-based Schottky barrier diodes (SBDs) is often limited by poor understanding of Schottky interfaces due to the existence of a native interlayer. Specifically, it is difficult to characterize the dielectric constant and thickness of the interlayer by conventional methods. In this work, we established an equivalent circuit model based on high-frequency capacitance–voltage (C–V) characteristics, thereby directly extracting the interlayer capacitance (Ci) and circumventing the challenge of determining the dielectric constant and thickness. Furthermore, the voltage-dependent ideality factor (n (V)) was evaluated based on current–voltage (I–V) characteristics under forward biases. By combining the Ci and n (V) extraction, the energy distribution of interface state density (Dit) was evaluated for the LaB6/H-diamond SBD, ranging from approximately 4 × 1013 to 1.2 × 1014 cm−2 eV−1 in the energy levels of 0.2 to 0.5 eV from the valence band edge (Ev) of diamond. This work provides a novel technique to characterize Dit profile for diamond SBDs, which would be beneficial for the future improvement of device performances.
{"title":"Interlayer capacitance extraction for profiling interface states in LaB₆/H-diamond Schottky diodes","authors":"Xufang Zhang , Mingkun Li , Shihao Lu , Shuopei Jiao , Shichao Wang , Pengyu Li , Zhiwei Jiao , Kang An , Hong Dong , Wei Wang , Jing Zhang","doi":"10.1016/j.microrel.2025.115955","DOIUrl":"10.1016/j.microrel.2025.115955","url":null,"abstract":"<div><div>The performance of diamond-based Schottky barrier diodes (SBDs) is often limited by poor understanding of Schottky interfaces due to the existence of a native interlayer. Specifically, it is difficult to characterize the dielectric constant and thickness of the interlayer by conventional methods. In this work, we established an equivalent circuit model based on high-frequency capacitance–voltage (<em>C</em>–<em>V</em>) characteristics, thereby directly extracting the interlayer capacitance (<em>C</em><sub>i</sub>) and circumventing the challenge of determining the dielectric constant and thickness. Furthermore, the voltage-dependent ideality factor (<em>n</em> (<em>V</em>)) was evaluated based on current–voltage (<em>I</em>–<em>V</em>) characteristics under forward biases. By combining the <em>C</em><sub>i</sub> and <em>n</em> (<em>V</em>) extraction, the energy distribution of interface state density (<em>D</em><sub>it</sub>) was evaluated for the LaB<sub>6</sub>/H-diamond SBD, ranging from approximately 4 × 10<sup>13</sup> to 1.2 × 10<sup>14</sup> cm<sup>−2</sup> eV<sup>−1</sup> in the energy levels of 0.2 to 0.5 eV from the valence band edge (<em>E</em><sub>v</sub>) of diamond. This work provides a novel technique to characterize <em>D</em><sub>it</sub> profile for diamond SBDs, which would be beneficial for the future improvement of device performances.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"176 ","pages":"Article 115955"},"PeriodicalIF":1.9,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145536917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-17DOI: 10.1016/j.microrel.2025.115954
Pushpa Rajaguru
This report focuses on the estimation of Anand viscoplastic model parameters for aluminium wirebonds, a critical component in Power Electronic Modules (PEMs). These complex PEM inhomogeneous structures are prone to thermo-mechanical failure due to heat generation and material Coefficient of Thermal Expansion (CTE) mismatches. The wirebond failures account for approximately 70 % of total PEM failures. The study addresses a gap in existing literature by deriving Anand model parameters for aluminium wirebonds from experimental tensile data. This involved of conducting isothermal uniaxial tensile tests on pure aluminium wire at various temperatures and strain rates and measuring the stress strain profile of each sample specimens. The nine Anand model parameters were then determined through a four-step non-linear fitting process. The accuracy of these estimated parameters was validated by comparing stress-strain curves from Finite Element Analysis (FEA) simulations with experimental data, showing a good fit across various conditions. The research proceeded to predict the fatigue lifetime of wirebond structures under various thermal cyclic loading scenarios, adhering to JEDEC standards. Accumulated plastic strain at the wirebond heel was identified as a key lifetime prediction parameter, utilizing the Coffin-Manson relationship. The analysis revealed an exponential decrease in wirebond lifetime with increasing temperature difference (ΔT) and upper thermal cycle temperature. Finally, the study explored using tree-based machine learning (ML) regressors (Random Forest, Decision Tree, and XGBoost) to predict accumulated plastic strain, aiming to mitigate the need for computationally expensive FEA simulations. Trained on a small dataset from 11 FEA simulations, the Decision Tree model exhibited a reasonable prediction error of 2.4 %, suggesting the potential for ML to provide efficient and reasonably accurate lifetime predictions in power electronics.
{"title":"Anand model parameter estimation for the aluminium wirebond in power electronic module and lifetime prediction by combining the finite element analysis and machine learning","authors":"Pushpa Rajaguru","doi":"10.1016/j.microrel.2025.115954","DOIUrl":"10.1016/j.microrel.2025.115954","url":null,"abstract":"<div><div>This report focuses on the estimation of Anand viscoplastic model parameters for aluminium wirebonds, a critical component in Power Electronic Modules (PEMs). These complex PEM inhomogeneous structures are prone to thermo-mechanical failure due to heat generation and material Coefficient of Thermal Expansion (CTE) mismatches. The wirebond failures account for approximately 70 % of total PEM failures. The study addresses a gap in existing literature by deriving Anand model parameters for aluminium wirebonds from experimental tensile data. This involved of conducting isothermal uniaxial tensile tests on pure aluminium wire at various temperatures and strain rates and measuring the stress strain profile of each sample specimens. The nine Anand model parameters were then determined through a four-step non-linear fitting process. The accuracy of these estimated parameters was validated by comparing stress-strain curves from Finite Element Analysis (FEA) simulations with experimental data, showing a good fit across various conditions. The research proceeded to predict the fatigue lifetime of wirebond structures under various thermal cyclic loading scenarios, adhering to JEDEC standards. Accumulated plastic strain at the wirebond heel was identified as a key lifetime prediction parameter, utilizing the Coffin-Manson relationship. The analysis revealed an exponential decrease in wirebond lifetime with increasing temperature difference (ΔT) and upper thermal cycle temperature. Finally, the study explored using tree-based machine learning (ML) regressors (Random Forest, Decision Tree, and XGBoost) to predict accumulated plastic strain, aiming to mitigate the need for computationally expensive FEA simulations. Trained on a small dataset from 11 FEA simulations, the Decision Tree model exhibited a reasonable prediction error of 2.4 %, suggesting the potential for ML to provide efficient and reasonably accurate lifetime predictions in power electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115954"},"PeriodicalIF":1.9,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145578951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As crucial packaging components of insulated gate bipolar transistor (IGBT) power modules, bonding wires are often confronted with strong load current from tens to hundreds of amperes. Thus, the reliability issues of bonding wires induced by electrical-mechanical coupling stress have become increasingly prominent. Nevertheless, the current mainstream research focuses on the reliability issues of bonding wires caused by electrical-thermal-mechanical (ETM) coupling stress, while neglecting electrical-magnetic-mechanical (EMM) coupling stress. In this article, for the first time, an in-depth investigation of EMM coupling stress of bonding wires in IGBT packaging modules is demonstrated by finite element simulation. The results indicate that the EMM coupling stress is mainly concentrated on the heel interfaces of bonding wires, presenting significantly quadratic and positive correlation with the intensity of load current. Furthermore, it is found that the stress fluctuation of bonding wires caused by EMM coupling is much larger than that caused by ETM coupling when IGBT modules operate at high switching frequency, providing confident evidence that the EMM stress on the bonding wires cannot be casually neglected and should be carefully taken into consideration. This work is bound to bring new insights and inspirations to electrical-mechanical coupling related reliability evaluation in power electronic devices.
{"title":"Electrical-magnetic-mechanical coupling stress of bonding wires in IGBT packaging modules","authors":"Cong Chen, Yuxin Luo, Jiahao Wang, Chaoyue Song, Bo Xu, Libing Bai, Yuhua Cheng","doi":"10.1016/j.microrel.2025.115953","DOIUrl":"10.1016/j.microrel.2025.115953","url":null,"abstract":"<div><div>As crucial packaging components of insulated gate bipolar transistor (IGBT) power modules, bonding wires are often confronted with strong load current from tens to hundreds of amperes. Thus, the reliability issues of bonding wires induced by electrical-mechanical coupling stress have become increasingly prominent. Nevertheless, the current mainstream research focuses on the reliability issues of bonding wires caused by electrical-thermal-mechanical (ETM) coupling stress, while neglecting electrical-magnetic-mechanical (EMM) coupling stress. In this article, for the first time, an in-depth investigation of EMM coupling stress of bonding wires in IGBT packaging modules is demonstrated by finite element simulation. The results indicate that the EMM coupling stress is mainly concentrated on the heel interfaces of bonding wires, presenting significantly quadratic and positive correlation with the intensity of load current. Furthermore, it is found that the stress fluctuation of bonding wires caused by EMM coupling is much larger than that caused by ETM coupling when IGBT modules operate at high switching frequency, providing confident evidence that the EMM stress on the bonding wires cannot be casually neglected and should be carefully taken into consideration. This work is bound to bring new insights and inspirations to electrical-mechanical coupling related reliability evaluation in power electronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115953"},"PeriodicalIF":1.9,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145578949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-15DOI: 10.1016/j.microrel.2025.115949
Waseem Abbas , Chang Lu , Yuluo Hou , Qian Xia , Ghulam Abbas Khan , Hiu Hung Lee , K.H. Loo
The reliability of Intelligent Power Modules (IPMs), critical for electric-vehicles (EVs), renewable-energy systems, and industrial-automation, is compromised by process-induced voids in die-attach joints. Previous research has investigated the thermo-mechanical behavior of solders/die-attach containing manufacturing induced voids, often by artificially creating excessive voids through simulation-analysis without sufficient experimental validation. Current electronic packages assembly standards, including IPC-A-610H, J-STD-001H, and IEC 61191–2, discontinue address voiding on account of conflicting perspectives and a lack of sufficient empirical findings. Given the lack of experimental evidence and conflicting industry perspectives, comprehensive data is essential to bridge this gap and refine void inspection standards. To address this critical issue, two commercially available 6-packed Insulated-Gate Bipolar Transistor (IGBT) IPM packages from different brands, featuring varying sizes and patterns of pre-existing die-attach voids, were selected. Two IGBTs from each brand were subjected to accelerated degradation testing based on power-cycling under identical stress levels, with the locality and frequency of solder/die-attach degradation monitored at certain intervals. Experimental observations reveal that small, distributive voids with specific patterns in solder joints exhibit negligible impact on die-attach degradation. Furthermore, these voids exhibit potential self-healing capabilities under moderate thermo-mechanical stress when Sn-based soldering materials are utilized. Conversely, large, dispersive voids without a specific pattern initiate solder damage and significantly reduce solder lifespan. Our findings highlight the need to consider void size and pattern in solder void inspection standards to improve power-device reliability. This study also provides the first experimental validation of self-healing in Sn-based solders under real-world power-cycling conditions, moving beyond previous simulations and theoretical analyses. This approach would enhance the reliability of power-devices for end user power-supply and management applications.
{"title":"Self-healing solder joints in power electronics: Experimental validation of die-attach void effects on reliability","authors":"Waseem Abbas , Chang Lu , Yuluo Hou , Qian Xia , Ghulam Abbas Khan , Hiu Hung Lee , K.H. Loo","doi":"10.1016/j.microrel.2025.115949","DOIUrl":"10.1016/j.microrel.2025.115949","url":null,"abstract":"<div><div>The reliability of Intelligent Power Modules (IPMs), critical for electric-vehicles (EVs), renewable-energy systems, and industrial-automation, is compromised by process-induced voids in die-attach joints. Previous research has investigated the thermo-mechanical behavior of solders/die-attach containing manufacturing induced voids, often by artificially creating excessive voids through simulation-analysis without sufficient experimental validation. Current electronic packages assembly standards, including IPC-A-610H, J-STD-001H, and IEC 61191–2, discontinue address voiding on account of conflicting perspectives and a lack of sufficient empirical findings. Given the lack of experimental evidence and conflicting industry perspectives, comprehensive data is essential to bridge this gap and refine void inspection standards. To address this critical issue, two commercially available 6-packed Insulated-Gate Bipolar Transistor (IGBT) IPM packages from different brands, featuring varying sizes and patterns of pre-existing die-attach voids, were selected. Two IGBTs from each brand were subjected to accelerated degradation testing based on power-cycling under identical stress levels, with the locality and frequency of solder/die-attach degradation monitored at certain intervals. Experimental observations reveal that small, distributive voids with specific patterns in solder joints exhibit negligible impact on die-attach degradation. Furthermore, these voids exhibit potential self-healing capabilities under moderate thermo-mechanical stress when Sn-based soldering materials are utilized. Conversely, large, dispersive voids without a specific pattern initiate solder damage and significantly reduce solder lifespan. Our findings highlight the need to consider void size and pattern in solder void inspection standards to improve power-device reliability. This study also provides the first experimental validation of self-healing in Sn-based solders under real-world power-cycling conditions, moving beyond previous simulations and theoretical analyses. This approach would enhance the reliability of power-devices for end user power-supply and management applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115949"},"PeriodicalIF":1.9,"publicationDate":"2025-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1016/j.microrel.2025.115948
Chieh-Chen Ker , Chun-Yu Lin , Ming-Duo Ker , Yu-Hsuan Chang , Ching-Wei Li , Tsung-Yin Chiang , Chun-Chi Wang
A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.
{"title":"Gate-to-source ESD protection design for GaN-on-silicon power HEMT","authors":"Chieh-Chen Ker , Chun-Yu Lin , Ming-Duo Ker , Yu-Hsuan Chang , Ching-Wei Li , Tsung-Yin Chiang , Chun-Chi Wang","doi":"10.1016/j.microrel.2025.115948","DOIUrl":"10.1016/j.microrel.2025.115948","url":null,"abstract":"<div><div>A monolithic integrated bidirectional gate-to-source ESD protection circuit for power high-electron-mobility transistor (HEMT) in GaN-on-Si process is proposed. The proposed circuit is incorporated with a voltage detection mechanism to ensure that the ESD protection circuit is selectively activated only under ESD stress conditions, thereby minimizing the unwanted interference and standby leakage current during normal device operation. It has been demonstrated that the proposed design can significantly enhance the robustness against ESD events with human-body-model (HBM) ESD level exceeding ±8 kV and IEC ESD level beyond ±2.5 kV.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115948"},"PeriodicalIF":1.9,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145528247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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