Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115571
C. Scognamillo , A.P. Catalano , L. Codecasa , A. Castellazzi , V. d'Alessandro
This work investigates the ruggedness of paralleled silicon carbide (SiC) MOSFETs tested under unclamped inductive switching (UIS) conditions. More specifically, the maximum avalanche energy (EAV) sustainable by individual and paralleled MOSFETs integrated in a multi-chip power module (PM) is quantified. Circuital electrothermal (ET) simulations are carried out by resorting to a physics-based electrical model of a commercial SiC power MOSFET coupled with a dynamic thermal feedback block (TFB). The electrical model of the power MOSFET, accounting for temperature-sensitive parameters, was calibrated on measurements data of transfer /output characteristics and of UIS tests. The TFB was extracted using FANTASTIC, an advanced numerical tool based on a model-order reduction technique; it accounts for self- and mutual-heating of devices, including nonlinear thermal effects. A comprehensive analysis of the system ruggedness was performed by focusing on (i) mutual heating mechanisms between transistors and (ii) technological mismatches in breakdown voltage (BV).
{"title":"A study of UIS ruggedness of mismatched paralleled SiC MOSFETs","authors":"C. Scognamillo , A.P. Catalano , L. Codecasa , A. Castellazzi , V. d'Alessandro","doi":"10.1016/j.microrel.2024.115571","DOIUrl":"10.1016/j.microrel.2024.115571","url":null,"abstract":"<div><div>This work investigates the ruggedness of paralleled silicon carbide (SiC) MOSFETs tested under unclamped inductive switching (UIS) conditions. More specifically, the maximum avalanche energy (E<sub>AV</sub>) sustainable by individual and paralleled MOSFETs integrated in a multi-chip power module (PM) is quantified. Circuital electrothermal (ET) simulations are carried out by resorting to a physics-based electrical model of a commercial SiC power MOSFET coupled with a dynamic thermal feedback block (TFB). The electrical model of the power MOSFET, accounting for temperature-sensitive parameters, was calibrated on measurements data of transfer /output characteristics and of UIS tests. The TFB was extracted using FANTASTIC, an advanced numerical tool based on a model-order reduction technique; it accounts for self- and mutual-heating of devices, including nonlinear thermal effects. A comprehensive analysis of the system ruggedness was performed by focusing on (i) mutual heating mechanisms between transistors and (ii) technological mismatches in breakdown voltage (BV).</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115571"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115572
Jianmin Yi , Cunbao Ma , Hao Wang , Hao Ma
This paper is dedicated to exploring the application of prognostics and health management (PHM) technique to electrically erasable programmable read only memory (EEPROM) devices. Although the reliability problems of memory devices have attracted extensive attention and research, PHM technique which enables efficient reliability assurance for such devices is relatively rare. In order to promote the implementation of PHM technique in such devices, this work demonstrates a radial basis function (RBF) network-based health monitoring and prediction method for EEPROM devices. Firstly, health indicators and the underlying degradation mechanism are analyzed. Subsequently, an equivalent circuit is developed to model the degradation process. Afterwards, an experimental data set of EEPROM degradation is adopted as a case study to carry out the research. Based on RBF neural network, the health monitoring and prediction frameworks are presented. To quantitatively evaluate the model, mean squared error (MSE) and relative accuracy (RA) are selected as the performance metrics. Finally, desirable results have been obtained through HI estimation and RUL prediction using the proposed model, which confirm the validity and practicability of the proposed methodology. This work throws light on the PHM-based reliability technology for memory devices and other digital electronics.
{"title":"Health monitoring and prediction of EEPROM considering program/erase endurance and data retention stress","authors":"Jianmin Yi , Cunbao Ma , Hao Wang , Hao Ma","doi":"10.1016/j.microrel.2024.115572","DOIUrl":"10.1016/j.microrel.2024.115572","url":null,"abstract":"<div><div>This paper is dedicated to exploring the application of prognostics and health management (PHM) technique to electrically erasable programmable read only memory (EEPROM) devices. Although the reliability problems of memory devices have attracted extensive attention and research, PHM technique which enables efficient reliability assurance for such devices is relatively rare. In order to promote the implementation of PHM technique in such devices, this work demonstrates a radial basis function (RBF) network-based health monitoring and prediction method for EEPROM devices. Firstly, health indicators and the underlying degradation mechanism are analyzed. Subsequently, an equivalent circuit is developed to model the degradation process. Afterwards, an experimental data set of EEPROM degradation is adopted as a case study to carry out the research. Based on RBF neural network, the health monitoring and prediction frameworks are presented. To quantitatively evaluate the model, mean squared error (MSE) and relative accuracy (RA) are selected as the performance metrics. Finally, desirable results have been obtained through HI estimation and RUL prediction using the proposed model, which confirm the validity and practicability of the proposed methodology. This work throws light on the PHM-based reliability technology for memory devices and other digital electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115572"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115567
Lilin Wang , Chunyue Huang , Lixiang Huang , Ying Liang , Chao Gao , Xianjia Liu , Zhiqin Cao
An ANSYS and HFSS-based 3D-TSV stacked-chip packaging interconnection structure simulation analysis model was established to conduct thermal-structural coupling analysis, random vibration loading analysis, and echo loss analysis. The regression equations for thermal-structural coupling stress, random vibration stress, and echo loss were derived using the response surface method. The multi-objective optimization of the TSV interconnection structure was performed using the NSWOA optimization algorithm. The weights of thermal-structural coupling stress, random vibration stress, and echo loss were calculated using entropy weight theory, and the optimal solution set was ranked using the rank-sum ratio method. The optimal parameter combination was obtained. The results indicate that under thermal-structural coupling loading, the maximum stress and strain of the TSV interconnection structure are located at the contact surface between the upper copper pillar and the topmost microbump. Under random vibration loading, the maximum stress occurs at the contact surface between the lower copper pillar and the lowermost microbump, while the maximum strain appears on the lowermost microbump. Under high-frequency conditions, the echo loss increases with the increase in frequency. The comprehensive optimization rate of the optimized results obtained using the NSWOA optimization algorithm reaches a maximum of 27.28%, achieving multi-objective optimization of the TSV interconnection structure.
{"title":"Multi-objective optimal design of thermal-vibration stress and return loss of TSV interconnect structures based on response surface-NSWOA optimization algorithm","authors":"Lilin Wang , Chunyue Huang , Lixiang Huang , Ying Liang , Chao Gao , Xianjia Liu , Zhiqin Cao","doi":"10.1016/j.microrel.2024.115567","DOIUrl":"10.1016/j.microrel.2024.115567","url":null,"abstract":"<div><div>An ANSYS and HFSS-based 3D-TSV stacked-chip packaging interconnection structure simulation analysis model was established to conduct thermal-structural coupling analysis, random vibration loading analysis, and echo loss analysis. The regression equations for thermal-structural coupling stress, random vibration stress, and echo loss were derived using the response surface method. The multi-objective optimization of the TSV interconnection structure was performed using the NSWOA optimization algorithm. The weights of thermal-structural coupling stress, random vibration stress, and echo loss were calculated using entropy weight theory, and the optimal solution set was ranked using the rank-sum ratio method. The optimal parameter combination was obtained. The results indicate that under thermal-structural coupling loading, the maximum stress and strain of the TSV interconnection structure are located at the contact surface between the upper copper pillar and the topmost microbump. Under random vibration loading, the maximum stress occurs at the contact surface between the lower copper pillar and the lowermost microbump, while the maximum strain appears on the lowermost microbump. Under high-frequency conditions, the echo loss increases with the increase in frequency. The comprehensive optimization rate of the optimized results obtained using the NSWOA optimization algorithm reaches a maximum of 27.28%, achieving multi-objective optimization of the TSV interconnection structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115567"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115566
Zhenzhen Peng , Yunjia Li , Yuzhong Rao , Xinyu Zhao , Zhimin Liang , Xiao Yang
In this study, the microstructural evolution and the shear strengths of the nano-silver microsolder joint under cycling conditions ranging from −65 °C to 150 °C have been investigated. The results indicate that thermal cycling does not alter the macro morphology of the nano-silver microsolder joint, with the Ag-Au connection interface showing no defects or delamination, maintaining excellent connection quality. However, the thickness of the Ag-Au solid solution layer decreases notably with an increase in thermal cycles, demonstrating a clear parabolic relationship with the square root of the number of cycles, which is consistent with Fick's second law. As thermal cycles increase, the porosity of the low-temperature sintered nano-silver microsolder joint rises by 21.7 %, from 0.46 to 0.56. Fractures occurred in the sintered nano-silver layer during shear tests in the samples before and after cycling, exhibiting plastic fracture behavior. The shear strength changes little during 0–400 thermal cycles but decreases abruptly after 500 thermal cycles. It can be concluded that localized stress concentrations at the boundaries of the nano-silver microsolder joint and the resulting nucleated microcavities caused the dramatic decrease of shear strength after 500 thermal cycling.
{"title":"Effect of thermal cycling on microstructure and mechanical properties of nano-silver microsolder joint","authors":"Zhenzhen Peng , Yunjia Li , Yuzhong Rao , Xinyu Zhao , Zhimin Liang , Xiao Yang","doi":"10.1016/j.microrel.2024.115566","DOIUrl":"10.1016/j.microrel.2024.115566","url":null,"abstract":"<div><div>In this study, the microstructural evolution and the shear strengths of the nano-silver microsolder joint under cycling conditions ranging from −65 °C to 150 °C have been investigated. The results indicate that thermal cycling does not alter the macro morphology of the nano-silver microsolder joint, with the Ag-Au connection interface showing no defects or delamination, maintaining excellent connection quality. However, the thickness of the Ag-Au solid solution layer decreases notably with an increase in thermal cycles, demonstrating a clear parabolic relationship with the square root of the number of cycles, which is consistent with Fick's second law. As thermal cycles increase, the porosity of the low-temperature sintered nano-silver microsolder joint rises by 21.7 %, from 0.46 to 0.56. Fractures occurred in the sintered nano-silver layer during shear tests in the samples before and after cycling, exhibiting plastic fracture behavior. The shear strength changes little during 0–400 thermal cycles but decreases abruptly after 500 thermal cycles. It can be concluded that localized stress concentrations at the boundaries of the nano-silver microsolder joint and the resulting nucleated microcavities caused the dramatic decrease of shear strength after 500 thermal cycling.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115566"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115555
Lukas Sommeregger , Jürgen Pilz
Semiconductors are widely used in various applications and critical infrastructures. These devices have specified lifetimes and quality targets that manufacturers must achieve. Lifetime estimation is conducted through accelerated stress tests. Electrical parameters are measured at multiple times during a stress test procedure. The change in these Electrical parameters is called lifetime drift. Data from these tests can be used to develop a statistical model predicting the lifetime behavior of the electrical parameters in real devices. These models can provide early warnings in production processes, identify critical parameter drift, and detect outliers.
While models for continuous electrical parameters exists, there may be bias when estimating the lifetime of discrete parameters. To address this, we propose a semi-parametric model for degradation trajectories based on longitudinal stress test data. This model optimizes guard bands, or quality-guaranteeing tighter limits, for discrete electrical parameters at production testing. It is scalable, data-driven, and explainable, offering improvements over existing methods for continuous underlying data, such as faster calculations, arbitrary non-parametric conditional distribution modeling, and a natural extension of optimization algorithms to the discrete case using Markov transition matrices.
{"title":"Quality control of lifetime drift in discrete electrical parameters in semiconductor devices via transition modeling","authors":"Lukas Sommeregger , Jürgen Pilz","doi":"10.1016/j.microrel.2024.115555","DOIUrl":"10.1016/j.microrel.2024.115555","url":null,"abstract":"<div><div>Semiconductors are widely used in various applications and critical infrastructures. These devices have specified lifetimes and quality targets that manufacturers must achieve. Lifetime estimation is conducted through accelerated stress tests. Electrical parameters are measured at multiple times during a stress test procedure. The change in these Electrical parameters is called lifetime drift. Data from these tests can be used to develop a statistical model predicting the lifetime behavior of the electrical parameters in real devices. These models can provide early warnings in production processes, identify critical parameter drift, and detect outliers.</div><div>While models for continuous electrical parameters exists, there may be bias when estimating the lifetime of discrete parameters. To address this, we propose a semi-parametric model for degradation trajectories based on longitudinal stress test data. This model optimizes guard bands, or quality-guaranteeing tighter limits, for discrete electrical parameters at production testing. It is scalable, data-driven, and explainable, offering improvements over existing methods for continuous underlying data, such as faster calculations, arbitrary non-parametric conditional distribution modeling, and a natural extension of optimization algorithms to the discrete case using Markov transition matrices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115555"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-01DOI: 10.1016/j.microrel.2024.115569
Shuqing Sun , Feida Chen , Yongbo Sun , Yongxing Li , Kun Yang , Xiaobin Tang
This study investigates the structural optimization of 650 V Silicon carbide (SiC) Double-Trench MOSFETs (DTMOSFETs) aimed at enhancing their resilience against Single Event Burnout (SEB) and Single Event Gate Rupture (SEGR), while preserving the fundamental performance of the devices. Proposing a novel approach that combines an increase in P-well doping concentration with the design of multiple buffer layers can achieve a reduction in lattice temperature and a more uniform temperature distribution, thereby enhancing hardening capability. Additionally, substituting the conventional SiO2 with high-k gate dielectric materials effectively reduces the maximum electric field intensity within the gate oxide layer. The improvement effect is determined by the size of the dielectric constant, and the larger the dielectric constant, the better the improvement effect. These hardening methods can considerably improve the Single Event Effect (SEE), offering a theoretical foundation for optimizing the SEE of SiC DTMOSFETs, which hold great promise for future applications in aerospace industries.
{"title":"Single event effects hardening in SiC double-trench MOSFETs","authors":"Shuqing Sun , Feida Chen , Yongbo Sun , Yongxing Li , Kun Yang , Xiaobin Tang","doi":"10.1016/j.microrel.2024.115569","DOIUrl":"10.1016/j.microrel.2024.115569","url":null,"abstract":"<div><div>This study investigates the structural optimization of 650 V Silicon carbide (SiC) Double-Trench MOSFETs (DTMOSFETs) aimed at enhancing their resilience against Single Event Burnout (SEB) and Single Event Gate Rupture (SEGR), while preserving the fundamental performance of the devices. Proposing a novel approach that combines an increase in P-well doping concentration with the design of multiple buffer layers can achieve a reduction in lattice temperature and a more uniform temperature distribution, thereby enhancing hardening capability. Additionally, substituting the conventional SiO<sub>2</sub> with high-k gate dielectric materials effectively reduces the maximum electric field intensity within the gate oxide layer. The improvement effect is determined by the size of the dielectric constant, and the larger the dielectric constant, the better the improvement effect. These hardening methods can considerably improve the Single Event Effect (SEE), offering a theoretical foundation for optimizing the SEE of SiC DTMOSFETs, which hold great promise for future applications in aerospace industries.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115569"},"PeriodicalIF":1.6,"publicationDate":"2025-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143183446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As global demand for high-efficiency automotive electronics grows, enhanced heat dissipation and reliability are essential to meet the energy demands of high-computation applications. Void formation in solder joints poses significant challenges, reducing thermal conductivity and joint strength. In response, this study optimizes the vacuum reflow process parameters and stencil aperture design to mitigate voids in Quad Flat No-Lead (QFN) packages, which are widely adopted for their heat dissipation capabilities.
Using the Taguchi method, we determined the optimal stencil aperture shapes and reflow conditions for two thermal pad sizes in QFNs. For the large thermal pad (5.24 mm × 4.5 mm), the optimal parameters included a fence-type aperture covering 85 % of the pad area, vacuum pressure of 50 mbar, 10-s vacuum duration, and a fully open vacuum valve. For the small thermal pad (1.6 mm × 4.2 mm), optimal parameters were a fully covered aperture at 85 % of the pad area, 50 mbar vacuum pressure, 5-s vacuum duration, and fully open valve. Results demonstrated that these optimized conditions effectively reduced void ratios to 0.7 % for the large pad and 0.5 % for the small pad, meeting industry standards for automotive applications.
随着全球对高效汽车电子的需求不断增长，增强的散热和可靠性对于满足高计算应用的能源需求至关重要。焊点中的空洞形成带来了重大挑战，降低了导热性和接头强度。因此，本研究优化了真空回流工艺参数和模板孔径设计，以减少Quad Flat No-Lead （QFN）封装中的空隙，QFN封装因其散热能力而被广泛采用。采用田口法，确定了两种热垫尺寸下QFNs的最佳孔径形状和回流条件。对于大型热垫（5.24 mm × 4.5 mm），最优参数为栅栏型孔径占热垫面积的85%，真空压力为50 mbar，真空持续时间为10 s，真空阀为全开。对于小型热垫（1.6 mm × 4.2 mm），最佳参数为全覆盖孔径为垫面积的85%，真空压力为50 mbar，真空持续时间为5 s，阀门全开。结果表明，这些优化条件有效地将大衬垫的空隙率降低到0.7%，小衬垫的空隙率降低到0.5%，符合汽车应用的行业标准。
{"title":"Mitigating solder voids in quad flat no-lead components: A vacuum reflow approach","authors":"Chien-Yi Huang , Chao-Chieh Chan , Chih-Yang Weng , Amirhossein Nafei","doi":"10.1016/j.microrel.2024.115564","DOIUrl":"10.1016/j.microrel.2024.115564","url":null,"abstract":"<div><div>As global demand for high-efficiency automotive electronics grows, enhanced heat dissipation and reliability are essential to meet the energy demands of high-computation applications. Void formation in solder joints poses significant challenges, reducing thermal conductivity and joint strength. In response, this study optimizes the vacuum reflow process parameters and stencil aperture design to mitigate voids in Quad Flat No-Lead (QFN) packages, which are widely adopted for their heat dissipation capabilities.</div><div>Using the Taguchi method, we determined the optimal stencil aperture shapes and reflow conditions for two thermal pad sizes in QFNs. For the large thermal pad (5.24 mm × 4.5 mm), the optimal parameters included a fence-type aperture covering 85 % of the pad area, vacuum pressure of 50 mbar, 10-s vacuum duration, and a fully open vacuum valve. For the small thermal pad (1.6 mm × 4.2 mm), optimal parameters were a fully covered aperture at 85 % of the pad area, 50 mbar vacuum pressure, 5-s vacuum duration, and fully open valve. Results demonstrated that these optimized conditions effectively reduced void ratios to 0.7 % for the large pad and 0.5 % for the small pad, meeting industry standards for automotive applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115564"},"PeriodicalIF":1.6,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142759726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-30DOI: 10.1016/j.microrel.2024.115553
Xiaoyu An, Zhaoyuan Huang, Zhifeng Dou, Falong Lu, Qian Wang
Addressing the criticality of IGBT modules in power electronics and reliability challenges in industrial applications, this study focuses on solving the important problem of solder layer aging failure in IGBT modules. Under defined operating conditions, a specific set of electrical parameters, notably the collector-emitter saturation voltage Vce(sat) , serves as a critical indicator for monitoring the degradation of solder layers within IGBT modules. This parameter is indicative of potential solder layer aging failures, which can be identified and studied to predict and mitigate such failures effectively. In order to analyze the aging trend more deeply and accurately, a new nature-inspired meta-heuristic algorithm based on Crested Porcupine Optimizer is introduced. Combining multiple data during the operation of the IGBT module, such as gate voltage, gate current, heatsink temperature, case temperature, collector-emitter current, and Vce(sat), the parameter optimization is carried out by using CPO, and a prediction model based on the optimization of the SVR by CPO is established, which is successfully implemented to predict the accurate prediction of IGBT module solder layer lifetime. The study also validates the effectiveness of the CPO-SVR method on an accelerated aging dataset of IGBT modules provided by NASA Lab. The results of this research contribute to an in-depth understanding and prediction of the aging process of IGBT modules, which in turn improves the reliability and lifetime of the devices.
{"title":"Predicting aging of IGBT solder layer using saturation voltage approach with CPO-SVR data modeling","authors":"Xiaoyu An, Zhaoyuan Huang, Zhifeng Dou, Falong Lu, Qian Wang","doi":"10.1016/j.microrel.2024.115553","DOIUrl":"10.1016/j.microrel.2024.115553","url":null,"abstract":"<div><div>Addressing the criticality of IGBT modules in power electronics and reliability challenges in industrial applications, this study focuses on solving the important problem of solder layer aging failure in IGBT modules. Under defined operating conditions, a specific set of electrical parameters, notably the collector-emitter saturation voltage Vce<sub>(sat)</sub> <!--> <!-->, serves as a critical indicator for monitoring the degradation of solder layers within IGBT modules. This parameter is indicative of potential solder layer aging failures, which can be identified and studied to predict and mitigate such failures effectively. In order to analyze the aging trend more deeply and accurately, a new nature-inspired meta-heuristic algorithm based on Crested Porcupine Optimizer is introduced. Combining multiple data during the operation of the IGBT module, such as gate voltage, gate current, heatsink temperature, case temperature, collector-emitter current, and Vce<sub>(sat)</sub>, the parameter optimization is carried out by using CPO, and a prediction model based on the optimization of the SVR by CPO is established, which is successfully implemented to predict the accurate prediction of IGBT module solder layer lifetime. The study also validates the effectiveness of the CPO-SVR method on an accelerated aging dataset of IGBT modules provided by NASA Lab. The results of this research contribute to an in-depth understanding and prediction of the aging process of IGBT modules, which in turn improves the reliability and lifetime of the devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115553"},"PeriodicalIF":1.6,"publicationDate":"2024-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1016/j.microrel.2024.115552
Zhengxin Zhang, Wangyong Chen, Jianwen Lin, Linlin Cai
The Complementary FET (CFET) architecture offers a more promising solution for achieving higher transistor density in sub-3 nm technology nodes. In this study, we use 3D TCAD simulations to conduct Monte Carlo based single-particle incidence analysis on FinFET and four types of CFET 6-Transistor (6T) Static Random Access Memory (SRAM). We identify the linear energy transfer (LET) thresholds for the five SRAM structures and analyze the causes of Single Event Upset (SEU) in three sensitive areas. Simulation results indicate that the SEU LET threshold of the CFET SRAM in the Fin-On-GAA-Fin (FOGF) structure is higher than that of the Fin-On-Trapezoidal-Fin (FOTF) structure. This is because both the upper and lower layers of the CFET SRAM in the FOGF structure use the GAA structure to isolate from the substrate, making it more difficult to trigger the bipolar amplification effect. The CFET SRAM using the Staggered FOGF structure demonstrates the best radiation resistance when the LET is below 0.3 pC/μm, due to the more dispersed distribution of sensitive areas and the isolation of the lower PMOS from the substrate. We also calculate the SEU cross-sections of the five SRAMs under different LETs. Showing that CFET SRAM consistently exhibits better radiation resistance compared to FinFET SRAM. These findings suggest that advanced CFET technology could be effectively applied to the design of radiation-hardened SRAM.
{"title":"Comparative study of single event upset susceptibility in the Complementary FET (CFET) and FinFET based 6T-SRAM","authors":"Zhengxin Zhang, Wangyong Chen, Jianwen Lin, Linlin Cai","doi":"10.1016/j.microrel.2024.115552","DOIUrl":"10.1016/j.microrel.2024.115552","url":null,"abstract":"<div><div>The Complementary FET (CFET) architecture offers a more promising solution for achieving higher transistor density in sub-3 nm technology nodes. In this study, we use 3D TCAD simulations to conduct Monte Carlo based single-particle incidence analysis on FinFET and four types of CFET 6-Transistor (6T) Static Random Access Memory (SRAM). We identify the linear energy transfer (LET) thresholds for the five SRAM structures and analyze the causes of Single Event Upset (SEU) in three sensitive areas. Simulation results indicate that the SEU LET threshold of the CFET SRAM in the Fin-On-GAA-Fin (FOGF) structure is higher than that of the Fin-On-Trapezoidal-Fin (FOTF) structure. This is because both the upper and lower layers of the CFET SRAM in the FOGF structure use the GAA structure to isolate from the substrate, making it more difficult to trigger the bipolar amplification effect. The CFET SRAM using the Staggered FOGF structure demonstrates the best radiation resistance when the LET is below 0.3 pC/μm, due to the more dispersed distribution of sensitive areas and the isolation of the lower PMOS from the substrate. We also calculate the SEU cross-sections of the five SRAMs under different LETs. Showing that CFET SRAM consistently exhibits better radiation resistance compared to FinFET SRAM. These findings suggest that advanced CFET technology could be effectively applied to the design of radiation-hardened SRAM.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115552"},"PeriodicalIF":1.6,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142707132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1016/j.microrel.2024.115554
M. Yazdan Mehr , P. Hajipour , M.R. Karampoor , H. van Zeijl , W.D. van Driel , T. Cooremans , F. De Buyl , G.Q. Zhang
This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.
{"title":"Effects of humidity, ionic contaminations and temperature on the degradation of silicone-based sealing materials used in microelectronics","authors":"M. Yazdan Mehr , P. Hajipour , M.R. Karampoor , H. van Zeijl , W.D. van Driel , T. Cooremans , F. De Buyl , G.Q. Zhang","doi":"10.1016/j.microrel.2024.115554","DOIUrl":"10.1016/j.microrel.2024.115554","url":null,"abstract":"<div><div>This paper investigates the effects of three ageing factors (chemical, humidity, and temperature) and their interactions on the physical properties and degradation of silicone sealant used in microelectronic applications. The thermal degradation of silicone sealants was investigated by exposing samples to temperatures in the range of 150 up to 175 °C. Also, a set of samples were aged at 40 °C in a salt spray set-up with 100 % humidity in a salty atmosphere. Results showed detectable changes in the FTIR spectra of aged specimen as compared with the as-received sample. In all accelerated testing conditions, peak intensities decreased with ageing time, inferring that that the surface characteristics of the sealant is affected by ageing. Shear test results showed that with increasing the ageing time, the maximum shear stress in most cases has decreased in all ageing conditions. Also, it appears that samples with longer ageing times have experienced more elongation before failure. Results also show that salt spraying of specimens is associated with a decrease in the mechanical properties of the sealant, indicating the deleterious implications of ionic contaminations for the mechanical properties of samples.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"164 ","pages":"Article 115554"},"PeriodicalIF":1.6,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142707135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
扫码关注我们
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号