Microelectronics Reliability最新文献_第6页

Yet another reliability assessment method for RRAM-based dot-product engine 另一种基于随机存储器的点积引擎可靠性评估方法

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-24 DOI: 10.1016/j.microrel.2025.115938

Ahmed Mahmoudi , Alessandro Veronesi , Philipp Grothe , Jianan Wen , Rolf Meyer , Markus Ulbricht , Rainer Buchty , Mladen Berekovic , Saleh Mulhem

Resistive random-access memory (RRAM) has been deployed to realize different hardware components, notably dot-product engines that accelerate neural network execution. Several designs of RRAM dot-product engines (RDPEs) have been proposed in the last decade. While generally a promising technology, RRAM devices suffer from various performance-affecting reliability issues. The stuck-at faults (SAFs) in RRAM devices significantly degrade the accuracy of the neural networks running on the RDPE. Therefore, the effect of these faults on applications needs to be assessed. Consequently, this paper introduces a new concept for evaluating the impact of unreliable RRAM behavior due to the most notable SAF phenomenon on executable software. For this, we propose a novel reliability concept called Execution-Guided Reliability (EGR). This EGR model is formulated mathematically based on the reliability block diagram method and later applied to evaluate RDPE reliability. Subsequently, we integrate EGR into a framework with multiple RDPEs to perform several experiments and show numerical results. We then explore and analyze the correlation between the EGR model and the computation error magnitudes of RDPEs to explain the behavior of SAFs in the RRAM devices. The results show that the correlation ranging from

− 0.988

to

− 0.999

indicates, with high confidence, a decreasing monotonic trend between EGR values and error magnitudes.

电阻式随机存取存储器（RRAM）已被用于实现不同的硬件组件，特别是加速神经网络执行的点积引擎。在过去的十年中，已经提出了几种RRAM点积引擎的设计。虽然RRAM设备通常是一种很有前途的技术，但它存在各种影响性能的可靠性问题。RRAM设备中的卡在故障严重降低了神经网络在RDPE上运行的精度。因此，需要评估这些故障对应用程序的影响。因此，本文引入了一个新的概念来评估由于最显著的SAF现象而导致的不可靠RRAM行为对可执行软件的影响。为此，我们提出了一种新的可靠性概念——执行导向可靠性（EGR）。基于可靠性方框图法建立了EGR模型，并将其应用于RDPE可靠性评估。随后，我们将EGR集成到一个具有多个rdpe的框架中，进行了多次实验并给出了数值结果。然后，我们探索和分析了EGR模型与rpe计算误差大小之间的相关性，以解释RRAM器件中SAFs的行为。结果表明，相关系数在- 0.988 ~ - 0.999范围内表明，EGR值与误差值呈单调递减趋势，置信度较高。

{"title":"Yet another reliability assessment method for RRAM-based dot-product engine","authors":"Ahmed Mahmoudi , Alessandro Veronesi , Philipp Grothe , Jianan Wen , Rolf Meyer , Markus Ulbricht , Rainer Buchty , Mladen Berekovic , Saleh Mulhem","doi":"10.1016/j.microrel.2025.115938","DOIUrl":"10.1016/j.microrel.2025.115938","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) has been deployed to realize different hardware components, notably dot-product engines that accelerate neural network execution. Several designs of RRAM dot-product engines (RDPEs) have been proposed in the last decade. While generally a promising technology, RRAM devices suffer from various performance-affecting reliability issues. The stuck-at faults (SAFs) in RRAM devices significantly degrade the accuracy of the neural networks running on the RDPE. Therefore, the effect of these faults on applications needs to be assessed. Consequently, this paper introduces a new concept for evaluating the impact of unreliable RRAM behavior due to the most notable SAF phenomenon on executable software. For this, we propose a novel reliability concept called Execution-Guided Reliability (EGR). This EGR model is formulated mathematically based on the reliability block diagram method and later applied to evaluate RDPE reliability. Subsequently, we integrate EGR into a framework with multiple RDPEs to perform several experiments and show numerical results. We then explore and analyze the correlation between the EGR model and the computation error magnitudes of RDPEs to explain the behavior of SAFs in the RRAM devices. The results show that the correlation ranging from <span><math><mi>− 0.988</mi></math></span> to <span><math><mi>− 0.999</mi></math></span> indicates, with high confidence, a decreasing monotonic trend between EGR values and error magnitudes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115938"},"PeriodicalIF":1.9,"publicationDate":"2025-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gas breakdown characteristic and ablation defect formation mechanism of micro-scale gap in MEMS MEMS微尺度间隙气体击穿特性及烧蚀缺陷形成机理

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-23 DOI: 10.1016/j.microrel.2025.115936

Jiaqi Zheng , Renzhi Hu , Jie Yang , Guofen Xie , Xuhui Gong , Chunlin Liu , Baolin Zhao

Gas breakdown at the microscale dimension has become one of the critical challenges one of urgent challenges along with the miniaturization and high-performance development of MEMS (Micro-Electro-Mechanical Systems) devices. However, comprehensive theoretical frameworks for micro-scale gas discharge characteristic and damage mechanisms in MEMS devices remains to be developed. In the article, the gas discharge behaviors of silicon-based MEMS devices with 1.5 μm gap were investigated, whose I-V characteristics during the initial breakdown process under DC voltage and the subsequent breakdown behavior upon reapplication of voltage were characterized in detail. A theoretical investigation incorporating field emission theory was performed to examine the twice breakdown phenomena, elucidating the critical factors and underlying mechanisms of micro-gap gas discharge. Incorporating ablation defect morphology, compositional analysis, and finite element simulation, the formation process of ablation defects on silicon electrodes was investigated, revealing the breakdown characteristics of MEMS devices with micro-gaps.

随着微机电系统（MEMS）器件的小型化和高性能发展，微尺度气体击穿已成为关键挑战之一。然而，关于MEMS器件微尺度气体放电特性和损伤机理的全面理论框架仍有待发展。本文研究了具有1.5 μm隙隙的硅基MEMS器件的气体放电行为，详细表征了其在直流电压下初始击穿过程中的I-V特性以及随后在重新施加电压时的击穿行为。结合场发射理论对微间隙气体放电的二次击穿现象进行了理论分析，阐明了微间隙气体放电的关键因素和机理。结合烧蚀缺陷形貌、成分分析和有限元模拟，研究了硅电极上烧蚀缺陷的形成过程，揭示了微间隙MEMS器件的击穿特性。

{"title":"Gas breakdown characteristic and ablation defect formation mechanism of micro-scale gap in MEMS","authors":"Jiaqi Zheng , Renzhi Hu , Jie Yang , Guofen Xie , Xuhui Gong , Chunlin Liu , Baolin Zhao","doi":"10.1016/j.microrel.2025.115936","DOIUrl":"10.1016/j.microrel.2025.115936","url":null,"abstract":"<div><div>Gas breakdown at the microscale dimension has become one of the critical challenges one of urgent challenges along with the miniaturization and high-performance development of MEMS (Micro-Electro-Mechanical Systems) devices. However, comprehensive theoretical frameworks for micro-scale gas discharge characteristic and damage mechanisms in MEMS devices remains to be developed. In the article, the gas discharge behaviors of silicon-based MEMS devices with 1.5 μm gap were investigated, whose I-V characteristics during the initial breakdown process under DC voltage and the subsequent breakdown behavior upon reapplication of voltage were characterized in detail. A theoretical investigation incorporating field emission theory was performed to examine the twice breakdown phenomena, elucidating the critical factors and underlying mechanisms of micro-gap gas discharge. Incorporating ablation defect morphology, compositional analysis, and finite element simulation, the formation process of ablation defects on silicon electrodes was investigated, revealing the breakdown characteristics of MEMS devices with micro-gaps.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115936"},"PeriodicalIF":1.9,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-cycle fatigue of printed sintered silver in extreme environments: Mechanical shock at multiple temperatures 印刷烧结银在极端环境下的低周疲劳：多重温度下的机械冲击

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-23 DOI: 10.1016/j.microrel.2025.115932

Hayden Richards , Abhijit Dasgupta , Andres Bujanda , Harvey Tsang , Matthew Bowman

This study considers the response of printed hybrid electronic (PHE) assemblies to extreme mechanical shock (50,000 g base excitation) at multiple elevated temperatures (25–125 °C). Passive components were recessed into milled cavities in injection-molded polysulfone beams using a unique ‘mill-and-fill’ method. The components were interconnected to printed silver traces using printed solder, with circuits then formed from the silver traces. The populated beam specimens were subjected to drop testing in a clamped-clamped configuration without secondary impact using an accelerated-fall drop tower with dual mass shock amplifier (DMSA), resulting in strain magnitudes in the polysulfone substrate of ∼30,000 μm/m at rates up to ∼200 /s. A finite element model of the fully populated assembly was used to estimate plastic strain history at the failure site in the sintered silver.

Circuit failure occurred due to component separation from the substrate caused by cracking within the sintered silver beneath the soldered interconnect – a failure mode common across all temperatures. Maximum plastic strain magnitudes in the sintered silver were ∼ 0.11 m/m at rates of ∼1000 /s. Total number of drops to failure was recorded in four different component locations at all temperatures. These results, together with transient nonlinear finite element simulation data, were then integrated by means of a cumulative damage model, to generate a low-cycle fatigue curve for sintered silver from 25 to 125 °C.

本研究考虑了印刷混合电子（PHE）组件在多个高温（25-125°C）下对极端机械冲击（50,000 g基激励）的响应。采用独特的“铣削-填充”方法，将被动元件嵌入注塑成型聚砜梁的铣削腔中。这些元件使用印刷焊料连接到印刷银线，然后由银线形成电路。填充梁试件在没有二次冲击的夹紧配置下进行跌落测试，使用带有双质量冲击放大器（DMSA）的加速跌落塔，在聚砜衬底中产生约30,000 μm/m的应变，速率高达约200 /s。利用满填充体的有限元模型估计了烧结银在破坏部位的塑性应变历史。电路故障发生的原因是由于元件与衬底分离，这是由于焊接互连下面烧结银的开裂造成的，这种故障模式在所有温度下都很常见。烧结银的最大塑性应变为~ 0.11 m/m，速率为~ 1000 /s。在所有温度下，在四个不同的组件位置记录到故障的总滴数。这些结果与瞬态非线性有限元模拟数据一起，通过累积损伤模型进行整合，生成烧结银在25 - 125°C范围内的低周疲劳曲线。

{"title":"Low-cycle fatigue of printed sintered silver in extreme environments: Mechanical shock at multiple temperatures","authors":"Hayden Richards , Abhijit Dasgupta , Andres Bujanda , Harvey Tsang , Matthew Bowman","doi":"10.1016/j.microrel.2025.115932","DOIUrl":"10.1016/j.microrel.2025.115932","url":null,"abstract":"<div><div>This study considers the response of printed hybrid electronic (PHE) assemblies to extreme mechanical shock (50,000 g base excitation) at multiple elevated temperatures (25–125 °C). Passive components were recessed into milled cavities in injection-molded polysulfone beams using a unique ‘mill-and-fill’ method. The components were interconnected to printed silver traces using printed solder, with circuits then formed from the silver traces. The populated beam specimens were subjected to drop testing in a clamped-clamped configuration without secondary impact using an accelerated-fall drop tower with dual mass shock amplifier (DMSA), resulting in strain magnitudes in the polysulfone substrate of ∼30,000 μm/m at rates up to ∼200 /s. A finite element model of the fully populated assembly was used to estimate plastic strain history at the failure site in the sintered silver.</div><div>Circuit failure occurred due to component separation from the substrate caused by cracking within the sintered silver beneath the soldered interconnect – a failure mode common across all temperatures. Maximum plastic strain magnitudes in the sintered silver were ∼ 0.11 m/m at rates of ∼1000 /s. Total number of drops to failure was recorded in four different component locations at all temperatures. These results, together with transient nonlinear finite element simulation data, were then integrated by means of a cumulative damage model, to generate a low-cycle fatigue curve for sintered silver from 25 to 125 °C.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115932"},"PeriodicalIF":1.9,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel triple-node upset tolerance and lower-power hardened latch circuit for aerospace applications 一种用于航空航天应用的新型三节点扰动公差和低功耗硬化锁存电路

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-22 DOI: 10.1016/j.microrel.2025.115939

Xiuying Wang , Qingyi Liu , Duowen Sun , Mingkun Xu , Qiang Zhao

At present, the anti-radiation hardening of latches in integrated circuits often requires large hardware overhead in order to achieve multi-node upset recovery, which also affects the working performance of the circuits. To overcome this design limitation, this paper proposes a low-power polarity-hardened design latch (LPDL) that tolerates triple-node upset (TNU) with a low power-delay-area product (PDAP). Based on NMOS polarity-hardened technology and transistor-stacked technology, the LPDL not only reduces the number of sensitive nodes, but also significantly lowers power consumption. Compared with other latches, for example, CLCT, FERST, TP-DICE, RH, RHPDL, FPADRL, DURMC, LCTNUT and LCTNUCR, the average optimization degrees of the LPDL for power consumption, and PDAP are 58.04%, and 63.39%, respectively. Additionally, the critical charge (

Q_{c r i t}

) exceeds 150 fC. The standard deviations under different process, voltage, and temperature and Monte Carlo simulations indicate that the LPDL is not only less sensitive to variations in the environment but also tolerates upsets, even under extreme process conditions.

目前，集成电路中锁存器的抗辐射硬化往往需要较大的硬件开销才能实现多节点扰动恢复，这也影响了电路的工作性能。为了克服这一设计限制，本文提出了一种低功耗极性硬化设计锁存器（LPDL），该锁存器具有低功耗延迟面积积（PDAP），可以承受三节点干扰（TNU）。基于NMOS极性硬化技术和晶体管堆叠技术，LPDL不仅减少了敏感节点的数量，而且显著降低了功耗。与CLCT、FERST、TP-DICE、RH、RHPDL、FPADRL、DURMC、LCTNUT、LCTNUCR等锁存器相比，LPDL对功耗的平均优化度为58.04%，PDAP的平均优化度为63.39%。此外，临界电荷（Qcrit）超过150 fC。在不同工艺、电压、温度和蒙特卡罗模拟下的标准差表明，LPDL不仅对环境变化不太敏感，而且即使在极端工艺条件下也能承受扰动。

{"title":"A novel triple-node upset tolerance and lower-power hardened latch circuit for aerospace applications","authors":"Xiuying Wang , Qingyi Liu , Duowen Sun , Mingkun Xu , Qiang Zhao","doi":"10.1016/j.microrel.2025.115939","DOIUrl":"10.1016/j.microrel.2025.115939","url":null,"abstract":"<div><div>At present, the anti-radiation hardening of latches in integrated circuits often requires large hardware overhead in order to achieve multi-node upset recovery, which also affects the working performance of the circuits. To overcome this design limitation, this paper proposes a low-power polarity-hardened design latch (LPDL) that tolerates triple-node upset (TNU) with a low power-delay-area product (PDAP). Based on NMOS polarity-hardened technology and transistor-stacked technology, the LPDL not only reduces the number of sensitive nodes, but also significantly lowers power consumption. Compared with other latches, for example, CLCT, FERST, TP-DICE, RH, RHPDL, FPADRL, DURMC, LCTNUT and LCTNUCR, the average optimization degrees of the LPDL for power consumption, and PDAP are 58.04%, and 63.39%, respectively. Additionally, the critical charge (<span><math><msub><mrow><mi>Q</mi></mrow><mrow><mi>c</mi><mi>r</mi><mi>i</mi><mi>t</mi></mrow></msub></math></span>) exceeds 150 fC. The standard deviations under different process, voltage, and temperature and Monte Carlo simulations indicate that the LPDL is not only less sensitive to variations in the environment but also tolerates upsets, even under extreme process conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115939"},"PeriodicalIF":1.9,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The effect of halogen ion on the process of electrochemical migration of resistor 卤素离子对电阻器电化学迁移过程的影响

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-21 DOI: 10.1016/j.microrel.2025.115937

Yao Tan , Zixue Jiang , Hao Zhang , Xianqin Zhuo , Junsheng Wu , Luntao Wang , Kui Xiao

A water droplet experiment was used to determine the threshold for electrochemical migration of the resistor in halogen contaminants. The risk of electrochemical migration increases with increasing pollutant concentrations, with NaCl being the most significant. At a Cl- concentration of 10 ppm, no dendrites formation; When Cl- concentrations are between 100 and 700 ppm, dendritic growth. When the electrolyte concentration is low, the formation of intact dendrites leads to a prolonged surge of current; With the increase of concentration, the number of nucleation sites and dendrites increases, However, the strong hydrogen evolution reaction makes it difficult to produce intact dendrites.

用水滴实验确定了电阻器在卤素污染物中电化学迁移的阈值。电化学迁移风险随着污染物浓度的增加而增加，以NaCl浓度的增加最为显著。在Cl-浓度为10ppm时，不形成枝晶；当Cl浓度在100 - 700ppm之间时，枝晶生长。当电解质浓度较低时，完整树突的形成导致电流的浪涌延长；随着浓度的增加，成核位点和枝晶的数量增加，但析氢反应强烈，难以生成完整的枝晶。

引用次数: 0

A review of dynamic effects, reliability and mitigation techniques of AlGaN/GaN HEMTs AlGaN/GaN hemt的动态效应、可靠性和缓解技术综述

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-16 DOI: 10.1016/j.microrel.2025.115935

I. Benjamin , S.R. Sriram , B. Bindu

The GaN high electron mobility transistor (HEMT) is a promising device for high speed and high power applications. The GaN material can withstand high voltages, high temperature and renders enhanced device performance in high operating frequency. However, there are several concerns that hinder the commercialization of GaN based transistors suitable for high speed and high power applications. The high-density defect formation and charge trapping in the surface and bulk degrade the dynamic performance of the device. This leads to various detrimental issues such as drain current collapse, increased dynamic ON-resistance, gate leakage current, low threshold voltage, low gate voltage swing, early breakdown, hot carrier effects and bias temperature instability. In this paper, the overview of various GaN structures, reliability and radiation effects and the solutions to suppress the defect formations and charge trapping effects along with improvised GaN structures are reviewed.

氮化镓高电子迁移率晶体管（HEMT）是一种很有前途的高速、高功率器件。GaN材料可以承受高电压、高温，并在高工作频率下增强器件性能。然而，有几个问题阻碍了适合高速和高功率应用的GaN基晶体管的商业化。高密度缺陷的形成和表面和本体中的电荷捕获降低了器件的动态性能。这会导致各种有害的问题，如漏极电流崩溃、动态导通电阻增加、栅极漏电流、低阈值电压、低栅极电压摆幅、早期击穿、热载子效应和偏置温度不稳定。本文综述了各种GaN结构、可靠性和辐射效应以及抑制缺陷形成和电荷捕获效应的方法。

引用次数: 0

Evaluation of reliability of lotus-type porous Cu joint soldered by SAC305 SAC305焊接莲花型多孔铜接头可靠性评价

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-16 DOI: 10.1016/j.microrel.2025.115933

Jae-Ho Shin , Keun-Soo Kim , Sang-Wook Kim , Jae-Won Kim , Min-Su Kim , Soong-Keun Hyun

Lotus-type porous Cu (LPC) is a metallic material characterized by its cylindrical pore structure, which exhibits excellent thermal conductivity, fluid permeability, ductility, and impact energy absorption capabilities. To evaluate the applicability of LPC as electronic materials, LPC/dissimilar materials joints were fabricated using SAC305 solder. To consider the pore structure in LPC, the solder filling ratio was focused as key variables in this work. The microstructure, mechanical behaviors and thermal shock behavior of LPC joints were examined. As the solder filling ratio increased, the joint strength increased, while ductile behavior decreased. When the pores were filled by solder (solder filling ratio: 100 %), the shear strength was similar to that of the non-porous Cu joint. After thermal shock cycling, LPC joint demonstrated lower degradation of shear strength compared to the non-porous Cu joint due to its structural characteristics. These results were attributed to the low yield strength of LPC and unique joining interface by pore structure of LPC.

莲花型多孔铜（Lotus-type porous Cu， LPC）是一种具有圆柱形孔结构的金属材料，具有优异的导热性、流体渗透性、延展性和冲击能吸收能力。为了评估LPC作为电子材料的适用性，采用SAC305焊料制备了LPC/异种材料的接头。为了考虑LPC的孔隙结构，本文将钎料填充率作为关键变量进行研究。研究了LPC接头的显微组织、力学性能和热冲击性能。随着钎料填充率的增加，接头强度增加，但延性降低。当焊料填充孔隙（焊料填充率为100%）时，接头的抗剪强度与无孔铜接头相近。热冲击循环后，由于LPC接头的结构特点，其抗剪强度的退化程度低于无孔铜接头。这些结果归因于低屈服强度的LPC和独特的连接界面的LPC的孔隙结构。

{"title":"Evaluation of reliability of lotus-type porous Cu joint soldered by SAC305","authors":"Jae-Ho Shin , Keun-Soo Kim , Sang-Wook Kim , Jae-Won Kim , Min-Su Kim , Soong-Keun Hyun","doi":"10.1016/j.microrel.2025.115933","DOIUrl":"10.1016/j.microrel.2025.115933","url":null,"abstract":"<div><div>Lotus-type porous Cu (LPC) is a metallic material characterized by its cylindrical pore structure, which exhibits excellent thermal conductivity, fluid permeability, ductility, and impact energy absorption capabilities. To evaluate the applicability of LPC as electronic materials, LPC/dissimilar materials joints were fabricated using SAC305 solder. To consider the pore structure in LPC, the solder filling ratio was focused as key variables in this work. The microstructure, mechanical behaviors and thermal shock behavior of LPC joints were examined. As the solder filling ratio increased, the joint strength increased, while ductile behavior decreased. When the pores were filled by solder (solder filling ratio: 100 %), the shear strength was similar to that of the non-porous Cu joint. After thermal shock cycling, LPC joint demonstrated lower degradation of shear strength compared to the non-porous Cu joint due to its structural characteristics. These results were attributed to the low yield strength of LPC and unique joining interface by pore structure of LPC.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115933"},"PeriodicalIF":1.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Aging mitigation of FinFET-based DFF through transistor-level analysis 通过晶体管级分析减缓基于finfet的DFF老化

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-14 DOI: 10.1016/j.microrel.2025.115931

Meng Li , Xin Xu , Yunpeng Li , Yiqun Shi , Qingqing Sun , Hao Zhu

The continuous scaling of semiconductor devices has made aging effects, such as hot carrier injection (HCI) and negative bias temperature instability (NBTI), increasingly significant in advanced technology nodes. The resulting threshold voltage shifts impose more severe propagation delays on standard cell libraries, ultimately affecting circuit timing reliability. In this paper, we introduce a transistor-level aging analysis methodology to mitigate aging effects on the timing reliability of Scan D Flip-Flops (DFFs) based on a 14-nm FinFET platform. This methodology provides a detailed and accurate assessment of aging impacts and enables the identification of the modules most susceptible to degradation. Subsequently, temporal aging mitigation techniques are comparatively analyzed, and structural improvement schemes are proposed and validated. Simulation results demonstrate that the proposed improvements achieve stable operation across different process corners. At the cost of a 20 % increase in the Power-Delay Product (PDP), the aging-induced delay increase is reduced in all corners, with an average reduction of 55.5 % observed in the slow–slow (ss) corner.

半导体器件的不断微缩使得热载流子注入（HCI）和负偏置温度不稳定性（NBTI）等老化效应在先进技术节点上日益显著。由此产生的阈值电压移位对标准单元库施加更严重的传播延迟，最终影响电路定时可靠性。在本文中，我们介绍了一种晶体管级老化分析方法，以减轻老化对基于14nm FinFET平台的扫描D触发器（dff）时序可靠性的影响。该方法提供了对老化影响的详细和准确的评估，并能够识别最容易退化的模块。在此基础上，对比分析了时间老化减缓技术，提出并验证了结构改进方案。仿真结果表明，所提出的改进方法可以实现跨不同过程角的稳定运行。在功率延迟积（PDP）增加20%的代价下，老化引起的延迟增加在所有角落都减少了，在慢-慢（ss）角落平均减少了55.5%。

{"title":"Aging mitigation of FinFET-based DFF through transistor-level analysis","authors":"Meng Li , Xin Xu , Yunpeng Li , Yiqun Shi , Qingqing Sun , Hao Zhu","doi":"10.1016/j.microrel.2025.115931","DOIUrl":"10.1016/j.microrel.2025.115931","url":null,"abstract":"<div><div>The continuous scaling of semiconductor devices has made aging effects, such as hot carrier injection (HCI) and negative bias temperature instability (NBTI), increasingly significant in advanced technology nodes. The resulting threshold voltage shifts impose more severe propagation delays on standard cell libraries, ultimately affecting circuit timing reliability. In this paper, we introduce a transistor-level aging analysis methodology to mitigate aging effects on the timing reliability of Scan D Flip-Flops (DFFs) based on a 14-nm FinFET platform. This methodology provides a detailed and accurate assessment of aging impacts and enables the identification of the modules most susceptible to degradation. Subsequently, temporal aging mitigation techniques are comparatively analyzed, and structural improvement schemes are proposed and validated. Simulation results demonstrate that the proposed improvements achieve stable operation across different process corners. At the cost of a 20 % increase in the Power-Delay Product (PDP), the aging-induced delay increase is reduced in all corners, with an average reduction of 55.5 % observed in the slow–slow (ss) corner.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115931"},"PeriodicalIF":1.9,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An interface trap density evaluation method for SiC MOSFET based on neural network 基于神经网络的SiC MOSFET界面阱密度评价方法

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-14 DOI: 10.1016/j.microrel.2025.115934

Borui Yang , Guicui Fu , Bo Wan , Xiangfen Wang

The high density of interface defects at the gate oxide interface is closely related to the device characteristics and reliability of silicon carbide metal-oxide-semiconductor field effect transistors. However, an efficient and reliable characterization method for interface defects remains to be developed. In this work, we propose a neural network method for evaluating the interface trap density distribution and fixed oxide charge density using the transfer characteristics of devices. The neural network utilizes a long short-term memory structure to capture the mapping relationship between the transfer characteristic and the interface defect parameters. The numerical simulation data are used to form the training dataset of the network, and an effective preprocessing method is also presented. The proposed method was successfully verified by comparing simulated transfer characteristics using the evaluated results of commercial devices with corresponding measurements. Also, the interface defect parameters were evaluated by the subthreshold current method for comparison. The result shows that the evaluated results of the proposed method are close to the experimental evaluated results, with relative errors of 3.3 %, 6.6 %, and 28.2 % for the three devices under threshold voltage, respectively. Further, the proposed method was successfully applied during the high temperature gate bias tests to detect the degradation trend of the gate oxide interface. The result reflects its practicality for the interface reliability analysis of silicon carbide metal-oxide-semiconductor field effect transistors.

栅极氧化界面处的高密度界面缺陷与碳化硅金属氧化物半导体场效应晶体管的器件特性和可靠性密切相关。然而，一种高效可靠的界面缺陷表征方法仍有待开发。在这项工作中，我们提出了一种神经网络方法，利用器件的转移特性来评估界面陷阱密度分布和固定氧化物电荷密度。神经网络利用长短期记忆结构捕捉传递特性与界面缺陷参数之间的映射关系。利用数值模拟数据形成网络训练数据集，并提出了一种有效的预处理方法。通过将商业装置的模拟传输特性与相应的测量结果进行比较，成功地验证了所提出的方法。同时，采用亚阈值电流法对界面缺陷参数进行评估，进行比较。结果表明，该方法的评估结果与实验评估结果接近，三种器件在阈值电压下的相对误差分别为3.3%、6.6%和28.2%。此外，该方法还成功地应用于栅极氧化界面的高温偏置测试中，用于检测栅极氧化界面的降解趋势。结果表明，该方法对碳化硅金属氧化物半导体场效应晶体管界面可靠性分析具有实用性。

{"title":"An interface trap density evaluation method for SiC MOSFET based on neural network","authors":"Borui Yang , Guicui Fu , Bo Wan , Xiangfen Wang","doi":"10.1016/j.microrel.2025.115934","DOIUrl":"10.1016/j.microrel.2025.115934","url":null,"abstract":"<div><div>The high density of interface defects at the gate oxide interface is closely related to the device characteristics and reliability of silicon carbide metal-oxide-semiconductor field effect transistors. However, an efficient and reliable characterization method for interface defects remains to be developed. In this work, we propose a neural network method for evaluating the interface trap density distribution and fixed oxide charge density using the transfer characteristics of devices. The neural network utilizes a long short-term memory structure to capture the mapping relationship between the transfer characteristic and the interface defect parameters. The numerical simulation data are used to form the training dataset of the network, and an effective preprocessing method is also presented. The proposed method was successfully verified by comparing simulated transfer characteristics using the evaluated results of commercial devices with corresponding measurements. Also, the interface defect parameters were evaluated by the subthreshold current method for comparison. The result shows that the evaluated results of the proposed method are close to the experimental evaluated results, with relative errors of 3.3 %, 6.6 %, and 28.2 % for the three devices under threshold voltage, respectively. Further, the proposed method was successfully applied during the high temperature gate bias tests to detect the degradation trend of the gate oxide interface. The result reflects its practicality for the interface reliability analysis of silicon carbide metal-oxide-semiconductor field effect transistors.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115934"},"PeriodicalIF":1.9,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of SEB cross-sections between spallation neutron and mono-energetic proton for SiC MOSFETs SiC mosfet中散裂中子与单能质子SEB截面的比较

IF 1.9 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability

Pub Date : 2025-10-11 DOI: 10.1016/j.microrel.2025.115930

Chao Peng , Zhifeng Lei , Zhangang Zhang , Teng Ma , Hong Zhang , Yujuan He , Rui Gao , Xuefei Liu , Yun Huang

The radiation-induced single event burnout (SEB) is observed for SiC MOSFETs by conducting proton and spallation neutron irradiation. Proton irradiation experiments reveal that the SEB cross-section rises monotonically with increasing proton energy. When the SiC MOSFET is biased at 78 % of its rated voltage, the SEB cross-section increase from 5.02 × 10⁻¹¹ cm² to 5.12 × 10⁻¹⁰ cm² as the proton energy increase from 60 MeV to 300 MeV. The SEB cross-sections for protons with energies above 100 MeV exceed those for spallation neutrons. It indicates that using the proton SEB cross-section at a single energy above 100 MeV would overestimate the atmospheric neutron-induced failure rate of SiC MOSFETs. The SEB caused by protons and spallation neutrons is strongly correlated with the ionizing energy deposition of their secondary ions from nuclear reactions. The information of the secondary ions produced by spallation neutron and proton is obtained through Particle and Heavy Ion Transport code System (PHITS) calculations. The simulation results indicate that the number of secondary ions capable of depositing sufficient energy to trigger SEB increases with proton energy. Therefore, the SEB cross section is correspondingly higher for higher-energy protons. For protons with energies above 100 MeV, the number of secondary ion products capable of triggering SEB is greater than that from spallation neutrons. This explains why the SEB cross-section for protons above 100 MeV is larger than that for spallation neutrons. By combining proton SEB cross-sections at five distinct energies, the atmospheric neutron-induced SEB failure rates at sea level for SiC MOSFETs are calculated to be range from 2.73 to 52.0 FIT when the devices are biased at 78 % to 94 % of their rated voltage. Based on the spallation neutron data, the failure rates range from 1.47 to 26.5 FIT for the same bias range. The failure rates calculated by these two methods are consistent, differing by less than 49 %. The findings indicate that both spallation neutrons and multi-energy proton irradiation are effective for estimating the failure rates of SiC MOSFETs under atmospheric neutron exposure.

通过质子和散裂中子的辐照，观察了SiC mosfet的单事件烧坏（SEB）。质子辐照实验表明，SEB截面随质子能量的增加而单调上升。当SiC MOSFET偏置在其额定电压的78%时，随着质子能量从60 MeV增加到300 MeV， SEB截面从5.02 × 10−11 cm2增加到5.12 × 10−10 cm2。能量在100 MeV以上的质子的SEB截面大于散裂中子的SEB截面。结果表明，在100 MeV以上的单能量下使用质子SEB截面会高估SiC mosfet的大气中子诱导故障率。由质子和散裂中子引起的SEB与核反应中它们的二次离子的电离能沉积密切相关。通过粒子和重离子输运编码系统（PHITS）的计算，获得了中子和质子散裂产生的二次离子的信息。模拟结果表明，能够沉积足够能量触发SEB的二次离子数量随着质子能量的增加而增加。因此，对于能量更高的质子，SEB截面相应更高。对于能量在100 MeV以上的质子，能够触发SEB的二次离子产物的数量大于散裂中子。这就解释了为什么大于100 MeV的质子的SEB截面大于散裂中子的SEB截面。通过结合5种不同能量下的质子SEB截面，计算了SiC mosfet在海平面上的大气中子诱导SEB故障率，当器件偏置在其额定电压的78%至94%时，其范围为2.73至52.0 FIT。根据散裂中子数据，在相同偏置范围内，故障率为1.47 ~ 26.5 FIT。这两种方法计算的故障率是一致的，相差不到49%。结果表明，散裂中子和多能质子辐照都能有效地估计大气中子辐照下SiC mosfet的故障率。

{"title":"Comparison of SEB cross-sections between spallation neutron and mono-energetic proton for SiC MOSFETs","authors":"Chao Peng , Zhifeng Lei , Zhangang Zhang , Teng Ma , Hong Zhang , Yujuan He , Rui Gao , Xuefei Liu , Yun Huang","doi":"10.1016/j.microrel.2025.115930","DOIUrl":"10.1016/j.microrel.2025.115930","url":null,"abstract":"<div><div>The radiation-induced single event burnout (SEB) is observed for SiC MOSFETs by conducting proton and spallation neutron irradiation. Proton irradiation experiments reveal that the SEB cross-section rises monotonically with increasing proton energy. When the SiC MOSFET is biased at 78 % of its rated voltage, the SEB cross-section increase from 5.02 × 10<sup>−11</sup> cm<sup>2</sup> to 5.12 × 10<sup>−10</sup> cm<sup>2</sup> as the proton energy increase from 60 MeV to 300 MeV. The SEB cross-sections for protons with energies above 100 MeV exceed those for spallation neutrons. It indicates that using the proton SEB cross-section at a single energy above 100 MeV would overestimate the atmospheric neutron-induced failure rate of SiC MOSFETs. The SEB caused by protons and spallation neutrons is strongly correlated with the ionizing energy deposition of their secondary ions from nuclear reactions. The information of the secondary ions produced by spallation neutron and proton is obtained through Particle and Heavy Ion Transport code System (PHITS) calculations. The simulation results indicate that the number of secondary ions capable of depositing sufficient energy to trigger SEB increases with proton energy. Therefore, the SEB cross section is correspondingly higher for higher-energy protons. For protons with energies above 100 MeV, the number of secondary ion products capable of triggering SEB is greater than that from spallation neutrons. This explains why the SEB cross-section for protons above 100 MeV is larger than that for spallation neutrons. By combining proton SEB cross-sections at five distinct energies, the atmospheric neutron-induced SEB failure rates at sea level for SiC MOSFETs are calculated to be range from 2.73 to 52.0 FIT when the devices are biased at 78 % to 94 % of their rated voltage. Based on the spallation neutron data, the failure rates range from 1.47 to 26.5 FIT for the same bias range. The failure rates calculated by these two methods are consistent, differing by less than 49 %. The findings indicate that both spallation neutrons and multi-energy proton irradiation are effective for estimating the failure rates of SiC MOSFETs under atmospheric neutron exposure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115930"},"PeriodicalIF":1.9,"publicationDate":"2025-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0