Implantable cardioverter defibrillators (ICDs) provide real-time monitoring and immediate defibrillation for life-threatening arrhythmias. However, the intracardiac electrogram (IEGM) acquisition of ICDs faces stringent constraints, including power consumption, low-frequency noise, and patient-specific physiological variability. This article introduces an ultralow-power, high-resolution, reconfigurable three-stage bandpass filter designed specifically for IEGM, utilizing ferroelectric field-effect transistor (FeFET) technology provided by a foundry platform. By employing adjustable threshold voltage $V {_{text {th}}}$ and gate capacitance of FeFET as programmable pseudo-high-value resistors (PHVRs) and capacitor structures, the filter enables personalized cardiac signal isolation tailored to individual patient needs. In addition, this work incorporates, for the first time, a comprehensive low-frequency noise model covering the entire operational region of FeFET into circuit-level analysis. Based on GlobalFoundries (GF) 28-nm SLPe FeFET-enabled process, the proposed filter achieves a wide gain tuning range (17–77 dB) and a flexible bandwidth tuning range (0.5–19 Hz for low cutoff frequency and 23–138 Hz for high cutoff frequency), with an average power consumption of 257 nW and minimum 11-$mu $ V resolution.
{"title":"Reconfigurable Ferroelectric Bandpass Filter With Low-Frequency Noise Analysis for Intracardiac Electrogram Monitoring","authors":"Jianwei Jia;Zhenge Jia;Omkar Phadke;Yiyu Shi;Shimeng Yu","doi":"10.1109/JXCDC.2025.3584711","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3584711","url":null,"abstract":"Implantable cardioverter defibrillators (ICDs) provide real-time monitoring and immediate defibrillation for life-threatening arrhythmias. However, the intracardiac electrogram (IEGM) acquisition of ICDs faces stringent constraints, including power consumption, low-frequency noise, and patient-specific physiological variability. This article introduces an ultralow-power, high-resolution, reconfigurable three-stage bandpass filter designed specifically for IEGM, utilizing ferroelectric field-effect transistor (FeFET) technology provided by a foundry platform. By employing adjustable threshold voltage <inline-formula> <tex-math>$V {_{text {th}}}$ </tex-math></inline-formula> and gate capacitance of FeFET as programmable pseudo-high-value resistors (PHVRs) and capacitor structures, the filter enables personalized cardiac signal isolation tailored to individual patient needs. In addition, this work incorporates, for the first time, a comprehensive low-frequency noise model covering the entire operational region of FeFET into circuit-level analysis. Based on GlobalFoundries (GF) 28-nm SLPe FeFET-enabled process, the proposed filter achieves a wide gain tuning range (17–77 dB) and a flexible bandwidth tuning range (0.5–19 Hz for low cutoff frequency and 23–138 Hz for high cutoff frequency), with an average power consumption of 257 nW and minimum 11-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>V resolution.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"67-73"},"PeriodicalIF":2.0,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11059896","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144606362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage ($V_{min }$ ) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM $V_{min }$ evaluation, we have measured the FinFETs fabricated using a commercial 5-nm technology down to 10 K. Next, we calibrate a cryogenic-aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types: 1) high-density cell (HDC); 2) low-voltage cell (LVC); and 3) high-performance cell (HPC). We analyze the impact of the threshold voltage ($V_{text {TH}}$ ) and gate length ($L_{G}$ )-only variations on the SRAM noise resilience. At cryogenic temperature, minimum read voltage ($V_{min ,R}$ ) =0.15 V (62% decrease from room temperature) and minimum write voltage ($V_{min ,W}$ ) =0.45 V are achieved without read-/write-assist circuits. We also highlight that the LVC provides the best tradeoff for $V_{min }$ between read and write operations for low-power cryogenic applications.
{"title":"An Investigation of Minimum Supply Voltage of 5-nm SRAM From 300 K Down to 10 K","authors":"Hafeez Raza;Shivendra Singh Parihar;Yogesh Singh Chauhan;Hussam Amrouch;Avinash Lahgere","doi":"10.1109/JXCDC.2025.3560215","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3560215","url":null,"abstract":"In this article, we present a comprehensive study of the impact of cryogenic temperatures on the minimum operating voltage (<inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula>) of 5-nm Fin Field-Effect Transistors (FinFETs)-based Static Random Access Memory (SRAM) cells. To perform the SRAM <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> evaluation, we have measured the FinFETs fabricated using a commercial 5-nm technology down to 10 K. Next, we calibrate a cryogenic-aware BSIM-CMG FinFET compact model, which we use with our SRAM evaluation framework. For a comprehensive study, we evaluate three industry-standard SRAM cell types: 1) high-density cell (HDC); 2) low-voltage cell (LVC); and 3) high-performance cell (HPC). We analyze the impact of the threshold voltage (<inline-formula> <tex-math>$V_{text {TH}}$ </tex-math></inline-formula>) and gate length (<inline-formula> <tex-math>$L_{G}$ </tex-math></inline-formula>)-only variations on the SRAM noise resilience. At cryogenic temperature, minimum read voltage (<inline-formula> <tex-math>$V_{min ,R}$ </tex-math></inline-formula>) =0.15 V (62% decrease from room temperature) and minimum write voltage (<inline-formula> <tex-math>$V_{min ,W}$ </tex-math></inline-formula>) =0.45 V are achieved without read-/write-assist circuits. We also highlight that the LVC provides the best tradeoff for <inline-formula> <tex-math>$V_{min }$ </tex-math></inline-formula> between read and write operations for low-power cryogenic applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"42-50"},"PeriodicalIF":2.0,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10963695","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143925318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-26DOI: 10.1109/JXCDC.2025.3573709
Zikang Lin;Xiaohui Wu;Shujing Zhao;Weihua Liu;Xin Li;Li Geng;Chuanyu Han
In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological neurons, along with controllable burst firing patterns. The spikes, interspike interval (ISI) within a burst, and the quiescence interval between bursts can be adjusted by varying the capacitance and resistance values. In addition, this circuit operates without the need for a bias supply or inductors, enhancing its scalability. This design not only improves circuit interconnection but also effectively reduces power consumption, providing a solid foundation for the development of spiking neural networks (SNNs).
{"title":"A Passive and Scalable High-Order Neuromorphic Circuit Enabled by Mott Memristors","authors":"Zikang Lin;Xiaohui Wu;Shujing Zhao;Weihua Liu;Xin Li;Li Geng;Chuanyu Han","doi":"10.1109/JXCDC.2025.3573709","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3573709","url":null,"abstract":"In this study, VO2 Mott memristors have been successfully fabricated, leading to the proposal of a passive and scalable high-order neural circuit. This circuit consists of two coupled VO2 Mott memristors, two resistors, and three capacitors. The proposed high-order neural circuit demonstrates 11 distinct firing behaviors similar to those of biological neurons, along with controllable burst firing patterns. The spikes, interspike interval (ISI) within a burst, and the quiescence interval between bursts can be adjusted by varying the capacitance and resistance values. In addition, this circuit operates without the need for a bias supply or inductors, enhancing its scalability. This design not only improves circuit interconnection but also effectively reduces power consumption, providing a solid foundation for the development of spiking neural networks (SNNs).","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"60-66"},"PeriodicalIF":2.0,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11015876","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144492399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-09DOI: 10.1109/JXCDC.2025.3568622
Sufia Shahin;Swati Deshwal;Anirban Kar;Mahdi Benkhelifa;Yogesh S. Chauhan;Hussam Amrouch
This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work-function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage ($V_{mathrm {TH}}$ ), on-state current ($I_{mathrm {ON}}$ ), and off-state current ($I_{mathrm {OFF}}$ ). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework—which accounts for defect generation due to negative bias temperature instability (NBTI)—is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding $V_{mathrm {TH}}$ shifts in p-type transistors under varying gate stress biases ($V_{mathrm {GSTR}}$ ) and operating temperatures. At the circuit level, a full array of 6T-static random access memory (SRAM) cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. The variability analysis reveals that the access disturb margin achieves a cell sigma ($mu /sigma $ ) of 17.4 at nominal supply voltage, significantly exceeding the $6sigma $ robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs.
本研究通过解决由工艺变化引起的设计时可变性和由温度和老化影响引起的运行时可变性来研究互补场效应晶体管（cfet）的可靠性。采用严格校准的TCAD模型，对实验数据进行验证，量化金属栅粒度（MGG）诱导的功函数变化（WFV）和随机掺杂波动（RDF）对关键器件参数的影响，包括阈值电压（$V_{mathrm {TH}}$）、导通电流（$I_{mathrm {ON}}$）和关断电流（$I_{mathrm {OFF}}$）。系统地分析了温度相关的变异性，以进一步阐明这些先进设备的行为。为了捕捉老化的动态影响，在TCAD中实现了反应扩散（RD）框架，该框架解释了由于负偏置温度不稳定性（NBTI）而产生的缺陷，从而可以在不同栅极应力偏置（$V_{mathrm {GSTR}}$）和工作温度下对p型晶体管的陷阱产生和相应的$V_{mathrm {TH}}$位移进行详细建模。在电路层面，在根据TCAD数据仔细校准行业标准紧凑型栅极全能（BSIM-CMG）模型后，使用SPICE模拟了具有必要外围电路的全阵列6t静态随机存取存储器（SRAM）单元。变异性分析表明，在标称电源电压下，接入干扰裕度达到17.4的cell sigma ($mu /sigma $)，显著超过$6sigma $对读干扰的鲁棒性准则。此外，当工作温度从300 K增加到398 K时，读取静态噪声裕度（RSNM）和保持静态噪声裕度（HSNM）下降了13.7％% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs.
{"title":"CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability","authors":"Sufia Shahin;Swati Deshwal;Anirban Kar;Mahdi Benkhelifa;Yogesh S. Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3568622","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3568622","url":null,"abstract":"This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work-function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage (<inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula>), <sc>on</small>-state current (<inline-formula> <tex-math>$I_{mathrm {ON}}$ </tex-math></inline-formula>), and <sc>off</small>-state current (<inline-formula> <tex-math>$I_{mathrm {OFF}}$ </tex-math></inline-formula>). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework—which accounts for defect generation due to negative bias temperature instability (NBTI)—is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding <inline-formula> <tex-math>$V_{mathrm {TH}}$ </tex-math></inline-formula> shifts in p-type transistors under varying gate stress biases (<inline-formula> <tex-math>$V_{mathrm {GSTR}}$ </tex-math></inline-formula>) and operating temperatures. At the circuit level, a full array of 6T-static random access memory (SRAM) cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. The variability analysis reveals that the access disturb margin achieves a cell sigma (<inline-formula> <tex-math>$mu /sigma $ </tex-math></inline-formula>) of 17.4 at nominal supply voltage, significantly exceeding the <inline-formula> <tex-math>$6sigma $ </tex-math></inline-formula> robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3%. These findings provide critical insights into the design tradeoffs and reliability challenges of CFET-based SRAMs.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"51-59"},"PeriodicalIF":2.0,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10994809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144243672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness of IMC using emerging FE technology at the 5-nm technology node. To achieve that, we begin by characterizing commercial 5-nm fin field-effect transistors (FinFETs) from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model [Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG)] to accurately reproduce the measurements. Afterward, we use the Preisach-model-based approach to incorporate the impact of FE within the BSIM-CMG model framework using the measurements from FE capacitor to realize ferroelectric fin field-effect transistors (Fe-FinFETs) operating from 300 down to 10 K. Then, as proof of concept, we focus on $1times 8$ ternary content addressable memory (TCAM) array that is used to perform language classification and voice recognition using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of TCAM-based IMC all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC. We reveal that cryogenic temperatures lead to the worst performance in Fe-FinFET-based TCAM. Hence, we have also proposed solutions to improve the cryogenic performance of Fe-FinFET-based TCAM.
{"title":"Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM","authors":"Shivendra Singh Parihar;Shubham Kumar;Swetaki Chatterjee;Girish Pahwa;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3547797","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3547797","url":null,"abstract":"Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness of IMC using emerging FE technology at the 5-nm technology node. To achieve that, we begin by characterizing commercial 5-nm fin field-effect transistors (FinFETs) from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model [Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG)] to accurately reproduce the measurements. Afterward, we use the Preisach-model-based approach to incorporate the impact of FE within the BSIM-CMG model framework using the measurements from FE capacitor to realize ferroelectric fin field-effect transistors (Fe-FinFETs) operating from 300 down to 10 K. Then, as proof of concept, we focus on <inline-formula> <tex-math>$1times 8$ </tex-math></inline-formula> ternary content addressable memory (TCAM) array that is used to perform language classification and voice recognition using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of TCAM-based IMC all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC. We reveal that cryogenic temperatures lead to the worst performance in Fe-FinFET-based TCAM. Hence, we have also proposed solutions to improve the cryogenic performance of Fe-FinFET-based TCAM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"34-41"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10909519","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-05DOI: 10.1109/JXCDC.2025.3539470
Jianzi Jin;Shifan Gao;Cimang Lu;Xiang Qiu;Yi Zhao
A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), the costly multiplication postprocessing can be efficiently performed with the analog operation inside the array. The BL-differential voltage output scheme has two unique invariances. First, the so-called scaling invariance allows the weight matrix to be scaled to the full range for every BL. Second, the shifting invariance allows the weight to be tuned to a larger conductance with a better I–V linearity. Combined with the distributed padding, input voltage loss can also be reduced by suppressing the IR drop. The above schemes can significantly improve the linearity and reduce the relative weight error by >50%, as confirmed in applications from MNIST to face recognition, making it a promising solution for advanced artificial intelligence (AI) and memory computing applications.
{"title":"Device Nonideality-Aware Compute-in-Memory Array Architecting: Direct Voltage Sensing, I–V Symmetric Bitcell, and Padding Array","authors":"Jianzi Jin;Shifan Gao;Cimang Lu;Xiang Qiu;Yi Zhao","doi":"10.1109/JXCDC.2025.3539470","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3539470","url":null,"abstract":"A voltage sensing compute-in-memory (CIM) architecture has been designed to improve the analog computing accuracy, and a chip on 90-nm flash platform has been successfully fabricated, with the bidirectional operation enabled by the symmetric bitcell structure. By padding the weight sum to a global value for all bit lines (BLs), the costly multiplication postprocessing can be efficiently performed with the analog operation inside the array. The BL-differential voltage output scheme has two unique invariances. First, the so-called scaling invariance allows the weight matrix to be scaled to the full range for every BL. Second, the shifting invariance allows the weight to be tuned to a larger conductance with a better I–V linearity. Combined with the distributed padding, input voltage loss can also be reduced by suppressing the IR drop. The above schemes can significantly improve the linearity and reduce the relative weight error by >50%, as confirmed in applications from MNIST to face recognition, making it a promising solution for advanced artificial intelligence (AI) and memory computing applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"19-24"},"PeriodicalIF":2.0,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10876176","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143553318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-04DOI: 10.1109/JXCDC.2025.3538702
Yusaku Shiotsu;Satoshi Sugahara
A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the energy minimum point (EMP) operation for inference. The proposed memory array in the PPIM macro is configured with single-port Schmitt-trigger-type cells just by adding multiple bit lines with spatial address mapping modulation, resulting in a highly area-efficient cell array. The EMP operation of the developed PPIM macro can maximize the energy efficiency. As a result, an energy efficiency higher than 100 tera-operations-per-second per Watt (TOPS/W) can be achieved at around the EMP voltage. The EMP operation is also beneficial for enhancing the processing performance [measured in units of tera-operations per second (TOPS)] of the macro. The performance of fully connected-layer (FCL) networks configured with a multiple of the PPIM macro is also demonstrated.
{"title":"Binarized Neural-Network Parallel-Processing Accelerator Macro Designed for an Energy Efficiency Higher Than 100 TOPS/W","authors":"Yusaku Shiotsu;Satoshi Sugahara","doi":"10.1109/JXCDC.2025.3538702","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3538702","url":null,"abstract":"A binarized neural-network (BNN) accelerator macro is developed based on a processing-in-memory (PIM) architecture having the ability of eight-parallel multiply-accumulate (MAC) processing. The parallel-processing PIM macro, referred to as a PPIM macro, is designed to perform the parallel processing with no use of multiport SRAM cells and to achieve the energy minimum point (EMP) operation for inference. The proposed memory array in the PPIM macro is configured with single-port Schmitt-trigger-type cells just by adding multiple bit lines with spatial address mapping modulation, resulting in a highly area-efficient cell array. The EMP operation of the developed PPIM macro can maximize the energy efficiency. As a result, an energy efficiency higher than 100 tera-operations-per-second per Watt (TOPS/W) can be achieved at around the EMP voltage. The EMP operation is also beneficial for enhancing the processing performance [measured in units of tera-operations per second (TOPS)] of the macro. The performance of fully connected-layer (FCL) networks configured with a multiple of the PPIM macro is also demonstrated.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"25-33"},"PeriodicalIF":2.0,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10870055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143602032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/JXCDC.2025.3534560
Madison Manley;James Read;Ankit Kaul;Shimeng Yu;Muhannad Bakir
Three-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with power supply noise (PSN) margins due to $V_{text {DD}}$ scaling and increased power delivery network (PDN) impedance. This study demonstrates the necessity and benefits of 3D-HI for large-scale CIM accelerators, where 2-D implementations would exceed manufacturing reticle limits. Our 3-D designs achieve 39% higher energy efficiency, $8times $ higher operation density, and improved throughput through shorter vertical interconnects. We quantify steady-state IR-drop impacts in 3D-HI CIM architectures using a framework that combines PDN modeling, 3D-HI power, performance, area estimation, and behavioral modeling. We demonstrate that a drop in supply voltage to CIM arrays increases sensitivity to process, voltage, and temperature (PVT) noise. Using our framework, we model IR-drop and simulate its impact on the accuracy of ResNet-50 and ResNet-152 when classifying images from the ImageNet 1k dataset in the presence of injected PVT noise. We analyze the impact of through-silicon via (TSV) design and placement to optimize the IR-drop and classification accuracy. For ResNet architectures in 3-D integration, we demonstrate that peripheral TSV placement provides an optimal balance between interconnect complexity and performance, achieving IR-drop below 10% of $V_{text {DD}}$ while maintaining high classification accuracy.
{"title":"Co-Optimization of Power Delivery Network Design for 3-D Heterogeneous Integration of RRAM-Based Compute In-Memory Accelerators","authors":"Madison Manley;James Read;Ankit Kaul;Shimeng Yu;Muhannad Bakir","doi":"10.1109/JXCDC.2025.3534560","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3534560","url":null,"abstract":"Three-dimensional heterogeneous integration (3D-HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, addressing the need for on-chip acceleration of large AI models. However, this approach faces challenges with power supply noise (PSN) margins due to <inline-formula> <tex-math>$V_{text {DD}}$ </tex-math></inline-formula> scaling and increased power delivery network (PDN) impedance. This study demonstrates the necessity and benefits of 3D-HI for large-scale CIM accelerators, where 2-D implementations would exceed manufacturing reticle limits. Our 3-D designs achieve 39% higher energy efficiency, <inline-formula> <tex-math>$8times $ </tex-math></inline-formula> higher operation density, and improved throughput through shorter vertical interconnects. We quantify steady-state IR-drop impacts in 3D-HI CIM architectures using a framework that combines PDN modeling, 3D-HI power, performance, area estimation, and behavioral modeling. We demonstrate that a drop in supply voltage to CIM arrays increases sensitivity to process, voltage, and temperature (PVT) noise. Using our framework, we model IR-drop and simulate its impact on the accuracy of ResNet-50 and ResNet-152 when classifying images from the ImageNet 1k dataset in the presence of injected PVT noise. We analyze the impact of through-silicon via (TSV) design and placement to optimize the IR-drop and classification accuracy. For ResNet architectures in 3-D integration, we demonstrate that peripheral TSV placement provides an optimal balance between interconnect complexity and performance, achieving IR-drop below 10% of <inline-formula> <tex-math>$V_{text {DD}}$ </tex-math></inline-formula> while maintaining high classification accuracy.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"10-18"},"PeriodicalIF":2.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854426","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-17DOI: 10.1109/JXCDC.2025.3531616
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