Pub Date : 2026-01-09DOI: 10.1109/JXCDC.2025.3632955
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Pub Date : 2025-11-17DOI: 10.1109/JXCDC.2025.3633490
I. Sotnyk;O. Prokopenko
Artificial neurons based on antiferromagnetic (AFM) spin Hall oscillators (SHOs) are promising elements for creating ultrafast, energy-efficient neuromorphic computing systems. These structures can generate picosecond spikes in response to dc and ac electric currents, thereby mimicking the reaction of biological neurons to an external stimulus. However, conventional AFM neurons have only one input, which significantly limits their applications. In this article, we propose an approach to the implementation of a programmable artificial neuron (P-neuron) based on conventional AFM neurons in the form of a simple, two-layer neural network. Each neuron in the first layer has an independent input, and all of their outputs are connected to a single main neuron in the second layer. This configuration allows the sensitivity of system to individual input signals to be changed independently and in real time by regulating the dc current applied to the first-layer neurons, which makes it possible to program the entire P-neuron structure. In addition, the P-neuron demonstrates the ability for controlled training. We demonstrate that a multi-input P-neuron can successfully classify small images ($5times 5$ pixels) of English alphabet symbols. Recognition is based on analyzing the time characteristics of the output neuron signal and comparing them with reference samples. We believe that the obtained results are important for the development and optimization of ultrafast neural network based on AFM nanostructures and AFM spintronic devices capable of generating and processing (sub)terahertz-frequency signals.
{"title":"Antiferromagnetic Programmable Neuron: Structure, Training, and Pattern Recognition Applications","authors":"I. Sotnyk;O. Prokopenko","doi":"10.1109/JXCDC.2025.3633490","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633490","url":null,"abstract":"Artificial neurons based on antiferromagnetic (AFM) spin Hall oscillators (SHOs) are promising elements for creating ultrafast, energy-efficient neuromorphic computing systems. These structures can generate picosecond spikes in response to dc and ac electric currents, thereby mimicking the reaction of biological neurons to an external stimulus. However, conventional AFM neurons have only one input, which significantly limits their applications. In this article, we propose an approach to the implementation of a programmable artificial neuron (P-neuron) based on conventional AFM neurons in the form of a simple, two-layer neural network. Each neuron in the first layer has an independent input, and all of their outputs are connected to a single main neuron in the second layer. This configuration allows the sensitivity of system to individual input signals to be changed independently and in real time by regulating the dc current applied to the first-layer neurons, which makes it possible to program the entire P-neuron structure. In addition, the P-neuron demonstrates the ability for controlled training. We demonstrate that a multi-input P-neuron can successfully classify small images (<inline-formula> <tex-math>$5times 5$ </tex-math></inline-formula> pixels) of English alphabet symbols. Recognition is based on analyzing the time characteristics of the output neuron signal and comparing them with reference samples. We believe that the obtained results are important for the development and optimization of ultrafast neural network based on AFM nanostructures and AFM spintronic devices capable of generating and processing (sub)terahertz-frequency signals.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"9-17"},"PeriodicalIF":2.7,"publicationDate":"2025-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11250656","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-14DOI: 10.1109/JXCDC.2025.3633067
Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu
Resistive random access memory (RRAM) is a leading candidate for next-generation nonvolatile memory and neuromorphic computing. However, its performance is limited by inherent switching variability and uncertainties in spatiotemporal multiscale materials and processes. This study integrates multiphysics and multiscale modeling with uncertainty quantification (UQ) to systematically address these limitations and reduce uncertainties. UQ identifies critical inputs that govern key performance metrics, including theON/OFF ratio, forming voltage, and power consumption, reducing their statistical distributions with the probabilities of reliability analysis over 92%. The phase field model (PFM) captures the morphological evolution of conductive filament (CF) and, by incorporating a second-order time derivative for ion diffusion, reveals the impact of morphological fluctuations governing RRAM behavior. Drift diffusion simulations further demonstrate that bilayer structures confine CF fractures to the HfO2 layer through interfacial constraints. This modeling framework provides a systematic approach to mitigate variability and improve the design and reliability of RRAM devices.
{"title":"Integrated Spatiotemporal Multiscale- Multiphysics-Uncertainty Simulation for Controlling Variability in RRAM Devices","authors":"Ziyan Liao;Zhiheng Huang;Min Xiao;Yuezhong Meng;Hui Yan;Yang Liu","doi":"10.1109/JXCDC.2025.3633067","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3633067","url":null,"abstract":"Resistive random access memory (RRAM) is a leading candidate for next-generation nonvolatile memory and neuromorphic computing. However, its performance is limited by inherent switching variability and uncertainties in spatiotemporal multiscale materials and processes. This study integrates multiphysics and multiscale modeling with uncertainty quantification (UQ) to systematically address these limitations and reduce uncertainties. UQ identifies critical inputs that govern key performance metrics, including the<sc>ON</small>/<sc>OFF</small> ratio, forming voltage, and power consumption, reducing their statistical distributions with the probabilities of reliability analysis over 92%. The phase field model (PFM) captures the morphological evolution of conductive filament (CF) and, by incorporating a second-order time derivative for ion diffusion, reveals the impact of morphological fluctuations governing RRAM behavior. Drift diffusion simulations further demonstrate that bilayer structures confine CF fractures to the HfO2 layer through interfacial constraints. This modeling framework provides a systematic approach to mitigate variability and improve the design and reliability of RRAM devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"12 ","pages":"1-8"},"PeriodicalIF":2.7,"publicationDate":"2025-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11248831","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145969437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-07DOI: 10.1109/JXCDC.2025.3630217
Md. Hasan Raza Ansari;Bashayr Alqahtani;Naveen Kumar;Vihar Georgiev;Nazek El-Atab
This work highlights the potential application of raised source and drain (RSD) MOSFETs-based charge trapping memory (CTM) for next-generation computing applications. This simulation study presents a double-gate (DG)-RSD MOSFET technology with a short gate length (50 nm) to significantly improve the performance of logic-in-memory (LIM) and neuromorphic computing (NC) systems. By taking advantage of the superior electrostatic control and reduced parasitic resistance provided by RSD MOSFETs, this work aims to reduce energy consumption for LIM and NC applications. The CTM operation is based on the Fowler–Nordheim (FN) tunneling mechanism, performing 16 Boolean logic functions in two steps: program (PGM) and read operations, including or, and, nor, nand, xor, and xnor. Furthermore, the device shows synapse capability by mimicking long-term potentiation (LTP) and depression long-term depression (LTD) while achieving good linearity and symmetricity between the conductance values. The results reveal that energy consumption for LIM is ~21.4 and ~68.9 fJ for the NC application. This simulation result also demonstrates a high level of accuracy of 88.19%, with less than a 2.04% difference compared to software-based neural networks (90.23%). These multifunctional capabilities of DG-RSD-based CTM highlight the potential application for next-generation computing.
{"title":"Energy-Efficient Logic-in-Memory and Neuromorphic Computing in Raised Source and Drain MOSFETs","authors":"Md. Hasan Raza Ansari;Bashayr Alqahtani;Naveen Kumar;Vihar Georgiev;Nazek El-Atab","doi":"10.1109/JXCDC.2025.3630217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3630217","url":null,"abstract":"This work highlights the potential application of raised source and drain (RSD) MOSFETs-based charge trapping memory (CTM) for next-generation computing applications. This simulation study presents a double-gate (DG)-RSD MOSFET technology with a short gate length (50 nm) to significantly improve the performance of logic-in-memory (LIM) and neuromorphic computing (NC) systems. By taking advantage of the superior electrostatic control and reduced parasitic resistance provided by RSD MOSFETs, this work aims to reduce energy consumption for LIM and NC applications. The CTM operation is based on the Fowler–Nordheim (FN) tunneling mechanism, performing 16 Boolean logic functions in two steps: program (PGM) and read operations, including <sc>or</small>, <sc>and</small>, <sc>nor</small>, <sc>nand</small>, <sc>xor</small>, and <sc>xnor</small>. Furthermore, the device shows synapse capability by mimicking long-term potentiation (LTP) and depression long-term depression (LTD) while achieving good linearity and symmetricity between the conductance values. The results reveal that energy consumption for LIM is ~21.4 and ~68.9 fJ for the NC application. This simulation result also demonstrates a high level of accuracy of 88.19%, with less than a 2.04% difference compared to software-based neural networks (90.23%). These multifunctional capabilities of DG-RSD-based CTM highlight the potential application for next-generation computing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"197-204"},"PeriodicalIF":2.7,"publicationDate":"2025-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11232511","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145560776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-23DOI: 10.1109/JXCDC.2025.3624662
Md Rahatul Islam Udoy;Jack Hutchins;Shamiul Alam;Catherine Schuman;Ahmedullah Aziz
This article introduces a framework that establishes a cohesive link between the first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, are processed using machine learning (ML) algorithms to identify complex patterns and relationships. As these machine-learning models develop, they become tools for predicting behaviors beyond the reach of conventional modeling and simulation methods. Applied to circuit simulation, the framework improves understanding of electrical interactions, enhancing accuracy and speeding up design automation. As a proof of concept, we perform first principles-based simulations of the graphene nanoribbon field effect transistor (GNRFET), an exploratory device, and create a symbolic-regression-based ML model that can readily be integrated into advanced circuit simulation. This framework presents a template offering a unified approach that synergizes the strengths of first principles-based simulations and circuit-level design tools.
{"title":"Integrating Atomistic Insights With Circuit Simulations via Transformer-Driven Symbolic Regression","authors":"Md Rahatul Islam Udoy;Jack Hutchins;Shamiul Alam;Catherine Schuman;Ahmedullah Aziz","doi":"10.1109/JXCDC.2025.3624662","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624662","url":null,"abstract":"This article introduces a framework that establishes a cohesive link between the first principles-based simulations and circuit-level analyses using a machine learning-based compact modeling platform. Starting with atomistic simulations, the framework examines the microscopic details of material behavior, forming the foundation for later stages. The generated datasets, with molecular insights, are processed using machine learning (ML) algorithms to identify complex patterns and relationships. As these machine-learning models develop, they become tools for predicting behaviors beyond the reach of conventional modeling and simulation methods. Applied to circuit simulation, the framework improves understanding of electrical interactions, enhancing accuracy and speeding up design automation. As a proof of concept, we perform first principles-based simulations of the graphene nanoribbon field effect transistor (GNRFET), an exploratory device, and create a symbolic-regression-based ML model that can readily be integrated into advanced circuit simulation. This framework presents a template offering a unified approach that synergizes the strengths of first principles-based simulations and circuit-level design tools.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"179-187"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215792","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing paradigms. We propose modified Schottky barrier and hopping models for capturing the on- and off-mode operations of the FE diode, respectively, in conjunction with the multidomain Preisach model for incorporating the FE switching. Since the operating regime of the FE diode is determined by the polarization state and the sign of the applied voltage, directional dependence is also introduced in the proposed model to effectively capture the experimentally observed current–voltage characteristics. The proposed FE-diode model is validated by accurately reproducing two sets of asymmetric experimental current–voltage characteristics of BE/HZO/IGZO/TE FE diodes.
{"title":"A SPICE-Compatible Compact Model of Ferroelectric Diode","authors":"Musaib Rafiq;Mohammad Sajid Nazir;Ateeb Naseer;Yogesh Singh Chauhan;Shubham Sahay","doi":"10.1109/JXCDC.2025.3624212","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624212","url":null,"abstract":"In this work, for the first time, we present a SPICE-compatible compact model of ferroelectric (FE) diodes to enable their design exploration for diverse applications, including memory and unconventional computing paradigms. We propose modified Schottky barrier and hopping models for capturing the on- and off-mode operations of the FE diode, respectively, in conjunction with the multidomain Preisach model for incorporating the FE switching. Since the operating regime of the FE diode is determined by the polarization state and the sign of the applied voltage, directional dependence is also introduced in the proposed model to effectively capture the experimentally observed current–voltage characteristics. The proposed FE-diode model is validated by accurately reproducing two sets of asymmetric experimental current–voltage characteristics of BE/HZO/IGZO/TE FE diodes.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"166-170"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214353","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-23DOI: 10.1109/JXCDC.2025.3624653
Swati Deshwal;Sufia Shahin;Anirban Kar;Yogesh S. Chauhan;Hussam Amrouch
This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework combining reaction–diffusion (RD) and reaction–drift–diffusion (RDD) mechanisms in TCAD. BEOL parasitics are extracted using TCAD-generated structures. Both the CFET and NSFET exhibit similar degradation behavior under NBTI stress. However, CFETs show more pronounced degradation due to HCD, primarily driven by stronger SHE. Next, we simulate CFET- and NSFET-based 3-D inverters and SRAM structures in TCAD, with BEOL interconnects up to M3 level, to study the impact of parasitics on the circuit performance. Meanwhile, CFETs offer ~50% area savings at the standard cell level and lower parasitics, leading to a 42% improvement in inverter propagation delay. The SRAM cells based on CFETs are also evaluated and compared against NSFET in terms of area, noise margins, and performance. The CFET SRAM cell provides area gain along with faster and more stable write operations, providing a potential advantage in high-performance applications compared to NSFET.
{"title":"Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET","authors":"Swati Deshwal;Sufia Shahin;Anirban Kar;Yogesh S. Chauhan;Hussam Amrouch","doi":"10.1109/JXCDC.2025.3624653","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624653","url":null,"abstract":"This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD), and the impact of back-end-of-line (BEOL) parasitics on standard cell performance. NBTI degradation is modeled using a framework combining reaction–diffusion (RD) and reaction–drift–diffusion (RDD) mechanisms in TCAD. BEOL parasitics are extracted using TCAD-generated structures. Both the CFET and NSFET exhibit similar degradation behavior under NBTI stress. However, CFETs show more pronounced degradation due to HCD, primarily driven by stronger SHE. Next, we simulate CFET- and NSFET-based 3-D inverters and SRAM structures in TCAD, with BEOL interconnects up to M3 level, to study the impact of parasitics on the circuit performance. Meanwhile, CFETs offer ~50% area savings at the standard cell level and lower parasitics, leading to a 42% improvement in inverter propagation delay. The SRAM cells based on CFETs are also evaluated and compared against NSFET in terms of area, noise margins, and performance. The CFET SRAM cell provides area gain along with faster and more stable write operations, providing a potential advantage in high-performance applications compared to NSFET.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"188-196"},"PeriodicalIF":2.7,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11215725","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145510090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/JXCDC.2025.3624217
Axel I. Saenz Rodriguez;Oksana Ostroverkhova;Pallavi Dhagat
We explore the effects of layered geometries of 2-D quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation of a 2-D quantum spin system with a shifted bilayer square lattice through the linear spin wave (LSW) approximation of quantum field theory (QFT). Inspired by recent interest in 2-D van der Waals (vdW) magnetic materials, we consider both short-range interactions given by nearest-neighbor intralayer ferromagnetic and interlayer antiferromagnetic spin-exchange interactions and long-range dipole–dipole interactions. This case, along with lattice shifts, has not been treated in the literature via LSW theory. Computations show the gap in the frequencies for the two lowest-energy magnon modes at zero wavenumber that depend on the horizontal and vertical layer shifts. The frequency gap is attributed to the long-range dipole interaction with the gap becoming more sensitive to the horizontal layer shifts for small layer separation. Our general framework is suitable for numerical computations of a wide collection of 2-D lattice models and presents an essential first step toward a comprehensive model that can incorporate quantum effects leading to quantifiable predictions of additional physical properties, for example, spin coherence length and damping, of interest for engineering of spintronic devices.
{"title":"Quantum Field Theory Model for Spin-Based Devices Using 2-D van der Waals Materials","authors":"Axel I. Saenz Rodriguez;Oksana Ostroverkhova;Pallavi Dhagat","doi":"10.1109/JXCDC.2025.3624217","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3624217","url":null,"abstract":"We explore the effects of layered geometries of 2-D quantum spin systems as a method to tune and control material properties for spintronic devices. We analyze the dispersion relation of a 2-D quantum spin system with a shifted bilayer square lattice through the linear spin wave (LSW) approximation of quantum field theory (QFT). Inspired by recent interest in 2-D van der Waals (vdW) magnetic materials, we consider both short-range interactions given by nearest-neighbor intralayer ferromagnetic and interlayer antiferromagnetic spin-exchange interactions and long-range dipole–dipole interactions. This case, along with lattice shifts, has not been treated in the literature via LSW theory. Computations show the gap in the frequencies for the two lowest-energy magnon modes at zero wavenumber that depend on the horizontal and vertical layer shifts. The frequency gap is attributed to the long-range dipole interaction with the gap becoming more sensitive to the horizontal layer shifts for small layer separation. Our general framework is suitable for numerical computations of a wide collection of 2-D lattice models and presents an essential first step toward a comprehensive model that can incorporate quantum effects leading to quantifiable predictions of additional physical properties, for example, spin coherence length and damping, of interest for engineering of spintronic devices.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"171-178"},"PeriodicalIF":2.7,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11214338","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-14DOI: 10.1109/JXCDC.2025.3621279
Piyush Kumar;Da Eun Shim;Azad Naeemi
This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. Based on ASAP7 PDK design rules, we create the bit-cell and peripheral layouts for SOT-MRAM and design the entire array. In addition, we quantify various array-level tradeoffs using full array SPICE circuit simulations based on layout-extracted parasitic netlists. This is then used to design the entire SOT-MRAM system along with a memory controller. Based on place and route (PnR), we evaluate the system-level PPA for various memory capacities, demonstrating bit densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s. Our results show that increasing the memory size from 1 to 16 Mb results in a performance degradation of ~33%–38% due to the impact of interconnect delay. As the results show that the performance of SOT-MRAM is limited by the interconnect delay, it is critical to co-optimize the device and interconnect technology to make SOT-MRAM a viable option at the advanced technology nodes. In addition, material discovery for field-free perpendicular magnetization switching in SOT devices based on out-of-plane spin torque is necessary to achieve SRAM-level write energies.
{"title":"Comprehensive Device to System Co-Design for SOT-MRAM at the 7 nm Node","authors":"Piyush Kumar;Da Eun Shim;Azad Naeemi","doi":"10.1109/JXCDC.2025.3621279","DOIUrl":"https://doi.org/10.1109/JXCDC.2025.3621279","url":null,"abstract":"This work presents a comprehensive spin-orbit torque (SOT)-based magnetic random access memory (MRAM) design at the 7 nm technology node, spanning from device-level characteristics to system-level power performance area (PPA). At the device level, we show the tradeoffs among the write current, error rate, and time, based on mircomagnetic simulations. Based on ASAP7 PDK design rules, we create the bit-cell and peripheral layouts for SOT-MRAM and design the entire array. In addition, we quantify various array-level tradeoffs using full array SPICE circuit simulations based on layout-extracted parasitic netlists. This is then used to design the entire SOT-MRAM system along with a memory controller. Based on place and route (PnR), we evaluate the system-level PPA for various memory capacities, demonstrating bit densities up to 14.8 Mb/mm2 and read bandwidths up to 2.98 GB/s. Our results show that increasing the memory size from 1 to 16 Mb results in a performance degradation of ~33%–38% due to the impact of interconnect delay. As the results show that the performance of SOT-MRAM is limited by the interconnect delay, it is critical to co-optimize the device and interconnect technology to make SOT-MRAM a viable option at the advanced technology nodes. In addition, material discovery for field-free perpendicular magnetization switching in SOT devices based on out-of-plane spin torque is necessary to achieve SRAM-level write energies.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"11 ","pages":"139-147"},"PeriodicalIF":2.7,"publicationDate":"2025-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11202876","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145405389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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