Pub Date : 2023-04-11DOI: 10.1109/JXCDC.2023.3266136
Brandon R. Zink;Yang Lv;Masoud Zabihi;Husrev Cilasun;Sachin S. Sapatnekar;Ulya R. Karpuzcu;Marc D. Riedel;Jian-Ping Wang
Stochastic computing (SC) has emerged as a promising solution for performing complex functions on large amounts of data to meet future computing demands. However, the hardware needed to generate random bit-streams using conventional CMOS-based technologies drastically increases the area and delay cost. Area costs can be reduced using spintronics-based random number generators (RNGs), and however, this will not alleviate the delay costs since stochastic bit generation is still performed separately from the computation. In this article, we present an SC method of embedding stochastic bit generation and processing in a computational random access memory (CRAM) array, which we refer to as SC-CRAM. We demonstrate that SC-CRAM is a resilient and low-cost method for image processing, Bayesian inference systems, and Bayesian belief networks.
{"title":"A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM)","authors":"Brandon R. Zink;Yang Lv;Masoud Zabihi;Husrev Cilasun;Sachin S. Sapatnekar;Ulya R. Karpuzcu;Marc D. Riedel;Jian-Ping Wang","doi":"10.1109/JXCDC.2023.3266136","DOIUrl":"10.1109/JXCDC.2023.3266136","url":null,"abstract":"Stochastic computing (SC) has emerged as a promising solution for performing complex functions on large amounts of data to meet future computing demands. However, the hardware needed to generate random bit-streams using conventional CMOS-based technologies drastically increases the area and delay cost. Area costs can be reduced using spintronics-based random number generators (RNGs), and however, this will not alleviate the delay costs since stochastic bit generation is still performed separately from the computation. In this article, we present an SC method of embedding stochastic bit generation and processing in a computational random access memory (CRAM) array, which we refer to as SC-CRAM. We demonstrate that SC-CRAM is a resilient and low-cost method for image processing, Bayesian inference systems, and Bayesian belief networks.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"29-37"},"PeriodicalIF":2.4,"publicationDate":"2023-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10099030.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43855515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-10DOI: 10.1109/JXCDC.2023.3265803
Piergiulio Mannocci;Daniele Ielmini
Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.
{"title":"A Generalized Block-Matrix Circuit for Closed-Loop Analog In-Memory Computing","authors":"Piergiulio Mannocci;Daniele Ielmini","doi":"10.1109/JXCDC.2023.3265803","DOIUrl":"10.1109/JXCDC.2023.3265803","url":null,"abstract":"Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"47-55"},"PeriodicalIF":2.4,"publicationDate":"2023-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10097860.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45573365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-17DOI: 10.1109/JXCDC.2023.3258431
Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti
Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is far lower than their static random access memory (SRAM)-CIM counterparts due to low device ON/ OFF ratio. In this work, we combine a nonvolatile memory based on a voltage-controlled magnetic tunneling junction (VC-MTJ) device, called voltage-controlled MRAM or VC-MRAM, and accurate switched-capacitor-based CIM using a novel in situ magnetic-to-digital converter (MDC). The VC-MTJ device has demonstrated $10times $ lower write energy and switching time compared to STT-MRAM device and has comparable density, read energy, and read latency. The in situ MDCs embedded inside each VC-MRAM row convert magnetically stored weight information to CMOS logic levels and enable switched-capacitor-based multiply–accumulate (MAC) operation with accuracy comparable to the state-of-the-art SRAM-CIM. This article describes the schematic and layout level design of a VC-MRAM CIM macro in 28 nm. This is the first nonvolatile CIM design to enable analog MAC computation with 256 parallel rows turned ON simultaneously without degradation in dynamic range (< 1 LSB). Detailed circuit simulations including experimentally validated VC-MTJ compact models show $1.5times $ higher energy efficiency and $2times $ higher density compared to the state-of-the-art SRAM-based CIM.
{"title":"A Nonvolatile Compute-in-Memory Macro Using Voltage-Controlled MRAM and In Situ Magnetic-to-Digital Converter","authors":"Vinod Kurian Jacob;Jiyue Yang;Haoran He;Puneet Gupta;Kang L Wang;Sudhakar Pamarti","doi":"10.1109/JXCDC.2023.3258431","DOIUrl":"10.1109/JXCDC.2023.3258431","url":null,"abstract":"Compute-in-memory (CIM) accelerator has become a popular solution to achieve high energy efficiency for deep learning applications in edge devices. Recent works have demonstrated CIM macros using nonvolatile memories [spin transfer torque (STT)-MRAM and resistive random access memory (RRAM)] to take advantages of their nonvolatility and high density. However, effective computation dynamic range is far lower than their static random access memory (SRAM)-CIM counterparts due to low device ON/ OFF ratio. In this work, we combine a nonvolatile memory based on a voltage-controlled magnetic tunneling junction (VC-MTJ) device, called voltage-controlled MRAM or VC-MRAM, and accurate switched-capacitor-based CIM using a novel in situ magnetic-to-digital converter (MDC). The VC-MTJ device has demonstrated \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 lower write energy and switching time compared to STT-MRAM device and has comparable density, read energy, and read latency. The in situ MDCs embedded inside each VC-MRAM row convert magnetically stored weight information to CMOS logic levels and enable switched-capacitor-based multiply–accumulate (MAC) operation with accuracy comparable to the state-of-the-art SRAM-CIM. This article describes the schematic and layout level design of a VC-MRAM CIM macro in 28 nm. This is the first nonvolatile CIM design to enable analog MAC computation with 256 parallel rows turned ON simultaneously without degradation in dynamic range (< 1 LSB). Detailed circuit simulations including experimentally validated VC-MTJ compact models show \u0000<inline-formula> <tex-math>$1.5times $ </tex-math></inline-formula>\u0000 higher energy efficiency and \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000 higher density compared to the state-of-the-art SRAM-based CIM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"56-64"},"PeriodicalIF":2.4,"publicationDate":"2023-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10075423.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41359420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-14DOI: 10.1109/JXCDC.2023.3255788
Tian Xie;Shimeng Yu;Shaolan Li
Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. Instead of using access transistors as switches, this work explores their analog characteristics as common-gate current buffers. So the cell current can be minimized and the output impedance is boosted. The idea of In-ADC Computing (IAC) is also proposed to further decrease the complexity of the peripheral circuits. Benefiting from the proposed ideas, a pretrained VGG-8 network based on the CIFAR-10 dataset can be implemented, and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit multiply-and-accumulate (MAC) operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still being able to operate in a power-efficient way.
{"title":"A High-Parallelism RRAM-Based Compute-In-Memory Macro With Intrinsic Impedance Boosting and In-ADC Computing","authors":"Tian Xie;Shimeng Yu;Shaolan Li","doi":"10.1109/JXCDC.2023.3255788","DOIUrl":"10.1109/JXCDC.2023.3255788","url":null,"abstract":"Resistive random access memory (RRAM) is considered to be a promising compute-in-memory (CIM) platform; however, they tend to lose energy efficiency quickly in high-throughput and high-resolution cases. Instead of using access transistors as switches, this work explores their analog characteristics as common-gate current buffers. So the cell current can be minimized and the output impedance is boosted. The idea of In-ADC Computing (IAC) is also proposed to further decrease the complexity of the peripheral circuits. Benefiting from the proposed ideas, a pretrained VGG-8 network based on the CIFAR-10 dataset can be implemented, and an accuracy of 87.2% is achieved with 8.9 TOPS/W energy efficiency (for 8-bit multiply-and-accumulate (MAC) operation), demonstrating that the proposed techniques enable low-distortion partial sum results while still being able to operate in a power-efficient way.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"38-46"},"PeriodicalIF":2.4,"publicationDate":"2023-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10070378.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46523822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor defined by Moore’s law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning (ML) and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.
{"title":"A Full-Stack View of Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms","authors":"Shuvro Chowdhury;Andrea Grimaldi;Navid Anjum Aadit;Shaila Niazi;Masoud Mohseni;Shun Kanai;Hideo Ohno;Shunsuke Fukami;Luke Theogarajan;Giovanni Finocchio;Supriyo Datta;Kerem Y. Camsari","doi":"10.1109/JXCDC.2023.3256981","DOIUrl":"10.1109/JXCDC.2023.3256981","url":null,"abstract":"The transistor celebrated its 75th birthday in 2022. The continued scaling of the transistor defined by Moore’s law continues, albeit at a slower pace. Meanwhile, computing demands and energy consumption required by modern artificial intelligence (AI) algorithms have skyrocketed. As an alternative to scaling transistors for general-purpose computing, the integration of transistors with unconventional technologies has emerged as a promising path for domain-specific computing. In this article, we provide a full-stack review of probabilistic computing with p-bits as a representative example of the energy-efficient and domain-specific computing movement. We argue that p-bits could be used to build energy-efficient probabilistic systems, tailored for probabilistic algorithms and applications. From hardware, architecture, and algorithmic perspectives, we outline the main applications of probabilistic computers ranging from probabilistic machine learning (ML) and AI to combinatorial optimization and quantum simulation. Combining emerging nanodevices with the existing CMOS ecosystem will lead to probabilistic computers with orders of magnitude improvements in energy efficiency and probabilistic sampling, potentially unlocking previously unexplored regimes for powerful probabilistic algorithms.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"1-11"},"PeriodicalIF":2.4,"publicationDate":"2023-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10068500.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41667070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-31DOI: 10.1109/JXCDC.2023.3241045
Mohammad Khairul Bashar;Zongli Lin;Nikhil Shukla
Dynamical systems can offer a novel non-Boolean approach to computing. Specifically, the natural minimization of energy in the system is a valuable property for minimizing the objective functions of combinatorial optimization problems, many of which are still challenging to solve using conventional digital solvers. In this work, we design two oscillator-inspired dynamical systems to solve quintessential computationally intractable problems in Boolean satisfiability (SAT). The system dynamics are engineered such that they facilitate solutions to two different flavors of the SAT problem. We formulate the first dynamical system to compute the solution to the 3-SAT problem, while for the second system, we show that its dynamics map to the solution of the Max-not-all-equal (NAE)-3-SAT problem. Our work advances our understanding of how this physics-inspired approach can be used to address challenging problems in computing.
{"title":"Oscillator-Inspired Dynamical Systems to Solve Boolean Satisfiability","authors":"Mohammad Khairul Bashar;Zongli Lin;Nikhil Shukla","doi":"10.1109/JXCDC.2023.3241045","DOIUrl":"10.1109/JXCDC.2023.3241045","url":null,"abstract":"Dynamical systems can offer a novel non-Boolean approach to computing. Specifically, the natural minimization of energy in the system is a valuable property for minimizing the objective functions of combinatorial optimization problems, many of which are still challenging to solve using conventional digital solvers. In this work, we design two oscillator-inspired dynamical systems to solve quintessential computationally intractable problems in Boolean satisfiability (SAT). The system dynamics are engineered such that they facilitate solutions to two different flavors of the SAT problem. We formulate the first dynamical system to compute the solution to the 3-SAT problem, while for the second system, we show that its dynamics map to the solution of the Max-not-all-equal (NAE)-3-SAT problem. Our work advances our understanding of how this physics-inspired approach can be used to address challenging problems in computing.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"12-20"},"PeriodicalIF":2.4,"publicationDate":"2023-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10032530.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43177120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-09DOI: 10.1109/JXCDC.2023.3235113
Mohammad Khairul Bashar;Antik Mallick;Avik W. Ghosh;Nikhil Shukla
The intrinsic energy minimization in dynamical systems offers a valuable tool for minimizing the objective functions of computationally challenging problems in combinatorial optimization. However, most prior works have focused on mapping such dynamics to combinatorial optimization problems whose objective functions have quadratic degree [e.g., maximum cut (MaxCut)]; such problems can be represented and analyzed using graphs. However, the work on developing such models for problems that need objective functions with degree greater than two, and subsequently, entail the use of hypergraph data structures, is relatively sparse. In this work, we develop dynamical system-inspired computational models for several such problems. Specifically, we define the “energy function” for hypergraph-based combinatorial problems ranging from Boolean Satisfiability (SAT) and its variants to integer factorization, and subsequently, define the resulting system dynamics. We also show that the design approach is applicable to optimization problems with quadratic degree, and use it to develop a new dynamical system formulation for minimizing the Ising Hamiltonian. Our work not only expands on the scope of problems that can be directly mapped to, and solved using physics-inspired models, but also creates new opportunities to design high-performance accelerators for solving combinatorial optimization.
{"title":"Dynamical System-Based Computational Models for Solving Combinatorial Optimization on Hypergraphs","authors":"Mohammad Khairul Bashar;Antik Mallick;Avik W. Ghosh;Nikhil Shukla","doi":"10.1109/JXCDC.2023.3235113","DOIUrl":"10.1109/JXCDC.2023.3235113","url":null,"abstract":"The intrinsic energy minimization in dynamical systems offers a valuable tool for minimizing the objective functions of computationally challenging problems in combinatorial optimization. However, most prior works have focused on mapping such dynamics to combinatorial optimization problems whose objective functions have quadratic degree [e.g., maximum cut (MaxCut)]; such problems can be represented and analyzed using graphs. However, the work on developing such models for problems that need objective functions with degree greater than two, and subsequently, entail the use of hypergraph data structures, is relatively sparse. In this work, we develop dynamical system-inspired computational models for several such problems. Specifically, we define the “energy function” for hypergraph-based combinatorial problems ranging from Boolean Satisfiability (SAT) and its variants to integer factorization, and subsequently, define the resulting system dynamics. We also show that the design approach is applicable to optimization problems with quadratic degree, and use it to develop a new dynamical system formulation for minimizing the Ising Hamiltonian. Our work not only expands on the scope of problems that can be directly mapped to, and solved using physics-inspired models, but also creates new opportunities to design high-performance accelerators for solving combinatorial optimization.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"9 1","pages":"21-28"},"PeriodicalIF":2.4,"publicationDate":"2023-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/10138050/10011425.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48914151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-23DOI: 10.1109/JXCDC.2022.3231550
Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia
Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random “coinflips” while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer (FL) magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is a need to systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high-quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution versus bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with a small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.
{"title":"Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions","authors":"Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia","doi":"10.1109/JXCDC.2022.3231550","DOIUrl":"10.1109/JXCDC.2022.3231550","url":null,"abstract":"Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random “coinflips” while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer (FL) magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is a need to systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high-quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution versus bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with a small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"194-202"},"PeriodicalIF":2.4,"publicationDate":"2022-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09998481.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41722839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-20DOI: 10.1109/JXCDC.2022.3230925
Piyush Kumar;Azad Naeemi
This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.
{"title":"High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist","authors":"Piyush Kumar;Azad Naeemi","doi":"10.1109/JXCDC.2022.3230925","DOIUrl":"10.1109/JXCDC.2022.3230925","url":null,"abstract":"This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"185-193"},"PeriodicalIF":2.4,"publicationDate":"2022-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09994702.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44088062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-08DOI: 10.1109/JXCDC.2022.3227774
Debasis Das;Xuanyao Fong
Spintronic artificial spiking neurons are promising due to their ability to closely mimic the leaky integrate-and-fire (LIF) dynamics of the biological LIF spiking neuron. However, the neuron needs to be reset after firing. Few of the spintronic neurons that have been proposed in the literature discuss the reset process in detail. In this article, we discuss the various schemes to achieve this reset in a magnetic domain wall (DW)-based spintronic neuron in which the position of the DW represents the membrane potential. In all the spintronic neurons studied, the neuron enters a refractory period and is reset when the DW reaches a particular position. We show that the self-reset operation in the neuron devices consumes energy that can vary from several pJ to a few fJ, which highlights the importance of the reset strategy in improving the energy efficiency of spintronic artificial spiking neurons.
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