Pub Date : 2022-12-23DOI: 10.1109/JXCDC.2022.3231550
Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia
Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random “coinflips” while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer (FL) magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is a need to systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high-quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution versus bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with a small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.
{"title":"Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions","authors":"Samuel Liu;Jaesuk Kwon;Paul W. Bessler;Suma G. Cardwell;Catherine Schuman;J. Darby Smith;James B. Aimone;Shashank Misra;Jean Anne C. Incorvia","doi":"10.1109/JXCDC.2022.3231550","DOIUrl":"10.1109/JXCDC.2022.3231550","url":null,"abstract":"Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random “coinflips” while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer (FL) magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is a need to systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high-quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution versus bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with a small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"194-202"},"PeriodicalIF":2.4,"publicationDate":"2022-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09998481.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41722839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-20DOI: 10.1109/JXCDC.2022.3230925
Piyush Kumar;Azad Naeemi
This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.
{"title":"High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist","authors":"Piyush Kumar;Azad Naeemi","doi":"10.1109/JXCDC.2022.3230925","DOIUrl":"10.1109/JXCDC.2022.3230925","url":null,"abstract":"This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"185-193"},"PeriodicalIF":2.4,"publicationDate":"2022-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09994702.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44088062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-08DOI: 10.1109/JXCDC.2022.3227774
Debasis Das;Xuanyao Fong
Spintronic artificial spiking neurons are promising due to their ability to closely mimic the leaky integrate-and-fire (LIF) dynamics of the biological LIF spiking neuron. However, the neuron needs to be reset after firing. Few of the spintronic neurons that have been proposed in the literature discuss the reset process in detail. In this article, we discuss the various schemes to achieve this reset in a magnetic domain wall (DW)-based spintronic neuron in which the position of the DW represents the membrane potential. In all the spintronic neurons studied, the neuron enters a refractory period and is reset when the DW reaches a particular position. We show that the self-reset operation in the neuron devices consumes energy that can vary from several pJ to a few fJ, which highlights the importance of the reset strategy in improving the energy efficiency of spintronic artificial spiking neurons.
{"title":"Self-Reset Schemes for Magnetic Domain Wall-Based Neuron","authors":"Debasis Das;Xuanyao Fong","doi":"10.1109/JXCDC.2022.3227774","DOIUrl":"10.1109/JXCDC.2022.3227774","url":null,"abstract":"Spintronic artificial spiking neurons are promising due to their ability to closely mimic the leaky integrate-and-fire (LIF) dynamics of the biological LIF spiking neuron. However, the neuron needs to be reset after firing. Few of the spintronic neurons that have been proposed in the literature discuss the reset process in detail. In this article, we discuss the various schemes to achieve this reset in a magnetic domain wall (DW)-based spintronic neuron in which the position of the DW represents the membrane potential. In all the spintronic neurons studied, the neuron enters a refractory period and is reset when the DW reaches a particular position. We show that the self-reset operation in the neuron devices consumes energy that can vary from several pJ to a few fJ, which highlights the importance of the reset strategy in improving the energy efficiency of spintronic artificial spiking neurons.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"166-172"},"PeriodicalIF":2.4,"publicationDate":"2022-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09976922.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48684960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-08DOI: 10.1109/JXCDC.2022.3227062
Brandon R. Zink;Yang Lv;Jian-Ping Wang
Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as recognition, classification, and prediction. This is because these tasks require parallel processing on large datasets. Stochastic computing (SC) is a promising alternative to conventional binary computing schemes due to its low area cost, low processing power, and robustness to noise. However, the large area and energy costs for random number generation with CMOS-based circuits make SC impractical for most hardware implementations. For this reason, beyond-CMOS approaches to random number generation have been investigated in recent years. Spintronics is one of the most promising approaches due to the intrinsic stochasticity of the magnetic tunnel junction (MTJ). In this review article, we provide an overview of the literature published in recent years investigating the tunable, intrinsic stochasticity of MTJs and proposing practical methods for random number generation using spintronic hardware.
{"title":"Review of Magnetic Tunnel Junctions for Stochastic Computing","authors":"Brandon R. Zink;Yang Lv;Jian-Ping Wang","doi":"10.1109/JXCDC.2022.3227062","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3227062","url":null,"abstract":"Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as recognition, classification, and prediction. This is because these tasks require parallel processing on large datasets. Stochastic computing (SC) is a promising alternative to conventional binary computing schemes due to its low area cost, low processing power, and robustness to noise. However, the large area and energy costs for random number generation with CMOS-based circuits make SC impractical for most hardware implementations. For this reason, beyond-CMOS approaches to random number generation have been investigated in recent years. Spintronics is one of the most promising approaches due to the intrinsic stochasticity of the magnetic tunnel junction (MTJ). In this review article, we provide an overview of the literature published in recent years investigating the tunable, intrinsic stochasticity of MTJs and proposing practical methods for random number generation using spintronic hardware.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"173-184"},"PeriodicalIF":2.4,"publicationDate":"2022-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/09976889.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/JXCDC.2022.3231761
{"title":"INFORMATION FOR AUTHORS","authors":"","doi":"10.1109/JXCDC.2022.3231761","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3231761","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/10102640.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/JXCDC.2023.3238030
Mohammad Nazmus Sakib;Hamed Vakili;Samiran Ganguly;Avik W. Ghosh;Mircea Stan
Magnetic racetrack memory has frequently been complicated by the pinning of domain wall bits on the one hand and the need to engineer precise synchronization and inter-track repulsion between skyrmionic bits on the other. Such proposals, however, do not capitalize on the complex 2-D motion of skyrmions, such as transverse Magnus force that tends to deviate the skyrmion trajectory from rectilinear motion along the current drive. The transverse deviation associated with such a skyrmion Hall effect is normally considered a liability for skyrmions, and efforts have focused on eliminating rather than utilizing it for proposed device applications. We propose a simple single skyrmion-based circuit macro with elementary and higher-order logic gates that utilize Magnus force and propose reconfigurable logic built on these gates. We demonstrate the reliability of the proposed approach with micromagnetics simulation. The energy consumption in this circuit lies mainly in the overhead, with the racetrack consuming a small fraction. The energy–delay product (EDP) is correspondingly low and can be improved by boosting the skyrmion speed.
{"title":"SSRL: Single Skyrmion Reconfigurable Logic Utilizing 2-D Magnus Force on Magnetic Racetracks","authors":"Mohammad Nazmus Sakib;Hamed Vakili;Samiran Ganguly;Avik W. Ghosh;Mircea Stan","doi":"10.1109/JXCDC.2023.3238030","DOIUrl":"10.1109/JXCDC.2023.3238030","url":null,"abstract":"Magnetic racetrack memory has frequently been complicated by the pinning of domain wall bits on the one hand and the need to engineer precise synchronization and inter-track repulsion between skyrmionic bits on the other. Such proposals, however, do not capitalize on the complex 2-D motion of skyrmions, such as transverse Magnus force that tends to deviate the skyrmion trajectory from rectilinear motion along the current drive. The transverse deviation associated with such a skyrmion Hall effect is normally considered a liability for skyrmions, and efforts have focused on eliminating rather than utilizing it for proposed device applications. We propose a simple single skyrmion-based circuit macro with elementary and higher-order logic gates that utilize Magnus force and propose reconfigurable logic built on these gates. We demonstrate the reliability of the proposed approach with micromagnetics simulation. The energy consumption in this circuit lies mainly in the overhead, with the racetrack consuming a small fraction. The energy–delay product (EDP) is correspondingly low and can be improved by boosting the skyrmion speed.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"203-211"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10021607.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41852686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/JXCDC.2022.3231764
Jae-Sun Seo
Deep neural networks (DNNs) have shown extraordinary performance in recent years for various applications including image classification, object detection, speech recognition, natural language processing, etc. Accuracydriven DNN architectures tend to increase the model sizes and computations at a very fast pace, demanding a massive amount of hardware resources. Frequent communication between the processing engine and the ON-/OFF-chip memory leads to high energy consumption, which becomes a bottleneck for the conventional DNN accelerator design.
{"title":"Special Topic on Energy-Efficient Compute-in-Memory With Emerging Devices","authors":"Jae-Sun Seo","doi":"10.1109/JXCDC.2022.3231764","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3231764","url":null,"abstract":"Deep neural networks (DNNs) have shown extraordinary performance in recent years for various applications including image classification, object detection, speech recognition, natural language processing, etc. Accuracydriven DNN architectures tend to increase the model sizes and computations at a very fast pace, demanding a massive amount of hardware resources. Frequent communication between the processing engine and the ON-/OFF-chip memory leads to high energy consumption, which becomes a bottleneck for the conventional DNN accelerator design.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"iii-v"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/10006410.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49978852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/JXCDC.2022.3218810
{"title":"RFIC 2023 Call for Papers","authors":"","doi":"10.1109/JXCDC.2022.3218810","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3218810","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"155-156"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9969523/10102698.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49950212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/JXCDC.2023.3268019
{"title":"2022 Index IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Vol. 8","authors":"","doi":"10.1109/JXCDC.2023.3268019","DOIUrl":"10.1109/JXCDC.2023.3268019","url":null,"abstract":"","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 2","pages":"212-218"},"PeriodicalIF":2.4,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9998452/10108913.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44065875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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