Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143391
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本刊的编辑委员会、理事会、现任工作人员、委员会成员和/或社团编辑。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2022.3143391","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3143391","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09916563.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49962921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143399
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本刊的编辑委员会、理事会、现任工作人员、委员会成员和/或社团编辑。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits publication information","authors":"","doi":"10.1109/JXCDC.2022.3143399","DOIUrl":"10.1109/JXCDC.2022.3143399","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C2-C2"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09916566.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43858938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3181925
Siri Narla, Piyush Kumar, Ann Franchesca Laguna, D. Reis, X. S. Hu, M. Niemier, A. Naeemi
This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with $1.35times $ and $14.4times $ improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below $10^{-4}$ while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a $2times $ energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.
{"title":"Modeling and Design for Magnetoelectric Ternary Content Addressable Memory (TCAM)","authors":"Siri Narla, Piyush Kumar, Ann Franchesca Laguna, D. Reis, X. S. Hu, M. Niemier, A. Naeemi","doi":"10.1109/JXCDC.2022.3181925","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3181925","url":null,"abstract":"This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with <inline-formula> <tex-math notation=\"LaTeX\">$1.35times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$14.4times $ </tex-math></inline-formula> improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below <inline-formula> <tex-math notation=\"LaTeX\">$10^{-4}$ </tex-math></inline-formula> while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a <inline-formula> <tex-math notation=\"LaTeX\">$2times $ </tex-math></inline-formula> energy-delay–area-product (EDAP) improvement over an SRAM-TCAM.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"44-52"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62234230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143393
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
这些说明提供了为本出版物准备论文的指导方针。为在本期刊上发表文章的作者提供信息。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Information for Authors","authors":"","doi":"10.1109/JXCDC.2022.3143393","DOIUrl":"10.1109/JXCDC.2022.3143393","url":null,"abstract":"These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09916562.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44907479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3188366
Siddhartha Raman Sundara Raman;Shanshan Xie;Jaydeep P. Kulkarni
Compute-in-memory (CIM) is a promising approach for efficiently performing data-centric computing (such as neural network computations). Among the multiple semiconductor memory technologies, embedded DRAM (eDRAM), which integrates the DRAM bit cell with high-performance logic transistors, can enable efficient CIM designs. However, the silicon-based eDRAM technology suffers from poor retention time-incurring significant refresh power overhead. However, eDRAM using back-end-of-line (BEOL) integrated $C$ -axis aligned crystalline (CAAC) indium–gallium–zinc–oxide (IGZO) transistors, exhibiting extreme low leakage, is a promising memory technology with lower refresh power overhead. A long retention time in IGZO eDRAM can enable multilevel cell functionality, which can improve its efficacy in CIM applications. In this article, we explore a capacitorless IGZO eDRAM-based multilevel cell, capable of storing 1.5 bits/cell for CIM designs focused on deep neural network (DNN) inference applications. We perform a detailed design space exploration of IGZO eDRAM sensitivity to process temperature variations for read, write, and retention operations followed by architecture-level simulations comparing performance and energy for different workloads. The effectiveness of IGZO eDRAM-based CIM architecture is evaluated using a representative neural network, and the proposed approach achieves 82% Top-1 inference accuracy for the CIFAR-10 dataset, compared with 87% software accuracy with high bit cell storage density.
{"title":"IGZO CIM: Enabling In-Memory Computations Using Multilevel Capacitorless Indium–Gallium–Zinc–Oxide-Based Embedded DRAM Technology","authors":"Siddhartha Raman Sundara Raman;Shanshan Xie;Jaydeep P. Kulkarni","doi":"10.1109/JXCDC.2022.3188366","DOIUrl":"10.1109/JXCDC.2022.3188366","url":null,"abstract":"Compute-in-memory (CIM) is a promising approach for efficiently performing data-centric computing (such as neural network computations). Among the multiple semiconductor memory technologies, embedded DRAM (eDRAM), which integrates the DRAM bit cell with high-performance logic transistors, can enable efficient CIM designs. However, the silicon-based eDRAM technology suffers from poor retention time-incurring significant refresh power overhead. However, eDRAM using back-end-of-line (BEOL) integrated \u0000<inline-formula> <tex-math>$C$ </tex-math></inline-formula>\u0000-axis aligned crystalline (CAAC) indium–gallium–zinc–oxide (IGZO) transistors, exhibiting extreme low leakage, is a promising memory technology with lower refresh power overhead. A long retention time in IGZO eDRAM can enable multilevel cell functionality, which can improve its efficacy in CIM applications. In this article, we explore a capacitorless IGZO eDRAM-based multilevel cell, capable of storing 1.5 bits/cell for CIM designs focused on deep neural network (DNN) inference applications. We perform a detailed design space exploration of IGZO eDRAM sensitivity to process temperature variations for read, write, and retention operations followed by architecture-level simulations comparing performance and energy for different workloads. The effectiveness of IGZO eDRAM-based CIM architecture is evaluated using a representative neural network, and the proposed approach achieves 82% Top-1 inference accuracy for the CIFAR-10 dataset, compared with 87% software accuracy with high bit cell storage density.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"35-43"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09815041.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46072256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-01DOI: 10.1109/JXCDC.2022.3143401
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
这些说明为编写本出版物的论文提供了指导。为在本期刊上发表文章的作者提供信息。
{"title":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Information for Authors","authors":"","doi":"10.1109/JXCDC.2022.3143401","DOIUrl":"https://doi.org/10.1109/JXCDC.2022.3143401","url":null,"abstract":"These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"C3-C3"},"PeriodicalIF":2.4,"publicationDate":"2022-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9903013/09916574.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49963529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-04-18DOI: 10.1109/JXCDC.2022.3168057
Cédric Marchand;Ian O’Connor;Mayeul Cantan;Evelyn T. Breyer;Stefan Slesazeck;Thomas Mikolajick
Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.
{"title":"A FeFET-Based Hybrid Memory Accessible by Content and by Address","authors":"Cédric Marchand;Ian O’Connor;Mayeul Cantan;Evelyn T. Breyer;Stefan Slesazeck;Thomas Mikolajick","doi":"10.1109/JXCDC.2022.3168057","DOIUrl":"10.1109/JXCDC.2022.3168057","url":null,"abstract":"Emerging nonvolatile memory technologies are attracting interest from the system design level to implement alternatives to conventional von-Neumann computing architectures. In particular, the hafnium oxide-based ferroelectric (FE) memory technology is fully CMOS-compatible and has already been used for logic-in-memory architectures or compact ternary content addressable memory (TCAM) cells. These enable the tight combination of different functionalities in the same circuit to reduce implementation area and energy consumption. In this article, we propose a new hybrid memory circuit that combines TCAM and normal memory capability: the Ternary Content addressable and MEMory (TC-MEM). A 1-bit TC-MEM circuit is proposed and discussed in detail, both as a concept and through its implementation in a 28-nm ferroelectric field-effect transistor (FeFET) technology. Measurement results demonstrate the circuit functionality. We also discuss how to scale it to multibit circuits, as well as its use both as a TCAM and as a normal memory allowing the implementation of reversible functions using one memory table instead of two memory tables, and in-memory-computing concepts.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"19-26"},"PeriodicalIF":2.4,"publicationDate":"2022-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09758734.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41615162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-23DOI: 10.1109/JXCDC.2022.3177588
Anni Lu;Yandong Luo;Shimeng Yu
Probabilistic machine learning plays a central role in the domains such as decision-making and autonomous control benefitting from its ability of representing and manipulating uncertainty about models and predictions. Until now, there are few hardware considerations to address the intensive computation and true random number generation for Bayesian neural network (BayesNN), whose weights are represented by probability distributions. In this article, we propose to apply the local reparameterization trick to alleviate the burden of random number generators (RNGs), which could be implemented by utilizing the inherent random noise of spin-orbit torque magnetic random access memory (SOT-MRAM). Sampling strategies are discussed to significantly reduce the number of operations and parameters of BayesNN. A device-circuit-system benchmark framework is then developed to evaluate the effects of device nonidealities such as the bias and variation of switching probability. The evaluation on the CIFAR-10 dataset suggests that BayesNN could achieve comparable accuracy as conventional deep neural network (DNN) with acceptable hardware overhead but provide much better uncertainty calibration with respect to out-of-distribution (OOD) inputs (rotated images as the example).
{"title":"An Algorithm-Hardware Co-Design for Bayesian Neural Network Utilizing SOT-MRAM’s Inherent Stochasticity","authors":"Anni Lu;Yandong Luo;Shimeng Yu","doi":"10.1109/JXCDC.2022.3177588","DOIUrl":"10.1109/JXCDC.2022.3177588","url":null,"abstract":"Probabilistic machine learning plays a central role in the domains such as decision-making and autonomous control benefitting from its ability of representing and manipulating uncertainty about models and predictions. Until now, there are few hardware considerations to address the intensive computation and true random number generation for Bayesian neural network (BayesNN), whose weights are represented by probability distributions. In this article, we propose to apply the local reparameterization trick to alleviate the burden of random number generators (RNGs), which could be implemented by utilizing the inherent random noise of spin-orbit torque magnetic random access memory (SOT-MRAM). Sampling strategies are discussed to significantly reduce the number of operations and parameters of BayesNN. A device-circuit-system benchmark framework is then developed to evaluate the effects of device nonidealities such as the bias and variation of switching probability. The evaluation on the CIFAR-10 dataset suggests that BayesNN could achieve comparable accuracy as conventional deep neural network (DNN) with acceptable hardware overhead but provide much better uncertainty calibration with respect to out-of-distribution (OOD) inputs (rotated images as the example).","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"27-34"},"PeriodicalIF":2.4,"publicationDate":"2022-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09780409.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46759180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-14DOI: 10.1109/JXCDC.2022.3143130
Hai Li;Dmitri E. Nikonov;Chia-Ching Lin;Kerem Camsari;Yu-Ching Liao;Chia-Sheng Hsu;Azad Naeemi;Ian A. Young
Spintronic devices provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. To accurately capture their multiphysics dynamics, a rigorous treatment of both spin and charge and their inter-conversion is required. Here, we present physics-based device models based on $4times4$ matrices for the spin-orbit coupling (SOC) part of the magneto-electric spin-orbit (MESO) device. Also, a more rigorous physics model of ferroelectric and magnetoelectric (ME) switching of ferromagnets, based on Landau–Lifshitz–Gilbert (LLG) and Landau–Khalatnikov (LK) equations, are presented. With the combined model implemented in a SPICE circuit simulator environment, simulation results were obtained which show feasibility of the MESO implementation and the functional operation of buffers, synchronous oscillators, and majority gates.
{"title":"Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits","authors":"Hai Li;Dmitri E. Nikonov;Chia-Ching Lin;Kerem Camsari;Yu-Ching Liao;Chia-Sheng Hsu;Azad Naeemi;Ian A. Young","doi":"10.1109/JXCDC.2022.3143130","DOIUrl":"10.1109/JXCDC.2022.3143130","url":null,"abstract":"Spintronic devices provide a promising beyond-complementary metal-oxide-semiconductor (CMOS) device option, thanks to their energy efficiency and compatibility with CMOS. To accurately capture their multiphysics dynamics, a rigorous treatment of both spin and charge and their inter-conversion is required. Here, we present physics-based device models based on \u0000<inline-formula> <tex-math>$4times4$ </tex-math></inline-formula>\u0000 matrices for the spin-orbit coupling (SOC) part of the magneto-electric spin-orbit (MESO) device. Also, a more rigorous physics model of ferroelectric and magnetoelectric (ME) switching of ferromagnets, based on Landau–Lifshitz–Gilbert (LLG) and Landau–Khalatnikov (LK) equations, are presented. With the combined model implemented in a SPICE circuit simulator environment, simulation results were obtained which show feasibility of the MESO implementation and the functional operation of buffers, synchronous oscillators, and majority gates.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"8 1","pages":"10-18"},"PeriodicalIF":2.4,"publicationDate":"2022-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9684158/09681806.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43377254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-30DOI: 10.1109/JXCDC.2021.3135720
Victor Zhirnov
The Decadal Plan for Semiconductors [1] has identified cryogenic computing as one of the research priorities that can help us meet the needs of future generations. Indeed, cryogenic semiconductor electronics is expected to have a rebirth due to advances in quantum computing, medical and scientific instrumentation, aviation, space exploration, and so on. Emerging materials and physics can be leveraged for new cryogenic device-inherent behavior that can have system-level benefits. Cryogenic semiconductor devices, including transistors, emerging resistive memories, and other device types as the basis, can innovate the entire computing stack from materials to systems and thus redefine how computation can be done. Looking forward, the realm of cryogenic electronics is inspired by the new and continually emerging understanding of cryogenic semiconductor physics applications.
{"title":"Special Topic on Cryogenic Semiconductor Devices and Circuits for Computing","authors":"Victor Zhirnov","doi":"10.1109/JXCDC.2021.3135720","DOIUrl":"10.1109/JXCDC.2021.3135720","url":null,"abstract":"The Decadal Plan for Semiconductors \u0000<xref>[1]</xref>\u0000 has identified cryogenic computing as one of the research priorities that can help us meet the needs of future generations. Indeed, cryogenic semiconductor electronics is expected to have a rebirth due to advances in quantum computing, medical and scientific instrumentation, aviation, space exploration, and so on. Emerging materials and physics can be leveraged for new cryogenic device-inherent behavior that can have system-level benefits. Cryogenic semiconductor devices, including transistors, emerging resistive memories, and other device types as the basis, can innovate the entire computing stack from materials to systems and thus redefine how computation can be done. Looking forward, the realm of cryogenic electronics is inspired by the new and continually emerging understanding of cryogenic semiconductor physics applications.","PeriodicalId":54149,"journal":{"name":"IEEE Journal on Exploratory Solid-State Computational Devices and Circuits","volume":"7 2","pages":"ii-iii"},"PeriodicalIF":2.4,"publicationDate":"2021-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/6570653/9650774/09666749.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41271591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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